prev_cmp_test.fit.qmsg

Altera-jtag0

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:01 " "Info: Finished register packing: elapsed time is 00:00:01" { { "Extra Info" "IFSAC_NUM_REGISTERS_PACKED_INTO_ATOM_TYPE" "68 I/O " "Extra Info: Packed 68 registers into blocks of type I/O" {  } {  } 1 0 "Packed %1!d! registers into blocks of type %2!s!" 0 0 "" 0} { "Extra Info" "IFSAC_NUM_REGISTERS_DUPLICATED" "34 " "Extra Info: Created 34 register duplicates" {  } {  } 1 0 "Created %1!d! register duplicates" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Warning" "WCUT_PLL_NON_ZDB_COMP_CLK_FEEDING_IO" "pll:inst1\|altpll:altpll_component\|pll compensate_clock 0 " "Warning: PLL \"pll:inst1\|altpll:altpll_component\|pll\" is in normal or source synchronous mode with output clock \"compensate_clock\" set to clk\[0\] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins" {  } { { "altpll.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } } { "pll.v" "" { Text "C:/EP2C5/www_sdram/pll.v" 88 0 0 } } { "test.bdf" "" { Schematic "C:/EP2C5/www_sdram/test.bdf" { { -80 408 648 80 "inst1" "" } } } }  } 0 0 "PLL \"%1!s!\" is in normal or source synchronous mode with output clock \"%2!s!\" set to clk\[%3!d!\] that is not fully compensated because it feeds an output pin -- only PLLs in zero delay buffer mode can fully compensate output pins" 0 0 "" 0}
{ "Warning" "WCUT_PLL_CLK_FEEDS_NON_DEDICATED_IO" "pll:inst1\|altpll:altpll_component\|pll clk\[0\] clk " "Warning: PLL \"pll:inst1\|altpll:altpll_component\|pll\" output port clk\[0\] feeds output pin \"clk\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "e:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } } { "pll.v" "" { Text "C:/EP2C5/www_sdram/pll.v" 88 0 0 } } { "test.bdf" "" { Schematic "C:/EP2C5/www_sdram/test.bdf" { { -80 408 648 80 "inst1" "" } } } } { "test.bdf" "" { Schematic "C:/EP2C5/www_sdram/test.bdf" { { -24 784 960 -8 "clk" "" } } } }  } 0 0 "PLL \"%1!s!\" output port %2!s! feeds output pin \"%3!s!\" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "14.384 ns register register " "Info: Estimated most critical path is register to register delay of 14.384 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns nios:inst\|cpu:the_cpu\|W_alu_result\[24\] 1 REG LAB_X18_Y8 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X18_Y8; Fanout = 5; REG Node = 'nios:inst\|cpu:the_cpu\|W_alu_result\[24\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { nios:inst|cpu:the_cpu|W_alu_result[24] } "NODE_NAME" } } { "cpu.v" "" { Text "C:/EP2C5/www_sdram/cpu.v" 4771 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.327 ns) + CELL(0.647 ns) 1.974 ns nios:inst\|sysid_control_slave_arbitrator:the_sysid_control_slave\|cpu_data_master_granted_sysid_control_slave~151 2 COMB LAB_X14_Y6 2 " "Info: 2: + IC(1.327 ns) + CELL(0.647 ns) = 1.974 ns; Loc. = LAB_X14_Y6; Fanout = 2; COMB Node = 'nios:inst\|sysid_control_slave_arbitrator:the_sysid_control_slave\|cpu_data_master_granted_sysid_control_slave~151'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.974 ns" { nios:inst|cpu:the_cpu|W_alu_result[24] nios:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~151 } "NODE_NAME" } } { "nios.v" "" { Text "C:/EP2C5/www_sdram/nios.v" 2842 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.918 ns) + CELL(0.614 ns) 3.506 ns nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_data_master_requests_cpu_jtag_debug_module~261 3 COMB LAB_X14_Y8 2 " "Info: 3: + IC(0.918 ns) + CELL(0.614 ns) = 3.506 ns; Loc. = LAB_X14_Y8; Fanout = 2; COMB Node = 'nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_data_master_requests_cpu_jtag_debug_module~261'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.532 ns" { nios:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~151 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module~261 } "NODE_NAME" } } { "nios.v" "" { Text "C:/EP2C5/www_sdram/nios.v" 69 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.160 ns) + CELL(0.650 ns) 4.316 ns nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_data_master_qualified_request_cpu_jtag_debug_module 4 COMB LAB_X14_Y8 11 " "Info: 4: + IC(0.160 ns) + CELL(0.650 ns) = 4.316 ns; Loc. = LAB_X14_Y8; Fanout = 11; COMB Node = 'nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_data_master_qualified_request_cpu_jtag_debug_module'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.810 ns" { nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module~261 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_qualified_request_cpu_jtag_debug_module } "NODE_NAME" } } { "nios.v" "" { Text "C:/EP2C5/www_sdram/nios.v" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.650 ns) 5.466 ns nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_grant_vector\[1\]~55 5 COMB LAB_X15_Y8 35 " "Info: 5: + IC(0.500 ns) + CELL(0.650 ns) = 5.466 ns; Loc. = LAB_X15_Y8; Fanout = 35; COMB Node = 'nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_grant_vector\[1\]~55'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.150 ns" { nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_qualified_request_cpu_jtag_debug_module nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_grant_vector[1]~55 } "NODE_NAME" } } { "nios.v" "" { Text "C:/EP2C5/www_sdram/nios.v" 138 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.693 ns) + CELL(0.206 ns) 7.365 ns nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_address\[1\]~128 6 COMB LAB_X19_Y7 33 " "Info: 6: + IC(1.693 ns) + CELL(0.206 ns) = 7.365 ns; Loc. = LAB_X19_Y7; Fanout = 33; COMB Node = 'nios:inst\|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module\|cpu_jtag_debug_module_address\[1\]~128'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.899 ns" { nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_grant_vector[1]~55 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[1]~128 } "NODE_NAME" } } { "nios.v" "" { Text "C:/EP2C5/www_sdram/nios.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.888 ns) + CELL(0.370 ns) 9.623 ns nios:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|Equal0~71 7 COMB LAB_X14_Y8 23 " "Info: 7: + IC(1.888 ns) + CELL(0.370 ns) = 9.623 ns; Loc. = LAB_X14_Y8; Fanout = 23; COMB Node = 'nios:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg\|Equal0~71'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.258 ns" { nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[1]~128 nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~71 } "NODE_NAME" } } { "cpu.v" "" { Text "C:/EP2C5/www_sdram/cpu.v" 508 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.299 ns) + CELL(0.624 ns) 11.546 ns nios:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|readdata\[18\]~1298 8 COMB LAB_X12_Y7 2 " "Info: 8: + IC(1.299 ns) + CELL(0.624 ns) = 11.546 ns; Loc. = LAB_X12_Y7; Fanout = 2; COMB Node = 'nios:inst\|cpu:the_cpu\|cpu_nios2_oci:the_cpu_nios2_oci\|readdata\[18\]~1298'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.923 ns" { nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~71 nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[18]~1298 } "NODE_NAME" } } { "cpu.v" "" { Text "C:/EP2C5/www_sdram/cpu.v" 2887 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.857 ns) + CELL(0.589 ns) 12.992 ns nios:inst\|cpu:the_cpu\|av_ld_byte2_data\[2\]~21 9 COMB LAB_X10_Y7 1 " "Info: 9: + IC(0.857 ns) + CELL(0.589 ns) = 12.992 ns; Loc. = LAB_X10_Y7; Fanout = 1; COMB Node = 'nios:inst\|cpu:the_cpu\|av_ld_byte2_data\[2\]~21'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.446 ns" { nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[18]~1298 nios:inst|cpu:the_cpu|av_ld_byte2_data[2]~21 } "NODE_NAME" } } { "cpu.v" "" { Text "C:/EP2C5/www_sdram/cpu.v" 4726 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.284 ns) + CELL(0.108 ns) 14.384 ns nios:inst\|cpu:the_cpu\|av_ld_byte2_data\[2\] 10 REG LAB_X10_Y6 2 " "Info: 10: + IC(1.284 ns) + CELL(0.108 ns) = 14.384 ns; Loc. = LAB_X10_Y6; Fanout = 2; REG Node = 'nios:inst\|cpu:the_cpu\|av_ld_byte2_data\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.392 ns" { nios:inst|cpu:the_cpu|av_ld_byte2_data[2]~21 nios:inst|cpu:the_cpu|av_ld_byte2_data[2] } "NODE_NAME" } } { "cpu.v" "" { Text "C:/EP2C5/www_sdram/cpu.v" 4726 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.458 ns ( 30.99 % ) " "Info: Total cell delay = 4.458 ns ( 30.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.926 ns ( 69.01 % ) " "Info: Total interconnect delay = 9.926 ns ( 69.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.384 ns" { nios:inst|cpu:the_cpu|W_alu_result[24] nios:inst|sysid_control_slave_arbitrator:the_sysid_control_slave|cpu_data_master_granted_sysid_control_slave~151 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_requests_cpu_jtag_debug_module~261 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_data_master_qualified_request_cpu_jtag_debug_module nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_grant_vector[1]~55 nios:inst|cpu_jtag_debug_module_arbitrator:the_cpu_jtag_debug_module|cpu_jtag_debug_module_address[1]~128 nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_nios2_avalon_reg:the_cpu_nios2_avalon_reg|Equal0~71 nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|readdata[18]~1298 nios:inst|cpu:the_cpu|av_ld_byte2_data[2]~21 nios:inst|cpu:the_cpu|av_ld_byte2_data[2] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}