test.fit.rpt

Altera-jtag0

; Total registers                    ; 1066                                     ;
; Total pins                         ; 46 / 142 ( 32 % )                        ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 75,776 / 119,808 ( 63 % )                ;
; Embedded Multiplier 9-bit elements ; 0 / 26 ( 0 % )                           ;
; Total PLLs                         ; 1 / 2 ( 50 % )                           ;
+------------------------------------+------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                         ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; EP2C5Q208C8                    ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
; Maximum processors allowed for parallel compilation                   ; 1                              ; 1                              ;
; Use TimeQuest Timing Analyzer                                         ; Off                            ; Off                            ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                           ; Off                            ; Off                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; Equivalent RAM and MLAB Paused Read Capabilities                      ; Care                           ; Care                           ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                         ;
+--------------------------------------------+-----------------+------------------+----------------------------------------+-----------+----------------+---------------------------------------------------+------------------+-----------------------+
; Node                                       ; Action          ; Operation        ; Reason                                 ; Node Port ; Node Port Name ; Destination Node                                  ; Destination Port ; Destination Port Name ;
+--------------------------------------------+-----------------+------------------+----------------------------------------+-----------+----------------+---------------------------------------------------+------------------+-----------------------+
; nios:inst|sdram:the_sdram|m_addr[0]        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ;                ; add[0]                                            ; DATAIN           ;                       ;
; nios:inst|sdram:the_sdram|m_addr[1]        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ;                ; add[1]                                            ; DATAIN           ;                       ;
; nios:inst|sdram:the_sdram|m_addr[2]        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ;                ; add[2]                                            ; DATAIN           ;                       ;
; nios:inst|sdram:the_sdram|m_addr[3]        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ;                ; add[3]                                            ; DATAIN           ;                       ;
; nios:inst|sdram:the_sdram|m_addr[4]        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ;                ; add[4]                                            ; DATAIN           ;                       ;
; nios:inst|sdram:the_sdram|m_addr[5]        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ;                ; add[5]                                            ; DATAIN           ;                       ;
; nios:inst|sdram:the_sdram|m_addr[6]        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ;                ; add[6]                                            ; DATAIN           ;                       ;
; nios:inst|sdram:the_sdram|m_addr[7]        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ;                ; add[7]                                            ; DATAIN           ;                       ;
; nios:inst|sdram:the_sdram|m_addr[8]        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ;                ; add[8]                                            ; DATAIN           ;                       ;
; nios:inst|sdram:the_sdram|m_addr[9]        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ;                ; add[9]                                            ; DATAIN           ;                       ;
; nios:inst|sdram:the_sdram|m_addr[10]       ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ;                ; add[10]                                           ; DATAIN           ;                       ;
; nios:inst|sdram:the_sdram|m_addr[11]       ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ;                ; add[11]                                           ; DATAIN           ;                       ;
; nios:inst|sdram:the_sdram|m_bank[0]        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ;                ; ba[0]                                             ; DATAIN           ;                       ;
; nios:inst|sdram:the_sdram|m_bank[1]        ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ;                ; ba[1]                                             ; DATAIN           ;                       ;
; nios:inst|sdram:the_sdram|m_cmd[0]         ; Packed Register ; Register Packing ; Fast Output Register assignment        ; REGOUT    ;                ; we                                                ; DATAIN           ;                       ;
; nios:inst|sdram:the_sdram|m_cmd[0]         ; Duplicated      ; Register Packing ; Fast Output Register assignment        ; REGOUT    ;                ; nios:inst|sdram:the_sdram|m_cmd[0]~_Duplicate_1   ; REGOUT           ;                       ;
; nios:inst|sdram:the_sdram|m_cmd[0]         ; Inverted        ; Register Packing ; Fast Output Register assignment        ;           ;                ;                                                   ;                  ;                       ;