test.tan.rpt

Altera-jtag0

; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+---------------------------------------------+-----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Type                                        ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                    ; To                                                                                                                                                                            ; From Clock                   ; To Clock                     ; Failed Paths ;
+---------------------------------------------+-----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+
; Worst-case tsu                              ; N/A       ; None                             ; 7.949 ns                         ; altera_internal_jtag~SHIFTUSER                                                          ; nios:inst|cpu:the_cpu|cpu_nios2_oci:the_cpu_nios2_oci|cpu_jtag_debug_module_wrapper:the_cpu_jtag_debug_module_wrapper|cpu_jtag_debug_module:the_cpu_jtag_debug_module1|sr[11] ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Worst-case tco                              ; N/A       ; None                             ; 10.058 ns                        ; nios:inst|pio:the_pio|data_out[0]                                                       ; pio[0]                                                                                                                                                                        ; sysclk                       ; --                           ; 0            ;
; Worst-case tpd                              ; N/A       ; None                             ; 3.106 ns                         ; altera_internal_jtag~TDO                                                                ; altera_reserved_tdo                                                                                                                                                           ; --                           ; --                           ; 0            ;
; Worst-case th                               ; N/A       ; None                             ; 3.649 ns                         ; altera_internal_jtag~TMSUTAP                                                            ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[13]                                                                                                      ; --                           ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Setup: 'sysclk'                       ; 34.428 ns ; 20.00 MHz ( period = 50.000 ns ) ; 64.22 MHz ( period = 15.572 ns ) ; nios:inst|cpu:the_cpu|F_pc[18]                                                          ; nios:inst|cpu:the_cpu|av_ld_byte0_data[2]                                                                                                                                     ; sysclk                       ; sysclk                       ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP' ; N/A       ; None                             ; 79.08 MHz ( period = 12.646 ns ) ; sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_aoi:auto_generated|dffe1a[0] ; sld_hub:sld_hub_inst|hub_tdo_reg                                                                                                                                              ; altera_internal_jtag~TCKUTAP ; altera_internal_jtag~TCKUTAP ; 0            ;
; Clock Hold: 'sysclk'                        ; 0.499 ns  ; 20.00 MHz ( period = 50.000 ns ) ; N/A                              ; nios:inst|sdram:the_sdram|i_cmd[3]                                                      ; nios:inst|sdram:the_sdram|i_cmd[3]                                                                                                                                            ; sysclk                       ; sysclk                       ; 0            ;
; Total number of failed paths                ;           ;                                  ;                                  ;                                                                                         ;                                                                                                                                                                               ;                              ;                              ; 0            ;
+---------------------------------------------+-----------+----------------------------------+----------------------------------+-----------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------+------------------------------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                                     ;
+----------------------------------------------------------------+--------------------+------+------------+------------------------------------+
; Option                                                         ; Setting            ; From ; To         ; Entity Name                        ;
+----------------------------------------------------------------+--------------------+------+------------+------------------------------------+
; Device Name                                                    ; EP2C5Q208C8        ;      ;            ;                                    ;
; Timing Models                                                  ; Final              ;      ;            ;                                    ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;            ;                                    ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;            ;                                    ;
; Cut off read during write signal paths                         ; On                 ;      ;            ;                                    ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;            ;                                    ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;            ;                                    ;
; Ignore Clock Settings                                          ; Off                ;      ;            ;                                    ;
; Analyze latches as synchronous elements                        ; On                 ;      ;            ;                                    ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;            ;                                    ;
; Enable Clock Latency                                           ; Off                ;      ;            ;                                    ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;            ;                                    ;
; Number of source nodes to report per destination node          ; 10                 ;      ;            ;                                    ;
; Number of destination nodes to report                          ; 10                 ;      ;            ;                                    ;
; Number of paths to report                                      ; 200                ;      ;            ;                                    ;
; Report Minimum Timing Checks                                   ; Off                ;      ;            ;                                    ;
; Use Fast Timing Models                                         ; Off                ;      ;            ;                                    ;
; Report IO Paths Separately                                     ; Off                ;      ;            ;                                    ;
; Perform Multicorner Analysis                                   ; On                 ;      ;            ;                                    ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;            ;                                    ;
; Maximum Delay                                                  ; 100 ns             ;      ; data_in_d1 ; nios_reset_clk_domain_synch_module ;
+----------------------------------------------------------------+--------------------+------+------------+------------------------------------+