ln97xend.h

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/* ln97xEnd.h - END based AMD LANCE Ethernet header */

/* Copyright 1998-2000 Wind River Systems, Inc. */
/* Copyright 1998 CETIA Inc. */
/*

modification history
--------------------
01c,11jun00,ham  removed reference to etherLib.
01b,19may00,pai  Implemented accumulated driver bug fixes (SPR #31349).
01a,07dec98,snk	added support 7997x[012] across architectures.
		written from 01b of lnPciEnd.h
*/

#ifndef __INCln97xEndh
#define __INCln97xEndh

#ifdef __cplusplus
extern "C" {
#endif

#ifndef _ASMLANGUAGE

#include "end.h"
#include "cacheLib.h"
#include "netinet/if_ether.h"

#if FALSE
#define DRV_DEBUG	/* temporary should be taken out */
#endif    

/* define the various levels of debugging if the DRV_DEBUG is defined */    

#ifdef	DRV_DEBUG
#include "logLib.h"
#define DRV_DEBUG_OFF		0x0000
#define DRV_DEBUG_RX		0x0001
#define	DRV_DEBUG_TX		0x0002
#define DRV_DEBUG_INT		0x0004
#define	DRV_DEBUG_POLL		(DRV_DEBUG_POLL_RX | DRV_DEBUG_POLL_TX)
#define	DRV_DEBUG_POLL_RX	0x0008
#define	DRV_DEBUG_POLL_TX	0x0010
#define	DRV_DEBUG_LOAD		0x0020
#define	DRV_DEBUG_LOAD2		0x0040
#define	DRV_DEBUG_IOCTL		0x0080
#define	DRV_DEBUG_RESET		0x0100
#define	DRV_DEBUG_MCAST		0x0200
#define	DRV_DEBUG_CSR		0x0400
#define DRV_DEBUG_RX_PKT        0x0800
#define DRV_DEBUG_POLL_REDIR	0x10000
#define	DRV_DEBUG_LOG_NVRAM	0x20000
#define DRV_DEBUG_ALL           0xfffff
#endif /* DRV_DEBUG */

/* board level/bus specific and architecture specific macros */

#if _BYTE_ORDER==_BIG_ENDIAN
#   define PCI_SWAP(x)	LONGSWAP((int)(x))
#else
#   define PCI_SWAP(x)	(x)
#endif

/* device IO or memory mapped accessa and data registers */

#define LN_97X_RDP	((UINT32 *)((UINT32)(pDrvCtrl->devAdrs) + 0x10))
#define LN_97X_RAP	((UINT32 *)((UINT32)(pDrvCtrl->devAdrs) + 0x14))
#define LN_97X_RST	((UINT32 *)((UINT32)(pDrvCtrl->devAdrs) + 0x18))
#define LN_97X_BDP	((UINT32 *)((UINT32)(pDrvCtrl->devAdrs) + 0x1C))

/* csr and bcr addresses */

#define CSR(x)                  (x)
#define BCR(x)                  (x)

/* Definitions for fields and bits in the LN_DEVICE */

#define CSR0_ERR		0x8000	/* (RO) err flg (BABL|CERR|MISS|MERR) */
#define CSR0_BABL		0x4000	/* (RC) babble transmitter timeout */
#define CSR0_CERR		0x2000	/* (RC) collision error */
#define CSR0_MISS		0x1000	/* (RC) missed packet */
#define CSR0_MERR		0x0800	/* (RC) memory error */
#define CSR0_RINT		0x0400	/* (RC) receiver interrupt */
#define CSR0_TINT		0x0200	/* (RC) transmitter interrupt */
#define CSR0_IDON		0x0100	/* (RC) initialization done */
#define CSR0_INTR		0x0080	/* (RO) interrupt flag */
#define CSR0_INEA		0x0040	/* (RW) interrupt enable */
#define CSR0_RXON		0x0020	/* (RO) receiver on */
#define CSR0_TXON		0x0010	/* (RO) transmitter on */
#define CSR0_TDMD		0x0008	/* (WOO)transmit demand */
#define CSR0_STOP		0x0004	/* (WOO)stop (& reset) chip */
#define CSR0_STRT		0x0002	/* (RW) start chip */
#define CSR0_INIT		0x0001	/* (RW) initialize (acces init block) */

#define CSR0_INTMASK 		(CSR0_BABL | CSR0_CERR | CSR0_MISS | \
			         CSR0_MERR | CSR0_RINT | CSR0_TINT | \
                                 CSR0_IDON | CSR0_INEA)

#define CSR3_DXSUFLO		0x0040	/* disable transmit stop on UFLO */
#define	CSR3_BSWP		0x0004	/* Byte Swap */

/* CSR 4 test and features control */

#define CSR4_EN124		0x8000	/* enable CSR124 access */
#define CSR4_DMAPLUS		0x4000	/* disable DMA burst xfer counter */
#define CSR4_TIMER		0x2000	/* enable bus activity timer */
#define CSR4_DPOLL		0x1000	/* disable transmit polling */
#define CSR4_APAD_XMIT		0x0800	/* enable auto pad transmit */
#define CSR4_ASTRP_RCV		0x0400	/* enable auto pad stripping */
#define CSR4_MFCO		0x0200	/* missed frame counter overflow */
#define CSR4_MFCOM		0x0100	/* missed frame counter mask */
#define CSR4_UINTCMD		0x0080	/* user interrupt command */
#define CSR4_UINT		0x0040	/* user interrupt issued */
#define CSR4_RCVCC0		0x0020	/* receive collision cntr overflow */
#define CSR4_RCVCCOM		0x0010	/* receive collision cntr mask */
#define CSR4_TXSTRT		0x0008	/* transmit start status */
#define CSR4_TXSTRTM		0x0004	/* transmit start mask */
#define CSR4_JAB		0x0002	/* jabber error indicated */
#define CSR4_JABM		0x0001	/* jabber error mask */

#define CSR4_TFC_MASK		(CSR4_MFCOM | CSR4_RCVCCOM | \
                                 CSR4_TXSTRTM | CSR4_JABM)

/* CSR 15 mode register - loaded from initialization block */

#define CSR15_PROM          0x00008000	/* set promiscuous mode */
#define CSR15_DTX           0x00000002	/* disable transmitter section */
#define CSR15_DRX           0x00000001	/* disable receiver section */

/* CSR 88 and CSR 89 chip ID registers */

#define CSR88_VERS_MSK      0xf0000000	/* (RO) silicon revision mask */
#define CSR88_PART_MSK      0x0000f000	/* (RO) part ID lower mask */
#define CSR88_MANF_MSK      0x00000fff	/* (RO) manufacturer's ID mask */

#define CSR89_RESV_MSK      0xffff0000	/* (RO) reserved fields mask */
#define CSR89_VERS_MSK      0x0000f000	/* (RO) silicon revision mask */
#define CSR89_PART_MSK      0x00000fff	/* (RO) part ID upper mask */

#define LN97X_MANFID_AMD    0x00000003	/* AMD manufacturer's ID  value */
#define LN970_PARTID_LO     0x00001000	/* Am79c970 part id lower value */ 
#define LN971_PARTID_LO     0x00003000	/* Am79c971 part id lower value */
#define LN972_PARTID_LO     0x00004000	/* Am79c972 part id lower value */

/* BCR 2 */

#define BCR2_LEDPE		0x1000	/* LED program enable */
#define BCR2_AUTO_SELECT	0x0002	/* auto select port type 10BT/AUI */

/* BCR 18 burst size and bus control register */

#define BCR18_ROMTMG		0x9000	/* expansion ROM timing (default) */
#define BCR18_MEMCMD		0x0200	/* enable PCI memory read multiple */
#define BCR18_BREADE		0x0040	/* burst read enable (SWSTYLE=3) */
#define BCR18_BWRITE		0x0020	/* burst write enable (SWSTYLE=3) */
#define BCR18_RESRVD		0x0001	/* reserved location (default) */

#define BCR18_BSBC_MASK		(BCR18_ROMTMG | BCR18_RESRVD | \
                                 BCR18_BREADE | BCR18_BWRITE)

/* BCR 20 software style register */
    
#define BCR20_SSIZE32		0x0100
#define BCR20_SWSTYLE_LANCE	0x0000
#define BCR20_SWSTYLE_ILACC	0x0001
#define BCR20_SWSTYLE_PCNET	0x0002
#define BCR20_SWSTYLE_PCNET_II	0x0003
    
/* Control block definitions for AMD LANCE (Ethernet) chip. */

typedef struct
    {
    ULONG       rdp;            /* register data Port */
    ULONG       rap;            /* Register Address Port */
    ULONG       rst;            /* Reset Register */
    ULONG       bdp;            /* Bus Configuration Register Data Port */
    } LN_DEVICE;

/* Initialization Block */

typedef struct lnIB
    {
    ULONG       lnIBMode;	/* mode register */
    UCHAR       lnIBPadr [8];   /* PADR: bswapd ethnt phys address */
    UCHAR       lnIBLadrf [8];  /* logical address filter */
    ULONG       lnIBRdra;       /* RDRA: read ring address, long word */
    ULONG       lnIBTdra;       /* TDRA: transmit ring address long word */
    } LN_IB;

/* Receive Message Descriptor Entry.*/

typedef struct lnRMD
    {
    ULONG       lnRMD2;         /* message byte count */
    ULONG       lnRMD1;         /* status & buffer byte count (negative) */
    ULONG       lnRMD0;         /* bits 31:00 of receive buffer address */
    ULONG       lnRMD3;         /* reserved */
    } LN_RMD;

/* Transmit Message Descriptor Entry. */

typedef struct lnTMD
    {
    ULONG       lnTMD2;         /* errors */
    ULONG       lnTMD1;         /* message byte count */
    ULONG       lnTMD0;         /* bits 31:00 of transmit buffer address */
    ULONG       lnTMD3;         /* reserved */
    } LN_TMD;

/* initialization block */

#define IB_MODE_TLEN_MSK	0xf0000000
#define IB_MODE_RLEN_MSK	0x00f00000

/* receive descriptor */

#define RMD1_OWN		0x80000000	/* Own */
#define RMD1_ERR		0x40000000	/* Error */
#define RMD1_FRAM		0x20000000	/* Framming Error */
#define RMD1_OFLO		0x10000000	/* Overflow */
#define RMD1_CRC		0x08000000	/* CRC */
#define RMD1_BUFF		0x04000000	/* Buffer Error */
#define RMD1_STP		0x02000000	/* Start of Packet */
#define RMD1_ENP		0x01000000	/* End of Packet */
#define RMD1_RES		0x00ff0000	/* reserved */
#define RMD1_CNST		0x0000f000	/* rmd1 constant value */

#define RMD1_BCNT_MSK		0x00000fff	/* buffer cnt mask */
#define RMD2_MCNT_MSK		0x00000fff	/* message buffer cnt mask */

/* transmit descriptor */

#define TMD1_OWN		0x80000000	/* Own */
#define TMD1_ERR		0x40000000	/* Error */
#define TMD1_MORE		0x10000000	/* More than One Retry */
#define TMD1_ONE		0x08000000	/* One Retry */
#define TMD1_DEF		0x04000000	/* Deferred */
#define TMD1_STP		0x02000000	/* Start of Packet */
#define TMD1_ENP		0x01000000	/* End of Packet */
#define TMD1_BPE                0x00800000      /* Bus Parity Error */
#define TMD1_RES		0x007F0000	/* Reserved locations */
#define TMD1_CNST		0x0000f000	/* tmd1 constant value */

#define TMD2_BUFF		0x80000000	/* Buffer Error */
#define TMD2_UFLO		0x40000000	/* Underflow Error */
#define TMD2_LCOL		0x10000000	/* Late Collision */
#define TMD2_LCAR		0x08000000	/* Lost Carrier */
#define TMD2_RTRY		0x04000000	/* Retry Error */
#define TMD2_TDR		0x03FF0000	/* Time Domain Reflectometry */

#define TMD1_BCNT_MSK		0x00000fff	/* buffer cnt mask */

#define	rBufAddr		lnRMD0
#define	rBufRmd1		lnRMD1
#define	rBufMskCnt		lnRMD2
#define rBufRmd3		lnRMD3

#define	tBufAddr		lnTMD0
#define tBufTmd1		lnTMD1
#define tBufTmd2		lnTMD2
#define tBufTmd3		lnTMD3

/* CRC for logical address filter */

#define LN_CRC_POLYNOMIAL	0xedb88320	/* CRC polynomial */
#define LN_CRC_TO_LAF_IX(crc)	((crc) >> 26)	/* get 6 MSBits */
#define LN_LAF_LEN		8    		/* logical addr filter legth */
#define LN_LA_LEN		6		/* logical address length */

/* Definitions for the drvCtrl specific flags field */

#define LS_PROMISCUOUS_FLAG     0x1	/* set the promiscuous mode */
#define LS_MEM_ALLOC_FLAG       0x2	/* allocating memory flag */
#define LS_PAD_USED_FLAG        0x4	/* padding used flag */
#define LS_RCV_HANDLING_FLAG    0x8	/* handling recv packet */
#define LS_START_OUTPUT_FLAG    0x10	/* trigger output flag */
#define LS_POLLING              0x20	/* polling flag */
#define LS_MODE_MEM_IO_MAP	0x100   /* device registers memory mapped */
#define LS_MODE_DWIO		0x200   /* device in 32 bit mode */