if_fei.h

Tornado 2.0.2 source code!vxworks的源代码

    {
    UINT8		ccByte0;	/* byte count */
    UINT8		ccByte1;	/* FIFO limits */
    UINT8		ccByte2;	/* adaptive IFS */
    UINT8		ccByte3;	/* reserved - set to 0 */
    UINT8		ccByte4;	/* rx max byte count */
    UINT8		ccByte5;	/* tx max byte count, byte cnt enable */
    UINT8		ccByte6;	/* save bf, CI/TNO int, late SCB */
    UINT8		ccByte7;	/* underrun retry, short discard */
    UINT8		ccByte8;	/* 503/MII */
    UINT8		ccByte9;	/* reserved - set to 0 */
    UINT8		ccByte10;	/* loopback, reamble, NSAI */
    UINT8		ccByte11;	/* linear priority */
    UINT8		ccByte12;	/* interframe spacing, L. pri mode */
    UINT8		ccByte13;	/* reserved - set to 0 */
    UINT8		ccByte14;	/* reserved - set to 0xf2 */
    UINT8		ccByte15;	/* CRS+CDT, Broadcast, promisc  */
    UINT8		ccByte16;	/* reserved - set to 0 */
    UINT8		ccByte17;	/* reserved - set to 0x40 */
    UINT8		ccByte18;	/* CRC, padding, stripping */
    UINT8		ccByte19;	/* full duplex, force full duplex */
    UINT8		ccByte20;	/* multi IA */
    UINT8		ccByte21;	/* multicast */
    } AC_CONFIG;

typedef struct ac_mcast 	/* AC_MCAST - Mulitcast Setup */
    {
    UINT16		cmMcCount;	/* the number of bytes in MC list */
    UINT8		cmAddrList[6 * N_MCAST];/* mulitcast address list */
    } AC_MCAST;

typedef struct ac_tcb 		/* AC_TCB - Transmit Control Blocks */
    {
    FEI_LINK		pTBD;		/* link to tx buf desc array */
    UINT16		count;		/* length of data */
    UINT8		txThresh;	/* tx threshold */
    UINT8		tbdNum;		/* tx buf desc number */
    UINT8		enetHdr [EH_SIZE];/* the ethernet header */
    char		enetData [ETHERMTU];/* transmit data */
    UINT16		ccFill;		/* padding */
    } AC_TCB;

/* special TCB-specific command block bit mask definitions */

#define CFD_S_TX_DMA_U	0x1000		/* DMA underrun */
#define TCB_CNT_EOF	0x8000		/* all data kept in TFD */
#define CFD_C_TX_FLEX	0x0008		/* use flexible mode */

typedef struct ac_dump 		/* AC_DUMP - Dump */
    {
    FEI_LINK		bufAddr; 	/* address of dump buffer */
    } AC_DUMP;

/* special Diag-specific command block bit mask definitions */

#define CFD_S_DIAG_F	0x0800		/* diag failed */

/* Command Frame Description and defines */

typedef struct cfd 		/* CFD - Command Frame Descriptor */
    {
    volatile UINT16	cfdStatus;	/* command status field */
    UINT16		cfdCommand;	/* command field */
    FEI_LINK		link;		/* address of next CB */
    union 				/* command dependent section */
	{
	struct ac_iasetup	cfd_iasetup;	/* IA setup */
	struct ac_config	cfd_config;	/* config */
	struct ac_mcast		cfd_mcast;	/* multicast setup */
	struct ac_tcb		cfd_tcb;	/* transmit */
	struct ac_dump		cfd_dump;	/* dump */
	} cfd_cmd;
    struct cfd *	pPrev;		/* previos CFD */
    } CFD;

#define cfdIASetup	cfd_cmd.cfd_iasetup
#define cfdConfig	cfd_cmd.cfd_config
#define cfdMcast 	cfd_cmd.cfd_mcast
#define cfdTcb	 	cfd_cmd.cfd_tcb
#define cfdDump 	cfd_cmd.cfd_dump

/* Action Status Word bit mask definitions */

#define CFD_S_OK	0x2000		/* Command completed successfully */
#define CFD_S_B         0x4000          /* CU starts access this CFD */
#define CFD_S_COMPLETE	0x8000		/* Command complete */

/* Action Command Word bit mask definitions */

#define CFD_C_NOP	0x0000		/* No Operation */
#define CFD_C_IASETUP	0x0001		/* Individual Address Setup */
#define CFD_C_CONFIG	0x0002		/* Configure Chip */
#define CFD_C_MASETUP	0x0003		/* Multicast Setup */
#define CFD_C_XMIT	0x0004		/* Transmit (see below too ...) */
#define CFD_C_DUMP	0x0006		/* Dump Registers */
#define CFD_C_DIAG	0x0007		/* Diagnose */
#define CFD_C_INT	0x2000		/* 557 interrupts CPU after execution */
#define CFD_C_SUSP	0x4000		/* CU should suspend after execution */
#define CFD_C_EL	0x8000		/* End of command list */

/* 82557 Receive Frame Descriptors */

typedef struct rfd 		/* RFD - Receive Frame Descriptor */
    {
    volatile UINT16	rfdStatus;	/* status field */
    UINT16		rfdCommand;	/* command field */
    FEI_LINK		link;		/* link to next rfd */
    FEI_LINK		pRBD;		/* link to rx buf desc array */
    volatile UINT16	actualCnt;	/* actual byte count */
    UINT16		bufSize;	/* buffer size */
    UINT8		enetHdr [EH_SIZE];/* the ethernet header */
    char		enetData [ETHERMTU];/* received data */
    UINT8		refCnt;		/* reference count */
    UINT8		ccFill;		/* padding */
    struct rfd *	pPrev;		/* previos RFD */
    } RFD;

/* RFD bit mask definitions */

#define RFD_S_COLL	0x0001		/* collision during reception */
#define RFD_S_IA	0x0002		/* individual address match */
#define RFD_S_RXER	0x0010		/* receive error */
#define RFD_S_LEN	0x0020		/* type/len field designator */
#define RFD_S_SHORT	0x0080		/* frame too short */
#define RFD_S_DMA	0x0100		/* DMA Overrun failure to get bus */
#define RFD_S_RSRC	0x0200		/* received, but ran out of buffers */
#define RFD_S_ALGN	0x0400		/* received misaligned with CRC error */
#define RFD_S_CRC	0x0800		/* received with CRC error */
#define RFD_S_OK	0x2000		/* frame received successfully */
#define RFD_S_B         0x4000          /* RU begins accessing this RFD */
#define RFD_S_COMPLETE	0x8000		/* frame reception complete */

#define RFD_C_FLEX	0x0008		/* flexible mode */
#define RFD_C_HEADER	0x0010		/* frame is a header */
#define RFD_C_SUSP	0x4000		/* suspend RU after receiving frame */
#define RFD_C_EL	0x8000		/* end of RFD list */

#define RFD_CNT_F	0x4000		/* actual count updated */
#define RFD_CNT_EOF	0x8000		/* end of frame */

/* EEPROM bit definitions */

#define FEI_EESK	0x01		/* EEPROM shift clock */
#define FEI_EECS	0x02		/* EEPROM chip select */
#define FEI_EEDI	0x04		/* EEPROM data in */
#define FEI_EEDO	0x08		/* EEPROM data out */


/* Following defines should be in another header file */

/* MDI definitions */

#define MDI_READ   0x2
#define MDI_WRITE  0x1
#define MDI_CTRL_REG   0x0
#define MDI_STATUS_REG 0x1

/* MDI control register bit  */
#define MDI_CR_COLL_TEST            0x80
#define MDI_CR_FDX                  0x100       /* FDX =1, half duplex =0 */
#define MDI_CR_RESTART              0x200       /* restart auto negotiation */
#define MDI_CR_ISOLATE              0x400       /* isolate PHY from MII */
#define MDI_CR_POWER_DOWN           0x800       /* power down */
#define MDI_CR_SELECT               0x1000      /* auto speed select  */
#define MDI_CR_100                  0x2000      /* 0 = 10mb, 1 = 100mb */
#define MDI_CR_LOOPBACK             0x4000      /* 0 = normal, 1 = loopback */
#define MDI_CR_RESET                0x8000      /* 0 = normal, 1 = PHY reset */

/* MDI Status register bit definitions */
#define MDI_SR_LINK_STATUS          0x4       /* link Status -- 1 = link */
#define MDI_SR_AUTO_SELECT          0x8       /* auto speed select capable */
#define MDI_SR_REMOTE_FAULT         0x10      /* Remote fault detect */
#define MDI_SR_AUTO_NEG             0x20      /* auto negotiation complete */
#define MDI_SR_10T_HALF_DPX         0x800     /* 10BaseT half duplex capable */
#define MDI_SR_10T_FULL_DPX         0x1000    /* 10BaseT full duplex capable */
#define MDI_SR_TX_HALF_DPX          0x2000    /* TX half duplex capable */
#define MDI_SR_TX_FULL_DPX          0x4000     /* TX full duplex capable */
#define MDI_SR_T4                   0x8000    /* T4 capable */

#define PHY_100MBS      1
#define PHY_10MBS       0
#define PHY_AUTO_SPEED  2

#define PHY_FULL_DPX    1
#define PHY_HALF_DPX    0
#define PHY_AUTO_DPX    2

#define PHY_LINK_ERROR  0x10
#define PHY_AUTO_FAIL   0x20

/* PRO/100B definitions */

#define EP100B_PCI_VENDOR_ID    0x8086          /* Intel vendor ID */
#define EP100B_PCI_DEVICE_ID    0x1229          /* PRO/100B device ID */

#if ((CPU_FAMILY==I960) && (defined __GNUC__))
#pragma align 0                 /* turn off alignment requirement */
#endif	/* CPU_FAMILY==I960 */

#ifdef __cplusplus
}
#endif

#endif /* __INCif_feih */