dec21x4xend.c

Tornado 2.0.2 source code!vxworks的源代码

/* dec21x4xEnd.c - END style DEC 21x4x PCI Ethernet network interface driver */

/* Copyright 1998 Wind River Systems, Inc. */

#include "copyright_wrs.h"

/*
modification history
--------------------
02d,29mar99,dat  SPR 26040, changed BIG_ENDIAN issue
02c,29mar99,dat  SPR 26119, fixed .bS/.bE calls
02b,14sep98,kla  modified pci calls for new library.	(SPR 24794)
02a,11sep98,kla  modified from ebsa285 BSP, for pc486 target	(SPR 24794)
01z,13oct98,cn   removed setting CSR6_FD in xxxMediaSelect [SPR# 21683]
		 and updated documentation about user flags.
01y,30sep98,dbt  Adding missing code in poll receive routine.
01x,22sep98,dat  SPR 22325, system mode transition.
01w,21apr98,jpd  added call to dec21x4xChipReset in dec21x4xStop().
01v,17mar98,jgn  fixed problems with this driver on CMA22x cards (SPR #20166)
		 (includes start up fix for 21x40 devices on all platforms)
01u,29jan98,rlp  check interrupt status before acknowledgement (SPR# 9995).
		 renamed macro names containing lower case characters.
01t,08dec97,tam  added _func_dec2114xIntAck.
01s,30oct97,rlp  added support for dec21143.
                 renamed _func_dec21x40MediaSelect to _func_dec2114xMediaSelect.
01r,19oct97,vin  moved swapping of loaned buffer before END_RCV_RTN_CALL
01q,17oct97,vin  removed extra free.
01p,09oct97,vin  delete unwanted frees in PollSend routine
01o,07oct97,vin  fixed multicasting, MIB MTU size to ETHER_MTU
01n,25sep97,gnn  SENS beta feedback fixes
01m,24sep97,vin  added clBlk related calls
01l,02sep97,gnn  fixed a race condition in the txRestart handling.
01k,25aug97,vin  adjusted cluster mem size.
01j,22aug97,vin  fixed initialization of cluster mem area.
01i,22aug97,gnn  fixed a bug in polled mode.
01h,21aug97,vin  added changes for newBuffering API
01g,12aug97,gnn  changes necessitated by MUX/END update.
01f,08aug97,map  fixed muxBufInit for user-specified bufpool.
                 added ilevel arg to sysLanIntDisable().
                 update collision statistics.
                 added more flags to userFlags.
01e,10jun97,map  renamed funcDec21x40MediaSelect to _func_dec21x40MediaSelect.
01d,28may97,kbw  general text edit
            map  added DEC SROM support for media configuration.
01c,23apr97,map  cleaned up; replaced SWAP_SHORT with PCISWAP_SHORT.
01b,16apr97,map  added support for dec21140.
01a,07apr97,map  modified if_dc.c to END style.
*/

/*
  
This module implements a DEC 21x4x PCI Ethernet network interface driver and
supports 21040, 21140 and 21143 versions of the chip.

The DEC 21x4x PCI Ethernet controller is little endian because it interfaces
with a little endian PCI bus.  Although PCI configuration for a device is
handled in the BSP, all other device programming and initialization are handled
in this module.

This driver is designed to be moderately generic. Without modification, it can
operate across the range of architectures and targets supported by VxWorks.
To achieve this, the driver requires a few external support routines as well
as several target-specific parameters.  These parameters, and the mechanisms
used to communicate them to the driver, are detailed below.  If any of the
assumptions stated below are not true for your particular hardware, you need to
modify the driver before it can operate correctly on your hardware.

On 21040, the driver configures the 10BASE-T interface by default, waits for
two seconds, and checks the status of the link. If the link status indicates
failure, AUI interface is configured.

On other versions of the 2114x family, the driver reads media information from
a DEC serial ROM and configures the media. On targets that do not support a
DEC format serial ROM, the driver calls a target-specfic media select routine
using the hook, _func_dec2114xMediaSelect, to configure the media.

The driver supports big-endian or little-endian architectures (as a 
configurable option).  The driver also and contains error recovery code 
that handles known device errata related to DMA activity.

Big endian processors can be connected to the PCI bus through some controllers
which take care of hardware byte swapping. In such cases all the registers
which the chip DMAs to have to be swapped and written to, so that when the
hardware swaps the accesses, the chip would see them correctly. The chip still
has to be programmed to operate in little endian mode as it is on the PCI
bus.  If the cpu board hardware automatically swaps all the accesses to and
from the PCI bus, then input and output byte stream need not be swapped.

BOARD LAYOUT
This device is on-board.  No jumpering diagram is necessary.

EXTERNAL INTERFACE

The driver provides one standard external interface, dec21x4xEndLoad(), which
a takes a string of colon separated parameters. The parameters should be
specified as hexadecimal strings, optionally preceded by "0x" or a minus sign
"-".

Although the parameter string is parsed using strtok_r(), each parameter is
converted from string to binary by a call to strtoul(parameter, NULL, 16).

The format of the parameter string is:

 "<unit number>:<device addr>:<PCI addr>:<ivec>:<ilevel>:<mem base>:\
<mem size>:<user flags>:<offset>"

TARGET-SPECIFIC PARAMETERS


.iP "unit number"

This represents the device instance number relative to this driver. 
I.e. a value of zero represents the first dec21x4x device, a value of 1
represents the second dec21x4x device.

.iP "device addr"

This is the base address at which the hardware device registers are located.

.iP "PCI addr"

This parameter defines the main memory address over the PCI bus. It is used to
translate physical memory address into PCI accessible address.

.iP "ivec"

This is the interrupt vector number of the hardware interrupt generated by
this Ethernet device.  The driver uses intConnect, or pciIntConnect (x86 arch),
to attach an interrupt handler for this interrupt.

.iP "ilevel"

This parameter defines the level of the hardware interrupt.

.iP "mem base"

This parameter specifies the base address of a DMA-able, cache free,
pre-allocated memory region for use as a memory pool for transmit/receive
descriptors and buffers.

If there is no pre-allocated memory available for the driver, this parameter
should be -1 (NONE). In which case, the driver allocates cache safe memory
for its use using cacheDmaAlloc().

.iP "mem size"

The memory size parameter specifies the size of the pre-allocated memory
region. If memory base is specified as NONE (-1), the driver ignores this
parameter.

.iP "user flags"

User flags control the run-time characteristics of the Ethernet
chip. Most flags specify non default CSR0 bit values. Refer to
dec21x4xEnd.h for the bit values of the flags, and to the device hardware
reference manual for details about device capabilities, and CSR 0.

Some of them are worth mentioning:

Full Duplex Mode: When set, the DEC_USR_FD flag allows the device to
work in full duplex mode, as long as the PHY used has this
capability. It is worth noting here that in this operation mode,
the dec21x40 chip ignores the Collision and the Carrier Sense signals.
 
Transmit treshold value: The DEC_USR_THR_XXX flags enable the user to
choose among different threshold values for the transmit FIFO.
Transmission starts when the frame size within the transmit FIFO is
larger than the treshold value. This should be selected taking into
account the actual operating speed of the PHY.  Again, see the device
hardware reference manual for details.
 
.iP "offset"

This parameter defines the offset which is used to solve alignment problem.

.iP "Device Type"

Although the default device type is DEC 21040, specifying the DEC_USR_21140
or DEC_USR_21143 flag bit turns on DEC 21140 or DEC_USR_21143 functionality.

.iP "Ethernet Address"

The Ethernet address is retrieved from standard serial ROM on DEC 21040, DEC
21140 and DEC 21143 devices. If retrieve from ROM fails, the driver calls the
BSP routine, sysDec21x4xEnetAddrGet(). Specifying DEC_USR_XEA flag bit tells
the driver should, by default, retrieve the Ethernet address using
the BSP routine, sysDec21x4xEnetAddrGet().

.iP "Priority RX processing"

The driver programs the chip to process the transmit and receive queues at the
same priority. By specifying DEC_USR_BAR_RX, the device is programmed
to process receives at a higher priority.

.iP "TX poll rate"

By default, the driver sets the Ethernet chip into a non-polling mode. 
In this mode, if the transmit engine is idle, it is kick-started every 
time a packet needs to be transmitted.  Alternately, the chip can be 
programmed to poll for the next available transmit descriptor if 
the transmit engine is in idle state. The poll rate is specified by one 
of DEC_USR_TAP_xxx.

.iP "Cache Alignment"

The DEC_USR_CAL_xxx flags specify the address boundaries for
data burst transfers.

.iP "DMA burst length"    

The DEC_USR_PBL_xxx flags specify the maximum number of long
words in a DMA burst.

.iP "PCI multiple read"

The DEC_USR_RML flag specifies that a device supports PCI
memory-read-multiple.


EXTERNAL SUPPORT REQUIREMENTS

This driver requires four external support functions, and provides a hook
function:

.iP "void sysLanIntEnable (int level)" "" 9 -1

This routine provides a target-specific interface for enabling Ethernet device
interrupts at a specified interrupt level.

.iP "void sysLanIntDisable (void)" "" 9 -1

This routine provides a target-specific interface for disabling Ethernet device
interrupts.

.iP "STATUS sysDec21x4xEnetAddrGet (int unit, char *enetAdrs)" "" 9 -1

This routine provides a target-specific interface for accessing a device
Ethernet address.

.iP "STATUS sysDec21143Init (DRV_CTRL * pDrvCtrl)" "" 9 -1

This routine performs any target-specific initialization
required before the dec21143 device is initialized by the driver.
The driver calls this routine every time it wants to load
the device.  This routine returns OK, or ERROR if it fails.

.iP "FUNCPTR _func_dec2114xMediaSelect" "" 9 -1

This driver provides a default media select routine, when
<_func_dec2114xMediaSelect> is NULL, to read and setup physical media with
configuration information from a Version 3 DEC Serial ROM. Any other media
configuration can be supported by initializing <_func_dec2114xMediaSelect>,
typically in sysHwInit(), to a target-specific media select routine.

A media select routine is typically defined as:

.ne 7
.CS
   STATUS decMediaSelect
       (
       DEC21X4X_DRV_CTRL *	pDrvCtrl,   /@ Driver control @/
       UINT *			pCsr6Val    /@ CSR6 return value @/
       )
       {
           ...
       }
.CE

Parameter <pDrvCtrl> is a pointer to the driver control structure which this
routine may use to access the Ethenet device. The driver control structure
field mediaCount, is initialized to 0xff at startup, while the other media
control fields (mediaDefault, mediaCurrent, and gprModeVal) are initialized to
zero. This routine may use these fields in any manner, however all other
driver control fields should be considered read-only and should not be
modified.

This routine should reset, initialize and select an appropriate media, and
write necessary the CSR6 bits (port select, PCS, SCR, and full duplex) to
memory location pointed to by <pCsr6Val>. The driver will use this value to
program register CSR6. This routine should return OK, and ERROR on failure.

.iP "FUNCPTR _func_dec2114xIntAck" "" 9 -1

This driver does acknowledge the LAN interrupts. However if the board hardware
requires specific interrupt acknowledgement, not provided by this driver,
the BSP should define such a routine and attach it to the driver via
_func_dec2114xIntAck. 

SEE ALSO: ifLib, 
.I "DECchip 21040 Ethernet LAN Controller for PCI."
.I "Digital Semiconductor 21140A PCI Fast Ethernet LAN Controller."
.I "Digital Semiconductor 21143 PCI/CardBus Fast Ethernet LAN Controller."
.I "Using the Digital Semiconductor 21140A with Boot ROM, Serial ROM, 
    and External Register: An Application Note"
.I "Using the Digital Semiconductor 21143 with Boot ROM, Serial ROM, 
    and External Register: An Application Note"
*/

/* includes */

#include "vxWorks.h"
#include "wdLib.h"
#include "iv.h"
#include "vme.h"
#include "errno.h"
#include "memLib.h"
#include "intLib.h"
#include "vxLib.h"
#include "net/mbuf.h"
#include "net/unixLib.h"
#include "net/protosw.h"
#include "sys/socket.h"
#include "sys/ioctl.h"
#include "net/route.h"
#include "iosLib.h"
#include "errnoLib.h"

#include "cacheLib.h"
#include "logLib.h"
#include "netLib.h"
#include "stdio.h"
#include "stdlib.h"
#include "sysLib.h"

#include "etherLib.h"
#include "net/systm.h"
#include "sys/times.h"
#include "net/if_subr.h"

#include "drv/end/dec21x4xEnd.h"

#undef	ETHER_MAP_IP_MULTICAST
#include "etherMultiLib.h"
#include "end.h"
#include "endLib.h"

#include "lstLib.h"
#include "semLib.h"

#undef	DRV_DEBUG
#undef	DRV_DEBUG_LOG

/* defines */

#define LOG_MSG(X0, X1, X2, X3, X4, X5, X6)				\
	if (_func_logMsg != NULL)					\
	    _func_logMsg(X0, X1, X2, X3, X4, X5, X6);

#ifdef	DRV_DEBUG_LOG
#define DRV_DEBUG_OFF		0x0000
#define DRV_DEBUG_RX		0x0001
#define	DRV_DEBUG_TX		0x0002
#define DRV_DEBUG_INT		0x0004
#define	DRV_DEBUG_POLL		(DRV_DEBUG_POLL_RX | DRV_DEBUG_POLL_TX)
#define	DRV_DEBUG_POLL_RX	0x0008
#define	DRV_DEBUG_POLL_TX	0x0010
#define	DRV_DEBUG_LOAD		0x0020
#define	DRV_DEBUG_IOCTL		0x0040
#define DRV_DEBUG_POLL_REDIR	0x10000
#define	DRV_DEBUG_LOG_NVRAM	0x20000

int	decDebug = 0x60;

#define DRV_LOG(FLG, X0, X1, X2, X3, X4, X5, X6)                        \
	if (decDebug & FLG)                                             \
            LOG_MSG(X0, X1, X2, X3, X4, X5, X6);

#else /* DRV_DEBUG_LOG */

#define DRV_LOG(DBG_SW, X0, X1, X2, X3, X4, X5, X6)

#endif /* DRV_DEBUG_LOG */

#ifdef  DRV_DEBUG

int     decTxInts=0;
 
IMPORT	void	decCsrShow (void);
IMPORT	void	decTxDShow(int numTxD); 
IMPORT	void	decRxDShow(int numRxD);
IMPORT	void	decShow(void); 
IMPORT  void	eAdrsDisplay(UINT8 * pAddr);
IMPORT	void	mcAdd (char *eAddr);
IMPORT	void	mcDel (char *eAddr);
IMPORT	void	decSerialRomUpload(void);
IMPORT	int	decReset(void);

#endif /* DRV_DEBUG */

#define END_FLAGS_ISSET(pEnd, setBits)                                  \
            ((pEnd)->flags & (setBits))

#define END_HADDR(pEnd)                                                 \
		((pEnd)->mib2Tbl.ifPhysAddress.phyAddress)

#define END_HADDR_LEN(pEnd)                                             \
		((pEnd)->mib2Tbl.ifPhysAddress.addrLength)

#define DEC_SPEED_10	10000000             /* 10 Mbps */
#define DEC_SPEED_100	100000000            /* 100 Mbps */
#define	DEC_SPEED_DEF	DEC_SPEED_10
#define EADDR_LEN	6                    /* ethernet address length */
#define DEC_PKT_SIZE	(ETHERMTU + ENET_HDR_REAL_SIZ + 6)

#define DELAY(count)	{                                               \
			volatile int cx = 0;                            \
			for (cx = 0; cx < (count); cx++);               \
			}

#define	LOOPS_PER_NS	4
#define NSDELAY(nsec)	{                                               \
			volatile int nx = 0;                            \
			volatile int loop = (int)((nsec)*LOOPS_PER_NS); \
			for (nx = 0; nx < loop; nx++);                  \
			}

#define DEC_BUF_ALLOC_ROUTINE                                           \
	(FUNCPTR) (DRV_FLAGS_ISSET(DEC_MEMOWN) ?                        \
                   cacheDmaMalloc : NULL)

#define DEC_BUF_POOL_ADRS                                               \
	(char *)(DRV_FLAGS_ISSET(DEC_MEMOWN) ?                          \
                  NULL:(pDrvCtrl->txRing + pDrvCtrl->numTds))

/* DRV_CTRL flags access macros */

#define DRV_FLAGS_SET(setBits)                                          \
	(pDrvCtrl->flags |= (setBits))