if_dc.c

Tornado 2.0.2 source code!vxworks的源代码

/* if_dc.c - DEC 21x4x Ethernet LAN network interface driver */

/* Copyright 1984-1998 Wind River Systems, Inc. */
/* Copyright 1996-1998 Motorola, Inc., All Rights Reserved */

#include "copyright_wrs.h"

/*
modification history
--------------------
01m,07apr98,dat  fixed man page generation.
01l,26nov97,map  added support for SENS stack.
01k,21nov97,map  update if_flags when DC_* flags are set [SPR# 9873]
01j,30oct97,map  Merged media-select changes from mtx603/dec21140/dec21140.c
                 (ver 01s). Added macros for BSP interface and register access.
                 Added MII interface routines.
01i,27oct97,map  Merged from mv2603/dec21140/dec21140.c (ver 01r) [SPR# 8176]
01h,24jun97,map  Fixed memory leaks. Added dropped frame counts [SPR# 8826]
01m,15dec97,map  use BSD macro to define BSD4[34]_DRIVER flag.
01l,26nov97,map  added support for SENS stack.
01k,21nov97,map  update if_flags when DC_* flags are set [SPR# 9873]
01j,30oct97,map  Merged media-select changes from mtx603/dec21140/dec21140.c
                 (ver 01s). Added macros for BSP interface and register access.
                 Added MII interface routines.
01i,27oct97,map  Merged from mv2603/dec21140/dec21140.c (ver 01r) [SPR# 8176]
01h,24jun97,map  Fixed memory leaks. Added dropped frame counts [SPR# 8826]
01g,06nov96,dgp  doc: final formatting
01f,01jul96,tam  moved code from dcInt to dcHandleRecvInt to reduce the amount
		 of code executed at interrupt level (spr #6070).
01e,19jun96,tam  added output etherhook to dcOutput (spr #6695).
01d,05sep95,vin  added filter Frame setup, added PROMISCOUS MODE to ioctl,
		 changed all ln references to dc, added flag DC_MULTICAST_FLAG.
01c,05apr95,vin  added AUI/10BASE-T dynamic configuration support. 
01b,31mar95,caf  changed name from "dcPci" to "dc".
01a,03mar95,vin	 written.
*/

/* 

This module implements an ethernet interface driver for the DEC 21x4x family,
and currently supports the following variants -- 21040, 21140, and 21140A.

The DEC 21x4x PCI Ethernet controllers are inherently little-endian since they
are designed for a little-endian PCI bus. While the 21040 only supports a
10Mps interface, other members of this family are dual-speed devices which
support both 10 and 100 Mbps.

This driver is designed to be moderately generic, operating unmodified across
the range of architectures and targets supported by VxWorks; and on multiple
versions of the dec21x4x family. To achieve this, the driver takes several
parameters, and external support routines which are detailed below. Also
stated below are assumptions made by the driver of the hardware, and if any of
these assumptions are not true for your hardware, the driver will probably not
function correctly.

This driver supports up to 4 ethernet units per CPU, and can be
configured for either big-endian or little-endian architectures.  It
contains error-recovery code to handle known device errata related to DMA
activity.

On a dec21040, this driver configures the 10BASE-T interface by default and
waits for two seconds to check the status of the link. If the link status is
"fail," it then configures the AUI interface.

The dec21140, and dec21140A devices support both 10 and 100Mbps and also a
variety of MII and non-MII PHY interfaces. This driver reads a DEC version 2.0
SROM device for PHY initialization information, and automatically configures
an apropriate active PHY media.

BOARD LAYOUT

This device is on-board.  No jumpering diagram is necessary.

EXTERNAL INTERFACE

This driver provides the standard external interface with the following
exceptions.  All initialization is performed within the attach routine;
there is no separate initialization routine.  Therefore, in the global interface
structure, the function pointer to the initialization routine is NULL.

The only user-callable routine is dcattach(), which publishes the `dc'
interface and initializes the driver and device.

TARGET-SPECIFIC PARAMETERS

.iP "bus mode"

This parameter is a global variable that can be modified at run-time.

The LAN control register #0 determines the bus mode of the device,
allowing the support of big-endian and little-endian architectures.
This parameter, defined as "ULONG dcCSR0Bmr", is the value that will
be placed into device control register #0. The default is mode is little
endian.

For information about changing this parameter, see the manual

.I "DEC  Local Area Network Controller DEC21040 or DEC21140 for PCI."

.iP "base address of device registers"

This parameter is passed to the driver by dcattach().

.iP "interrupt vector"

This parameter is passed to the driver by dcattach().

This driver configures the device to generate hardware interrupts
for various events within the device; thus it contains
an interrupt handler routine.  The driver calls intConnect() to connect 
its interrupt handler to the interrupt vector generated as a result of 
the device interrupt.

.iP "interrupt level"

This parameter is passed to the driver by dcattach().

Some targets use additional interrupt controller devices to help organize and
service the various interrupt sources.  This driver avoids all board-specific
knowledge of such devices.  During the driver's initialization, the external
routine sysLanIntEnable() is called to perform any board-specific operations
required to allow the servicing of a device interrupt.  For a description of
sysLanIntEnable(), see "External Support Requirements" below.

This parameter is passed to the external routine.

.iP "shared memory address"

This parameter is passed to the driver by dcattach().

The DEC 21x4x device is a DMA type of device and typically shares access to
some region of memory with the CPU.  This driver is designed for systems that
directly share memory between the CPU and the DEC 21x4x.  It assumes that this
shared memory is directly available to it without any arbitration or timing
concerns.

This parameter can be used to specify an explicit memory region for use by the
DEC 21x4x device.  This should be done on hardware that restricts the DEC
21x4x device to a particular memory region.  The constant NONE can be used to
indicate that there are no memory limitations, in which case, the driver
attempts to allocate the shared memory from the system space.

.iP "shared memory size"

This parameter is passed to the driver by dcattach().

This parameter can be used to explicitly limit the amount of shared
memory (bytes) this driver will use.  The constant NONE can be used to
indicate no specific size limitation.  This parameter is used only if
a specific memory region is provided to the driver.

.iP "shared memory width"

This parameter is passed to the driver by dcattach().

Some target hardware that restricts the shared memory region to a
specific location also restricts the access width to this region by
the CPU.  On these targets, performing an access of an invalid width
will cause a bus error.

This parameter can be used to specify the number of bytes of access
width to be used by the driver during access to the shared memory.
The constant NONE can be used to indicate no restrictions.

Current internal support for this mechanism is not robust; implementation 
may not work on all targets requiring these restrictions.

.iP "shared memory buffer size"

This parameter is passed to the driver by dcattach().

The driver and DEC 21x4x device exchange network data in buffers.  This
parameter permits the size of these individual buffers to be limited.
A value of zero indicates that the default buffer size should be used.
The default buffer size is large enough to hold a maximum-size Ethernet
packet.

.iP "pci Memory base"

This parameter is passed to the driver by dcattach(). This parameter
gives the base address of the main memory on the PCI bus. 

.iP "dcOpMode"

This parameter is passed to the driver by dcattach(). This parameter
gives the mode of initialization of the device. The mode flags for both
the DEC21040 and DEC21140 interfaces are listed below.  

DC_PROMISCUOUS_FLAG     0x01 
DC_MULTICAST_FLAG	0x02

The mode flags specific to the DEC21140 interface are listed below.

DC_100_MB_FLAG          0x04
DC_21140_FLAG           0x08
DC_SCRAMBLER_FLAG       0x10
DC_PCS_FLAG             0x20
DC_PS_FLAG              0x40

DC_FULLDUPLEX_FLAG      0x10

Loopback mode flags
DC_ILOOPB_FLAG          0x100 
DC_ELOOPB_FLAG          0x200
DC_HBE_FLAG	        0x400

.iP "Ethernet address"

This is obtained by the driver by reading an ethernet ROM register or the DEC
serial ROM.

.LP

EXTERNAL SUPPORT REQUIREMENTS

This driver requires one external support function:

.iP "void sysLanIntEnable (int level)" "" 9 -1

This routine provides a target-specific enable of the interrupt for the DEC
21x4x device.  Typically, this involves interrupt controller hardware, either
internal or external to the CPU.

This routine is called once via the macro SYS_INT_ENABLE().
.LP

INTERNAL

This driver utilizes macros to access registers and certain BSP
functionalities. These macros may be redefined in a wrapper file to generate a
new driver module with a customized interface.

.iP "SYS_INT_CONNECT"

This macro is used to associate an interrupt handler to the device interrupt
vector pDrvCtrl->ivec. An OK/ERROR status is returned via parameter `pResult'.

.iP "SYS_INT_DISCONNECT"

Currently, this macro is not used by the driver, but exists for future
implementation and will be used to disconnect an interrupt handler from the
device interrupt vector. An OK/ERROR status is returned via parameter, `pResult'.

.iP "SYS_INT_ENABLE"

This macro is used by the driver to enable device interrupts. Typically, this
macro should call a BSP routine that will enable interrupts from this device.

.iP "SYS_INT_DISABLE"

This macro is called by the driver to disable device interrupts.

.iP "DC_CSR_READ"

This macro is used by the driver to read the device command status 
registers. If not redefined, this macro calls the inbuilt driver function
dcCsrRead().

.iP "DC_CSR_WRITE"

This macro is used by the driver to write to a device command status
register. By default this macro calls the inbuilt driver funtion dcCsrWrite().

.LP


SEE ALSO: ifLib, 

.I "DECchip 21040 or 21140 Ethernet LAN Controller for PCI."

*/

#include "vxWorks.h"
#include "stdlib.h"
#include "taskLib.h"
#include "logLib.h"
#include "intLib.h"
#include "netLib.h"
#include "stdio.h"
#include "stdlib.h"
#include "sysLib.h"
#include "iv.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sys/ioctl.h"
#include "etherLib.h"

#ifndef DOC             /* don't include when building documentation */
#include "net/mbuf.h"
#endif  /* DOC */

#include "net/protosw.h"
#include "sys/socket.h"
#include "errno.h"

#include "net/if.h"
#include "net/route.h"

#include "netinet/in.h"
#include "netinet/in_systm.h"
#include "netinet/in_var.h"
#include "netinet/ip.h"
#include "netinet/if_ether.h"
#include "net/if_subr.h"
#include "semLib.h"

#include "drv/netif/if_dc.h"                 /* device description header */

/* defines */

#if (BSD == 44)
#  define	BSD44_DRIVER
#else
#  define	BSD43_DRIVER
#endif /* (BSD == 44) */

#ifdef BSD43_DRIVER
typedef struct enet_hdr
    {
    char dst [6];
    char src [6];
    USHORT type;
    } ENET_HDR;
#endif /* BSD43_DRIVER */

#define ENET_HDR_SIZ        sizeof(ENET_HDR)
#define ENET_HDR_REAL_SIZ   14

#define DC_BUFSIZ      (ETHERMTU + SIZEOF_ETHERHEADER + 6)
#define MAX_UNITS       4	/* maximum units supported */
#define DC_L_POOL	0x10	/* number of Rx loaner buffers in pool */
#define LOOP_PER_NS 4

#define DELAY(count)	{                                               \
			volatile int cx = 0;                            \
			for (cx = 0; cx < (count); cx++);               \
			}

#ifndef NSDELAY
#define NSDELAY(nsec)	{                                               \
			volatile int nx = 0;                            \
			volatile int loop = (int)(nsec*LOOP_PER_NS);    \
			for (nx = 0; nx < loop; nx++);                  \
			}
#endif /* NSDELAY */

#define DEC21140(x)	(x & DC_21140_FLAG)

/*
 * If DC_KICKSTART_TX is TRUE the transmitter is kick-started to force a read
 * of the transmit descriptors, otherwise the internal polling (1.6msec) will
 * initiate a read of the descriptors.  This should be FALSE is there is any
 * chance of memory latency or chip accesses detaining the DEC 21x4x DMA,
 * which results in a transmitter UFLO error.  This can be changed with the
 * global dcKickStartTx below.
 */

#define DC_KICKSTART_TX TRUE

/* Cache macros */

#define DC_CACHE_INVALIDATE(address, len)                               \
        CACHE_DRV_INVALIDATE (&pDrvCtrl->cacheFuncs, (address), (len))

#define DC_CACHE_VIRT_TO_PHYS(address)                                  \
        CACHE_DRV_VIRT_TO_PHYS (&pDrvCtrl->cacheFuncs, (address))

#define DC_CACHE_PHYS_TO_VIRT(address)                                  \
        CACHE_DRV_PHYS_TO_VIRT (&pDrvCtrl->cacheFuncs, (address))

/*
 * Default macro definitions for BSP interface.
 * These macros can be redefined in a wrapper file, to generate
 * a new module with an optimized interface.
 */
#ifndef SYS_INT_CONNECT
#define	SYS_INT_CONNECT(pDrvCtrl, rtn, arg, pResult)                    \
    {                                                                   \
    *pResult = intConnect((VOIDFUNCPTR *)INUM_TO_IVEC (pDrvCtrl->ivec), \
                          (rtn), (int) (arg));                          \
    }
#endif /* SYS_INT_CONNECT */

#ifndef SYS_INT_DISCONNECT
#define SYS_INT_DISCONNECT(pDrvCtrl, rtn, arg, pResult)                 \
    {                                                                   \
    *pResult = OK;                                                      \
    }
#endif /* SYS_INT_DISCONNECT */
    
#ifndef SYS_INT_ENABLE
#define	SYS_INT_ENABLE(pDrvCtrl)                                        \
    {                                                                   \
    IMPORT void sysLanIntEnable(int level);                             \
    sysLanIntEnable (pDrvCtrl->ilevel);                                 \
    }
#endif /* SYS_INT_ENABLE */

#ifndef SYS_INT_DISABLE
#define SYS_INT_DISABLE(pDrvCtrl)                                       \
    {                                                                   \
    IMPORT void sysLanIntDisable(int level);                            \
    sysLanIntDisable (pDrvCtrl->ilevel);                                \
    }
#endif /* SYS_INT_DISABLE */
    
/* memory to PCI address translation macros */

#define PCI_TO_MEM_PHYS(pciAdrs)                                        \
	((pciAdrs) - (pDrvCtrl->pciMemBase))
	
#define MEM_TO_PCI_PHYS(memAdrs)                                        \
	((memAdrs) + (pDrvCtrl->pciMemBase))

#define DC_TD_INDEX_NEXT(pDrvCtrl)                                      \
	(((pDrvCtrl)->txIndex + 1) % (pDrvCtrl)->dcNumTds)

#define DC_TD_DINDEX_NEXT(pDrvCtrl)                                     \
	(((pDrvCtrl)->txDiIndex + 1) % (pDrvCtrl)->dcNumTds)

/*