test1.c

cache测试软件

#include <stdio.h>

#define BUF_WIDTH  704
#define BUF_HEIGHT 576

#define BUF_SIZE   BUF_WIDTH*BUF_HEIGHT


#define DCACHE_SIZE 32*1024

typedef (*TST_FUNC)(void);

static unsigned char buf_0[BUF_SIZE],buf_1[BUF_SIZE];
static unsigned char buf_2[BUF_SIZE],buf_3[BUF_SIZE];
static unsigned char tmpbuf_0[BUF_HEIGHT],tmpbuf_1[BUF_WIDTH];
static unsigned char buf_flush[DCACHE_SIZE];

TST_FUNC test[20];

init(void)
{
 long i;
 
 for(i = 0; i < BUF_SIZE; i++)
   buf_0[i]=i*rand();//buf_0 mapped to cache,but incoherent	
 //for(i = 0; i < BUF_SIZE; i++)
  // buf_1[i]=0xff;//buf_1 mapped to cache,but incoherent	  
   
}

int dcache_flush(void)
{//simulate a data cache flush
 int i;
 
 for(i = 0; i < DCACHE_SIZE; i++)
   buf_flush[i]=i;	 
}

int test_1(void)
{//purpose:to test incoherency
 //conclusion:cache a double sword,it caused cache incoherency
 init();
 
 kprintf("test_0:%d   %d\n ",buf_0[10],*((volatile_noncached unsigned char *)(buf_0+10)));
}

int test_2(void)
{//purpose:to compare printf with kprintf
 //conclusion:it demonstrates printf caused a flush to cache while kprintf did not.
 init();

 printf("test_2:%d   %d\n ",buf_0[10],*((volatile_noncached unsigned char *)(buf_0+10)));
 printf("test_2:%d   %d\n ",buf_0[10],*((volatile_noncached unsigned char *)(buf_0+10)));
}

int test_3(void)
{//purpose:add cache flush 
 //conclusion:it explains when a big amount of data are allocated to cache,they will cause a cache flush
 init();
 
 dcache_flush();
 kprintf("test_3:%d   %d\n ",buf_0[10],*((volatile_noncached unsigned char *)(buf_0+10)));
}

int test_4(void)
{
	int i;
	//purpose:to compare printf with kprintf
 //conclusion:it demonstrates printf caused a flush to cache while kprintf did not.
 init();
 
 #if 1 //by diret read
  /*simulate data transfer from ram memory to cache by DMA*/
  for(i=0;i<BUF_SIZE;i++) 
  tmpbuf_0[i]=*((volatile_noncached unsigned char *)(buf_0+i));
  
  /*simulate cpu's copying data from cache to cache*/
  for(i=0;i<BUF_SIZE;i++) 
  tmpbuf_1[i]=tmpbuf_0[i];
  
  /*simulate data transfer from cache to ram memory by DMA*/
  for(i=0;i<BUF_SIZE;i++) 
  *((volatile_noncached unsigned char *)(buf_1+i))=tmpbuf_1[i];
 #else //by memcpy
 
 #endif

 /*
 explanation:
   buf_0[10] should be 10 because it's in cache and has never been overwritten so far;
   buf_0_volatile_noncached[10] should be 0 due to cache incoherency;
 */
 kprintf("test_4:%d   %d\n ",buf_0[10],*((volatile_noncached unsigned char *)(buf_0+10)));
 
 /*
 explanation:
   buf_1[10] should be 20 because it's in cache and has never been overwritten in cache so far;
   buf_1_volatile_noncached[10] should be 10 due to the operation of dma data transfer bypassing cache 
 */
 kprintf("test_4:%d   %d\n ",buf_1[10],*((volatile_noncached unsigned char *)(buf_1+10)));
 
 /*
 explanation:
   buf_0[10] should be 10 because it's in cache;
   buf_0_volatile_noncached[10] should be 10 after flush;
   buf_1[10] should be 20 because it's 20 in cache when initialized but turned to 20 after flush.
   buf_1_volatile_noncached[10] should be 20 due to the operation of data transfer bypassing cache 
 */
 
 dcache_flush();
 
 kprintf("test_4:%d   %d\n ",buf_0[10],*((volatile_noncached unsigned char *)(buf_0+10)));
 kprintf("test_4:%d   %d\n ",buf_1[10],*((volatile_noncached unsigned char *)(buf_1+10)));

/*
 Bug:
 data value 0 at ram memory buf_0+10 was copeid to ram memory addess buf_1+10,however the addess 
 at ram memory buf_1+10 finally got 20,what's wrong?
*/
}

int test_5(void)
{//to test the bug of fwrite
 int i;
 
 init();
 
 #if 1 //by diret read
  /*simulate data transfer from ram memory to cache by DMA*/
  for(i=0;i<BUF_SIZE;i++) 
  tmpbuf_0[i]=*((volatile_noncached unsigned char *)(buf_0+i));
  
  /*simulate cpu's copying data from cache to cache*/
  for(i=0;i<BUF_SIZE;i++) 
  tmpbuf_1[i]=tmpbuf_0[i];
  
  /*simulate data transfer from cache to ram memory by DMA*/
  for(i=0;i<BUF_SIZE;i++) 
  *((volatile_noncached unsigned char *)(buf_1+i))=tmpbuf_1[i];
 #else //by memcpy
 
 #endif
 
 /*
  Bug:
  perhaps,you are tring to copy data form src ram memory to dst ram memory via cache
  however,you get data from cache not src ram memory to dst memory,they are incoherent!
 */
 #if 1
 {
  FILE *fptr;
  
  if((fptr = fopen("c:/eti_tools/filter/check.yuv","wb")) == NULL)
  {
    printf("Could not open file %s\n","c:/eti_tools/filter/check.yuv" );
    exit(1);
  }	
  
  fwrite(buf_1, sizeof(unsigned char),BUF_SIZE, fptr);
  fclose(fptr);
  printf("done!\n");
  exit(1);
 }	   
 #endif 	
}

int test_6(void)
{//to solve the bug 
 int i;

 init();//to simualte the inital states of the two buffers,buf_0 and buf_1; 
 
 /*
 ... //the two buffers might be accessed before the following operation,data transfer.
 */
 
 dcache_flush();//make cache consistent with ram memory before any operation
 
 /*doing data transfer and check*/
 //------------------------------------------------------------------------
 #if 1 //by diret read
  /*simulate data transfer from ram memory to cache by DMA*/
  for(i=0;i<BUF_SIZE;i++) 
  tmpbuf_0[i]=*((volatile_noncached unsigned char *)(buf_0+i));
  
  /*simulate cpu's copying data from cache to cache*/
  for(i=0;i<BUF_SIZE;i++) 
  tmpbuf_1[i]=tmpbuf_0[i];
  
  /*simulate data transfer from cache to ram memory by DMA*/
  for(i=0;i<BUF_SIZE;i++) 
  *((volatile_noncached unsigned char *)(buf_1+i))=tmpbuf_1[i];
 #else //by memcpy
 
 #endif
 
 dcache_flush();//make cache consistent with ram memory before any operation
 #if 1
 {
  FILE *fptr;
  
  if((fptr = fopen("c:/eti_tools/filter/check.yuv","wb")) == NULL)
  {
    printf("Could not open file %s\n","c:/eti_tools/filter/check.yuv" );
    exit(1);
  }	
  //use volatible nocached
  fwrite((volatile_noncached unsigned char*)buf_1, sizeof(unsigned char),BUF_SIZE, fptr);
  fclose(fptr);
  printf("done!\n");
  exit(1);
 }	   
 #endif 
 //------------------------------------------------------------------------
 
 /*
  analysis:
  Ram memory maight be coherent with cache,but it will be if we do cache flush before 
  any operation.At this time when flushed, it reflects the lastest state of ram memory.
 */
}

int test_7(void)
{//to simulate and test a more huge data transfer 
 int i,j;

 init();//to simualte the inital states of the two buffers,buf_0 and buf_1; 
 
 /*
 ... //the two buffers might be accessed before the following operation,data transfer.
 */
 
 dcache_flush();//make cache consistent with ram memory before any operation
 
 /*doing data transfer and check*/
 //------------------------------------------------------------------------
 #if 1 //by diret read
  /*simulate data transfer from ram memory to cache by DMA*/
 for(i=0;i<BUF_HEIGHT;i++)
 {
  for(j=0;j<BUF_WIDTH;j++)
   tmpbuf_0[j]=*((volatile_noncached unsigned char *)(buf_0+i*BUF_WIDTH+j));
   
   /*simulate cpu's copying data from cache to cache*/
  for(j=0;j<BUF_WIDTH;j++) 
  tmpbuf_1[j]=tmpbuf_0[j];
  
  /*simulate data transfer from cache to ram memory by DMA*/
  for(j=0;j<BUF_WIDTH;j++) 
  *((volatile_noncached unsigned char *)(buf_1+i*BUF_WIDTH+j))=tmpbuf_1[j];	
 }
 #else //by memcpy
 
 #endif
 
 dcache_flush();//make cache consistent with ram memory before any operation
 #if 1
 {
  FILE *fptr;
  
  if((fptr = fopen("c:/eti_tools/filter/check.yuv","wb")) == NULL)
  {
    printf("Could not open file %s\n","c:/eti_tools/filter/check.yuv" );
    exit(1);
  }	
  //using volatible noncached or not makes no difference;
  //=fwrite((volatile_noncached unsigned char*)buf_1, sizeof(unsigned char),BUF_SIZE, fptr);
  fwrite(buf_1, sizeof(unsigned char),BUF_SIZE, fptr);  
  
  fclose(fptr);
  //printf("done!\n");
  exit(1);
 }	   
 #endif 
 //------------------------------------------------------------------------
 
 /*
  analysis:
  Ram memory maight be coherent with cache,but it will be if we do cache flush before 
  any operation.At this time when flushed, it reflects the lastest state of ram memory.
 */
}

int test_8(void)
{//use memory copy to do data copy from cache to cache
 int i,j;

 init();//to simualte the inital states of the two buffers,buf_0 and buf_1; 
 
 /*
 ... //the two buffers might be accessed before the following operation,data transfer.
 */
 
 dcache_flush();//make cache consistent with ram memory before any operation
 
 /*doing data transfer and check*/
 //------------------------------------------------------------------------
 #if 1 //by diret read
  /*simulate data transfer from ram memory to cache by DMA*/
 for(i=0;i<BUF_HEIGHT;i++)
 {
  for(j=0;j<BUF_WIDTH;j++)
   tmpbuf_0[j]=*((volatile_noncached unsigned char *)(buf_0+i*BUF_WIDTH+j));
  //memcpy(tmpbuf_0,(volatile_noncached unsigned char *)(buf_0+i*BUF_WIDTH+j),BUF_WIDTH);
   
   /*simulate cpu's copying data from cache to cache*/
  //for(j=0;j<BUF_WIDTH;j++) 
  //tmpbuf_1[j]=tmpbuf_0[j];
  memcpy(tmpbuf_1,tmpbuf_0,BUF_WIDTH);
  
  /*simulate data transfer from cache to ram memory by DMA*/
  for(j=0;j<BUF_WIDTH;j++) 
  *((volatile_noncached unsigned char *)(buf_1+i*BUF_WIDTH+j))=tmpbuf_1[j];
  //memcpy((volatile_noncached unsigned char *)(buf_1+i*BUF_WIDTH+j),tmpbuf_1,BUF_SIZE);
 }
 #else //by memcpy
 
 #endif
 
 dcache_flush();//make cache consistent with ram memory before any operation
 #if 1
 {
  FILE *fptr;
  
  if((fptr = fopen("c:/eti_tools/filter/check.yuv","wb")) == NULL)
  {
    printf("Could not open file %s\n","c:/eti_tools/filter/check.yuv" );
    exit(1);
  }	
  //using volatible noncached or not makes no difference;
  //=fwrite((volatile_noncached unsigned char*)buf_1, sizeof(unsigned char),BUF_SIZE, fptr);
  fwrite(buf_1, sizeof(unsigned char),BUF_SIZE, fptr);  
  
  fclose(fptr);
  printf("done!\n");
  exit(1);
 }	   
 #endif 
 //------------------------------------------------------------------------
 
 /*
  analysis:
  Ram memory maight be coherent with cache,but it will be if we do cache flush before 
  any operation.At this time when flushed, it reflects the lastest state of ram memory.
 */
}

int test_9(void)
{//use memory copy to do data transfer,but can't achieve the expected resutl!
 int i,j;

 init();//to simualte the inital states of the two buffers,buf_0 and buf_1; 
 
 /*
 ... //the two buffers might be accessed before the following operation,data transfer.
 */
 
 dcache_flush();//make cache consistent with ram memory before any operation
 
 /*doing data transfer and check*/
 //------------------------------------------------------------------------
 #if 1 //by diret read
  /*simulate data transfer from ram memory to cache by DMA*/
 for(i=0;i<BUF_HEIGHT;i++)
 {
  //for(j=0;j<BUF_WIDTH;j++)
   //tmpbuf_0[j]=*((volatile_noncached unsigned char *)(buf_0+i*BUF_WIDTH+j));
  memcpy(tmpbuf_0,(volatile_noncached unsigned char *)(buf_0+i*BUF_WIDTH+j),BUF_WIDTH);
  //=memcpy(tmpbuf_0,(buf_0+i*BUF_WIDTH+j),BUF_WIDTH);
  
   /*simulate cpu's copying data from cache to cache*/
  //for(j=0;j<BUF_WIDTH;j++) 
  //tmpbuf_1[j]=tmpbuf_0[j];