system.c

本source code 為s3c4510的bootloader

   if(cn == ch || ch < 0) {
     Print("  %04x", ((reg[cn] & ROMCON_BASE_MASK) >> ROMCON_BASE_OFFSET));
   }
 }
 
//
 PrintMBIT("29:20  next pointer");
 for(cn = 0; cn < cnt; ++cn) {
   if(cn == ch || ch < 0) {
     Print("  %04x", ((reg[cn] & ROMCON_NEXT_MASK) >> ROMCON_NEXT_OFFSET));
   }
 }
}

// print DRAMCON /////////////////////////////////////////////////////////////////

static void PrintDRAMCON(int ch)
{
 U32 reg[4];				// DRAMCON regs 
 int cn, cnt, len;			// bank number, count, field length
 reg[0] = DRAMCON0; 			// DRAM bank 0 control reg 
 reg[1] = DRAMCON1; 			// DRAM bank 1 control reg 
 reg[2] = DRAMCON2; 			// DRAM bank 2 control reg 
 reg[3] = DRAMCON3; 			// DRAM bank 3 control reg 

 if(ch >= 0) 
  {
   cnt = ch + 1; 
   len = 15; 
  } 
 else 
  {
   cnt = -ch; 
   len = 40 / cnt; 
   if(len > 15) { len = 15; }
  } 

 Print("\nDRAMCON");
 for(cn = 0; cn < cnt; ++cn)
  {
   if(cn == ch || ch < 0) 
    {
     Print(" 0x%08x", reg[cn]);
    }
  }

 {
// [0] EDOMO mode
  PrintSBIT(ch, "0 EDO mode", reg, DRAMCON_EDO, "1/EDO", "0/norm");
 }
 
 {
// [2:1] CAS strobe time (tCS)
  ABIT tcs_bt[] = {
    {"00/1CLK", DRAMCON_TCS_1CLK},
    {"01/2CLK", DRAMCON_TCS_2CLK},
    {"10/3CLK", DRAMCON_TCS_3CLK},
    {"11/4CLK", DRAMCON_TCS_4CLK},
    {0, 0}
  };

  PrintABIT(ch, "2:1 CAS strobe time (tCS)", reg, DRAMCON_TCS, tcs_bt);
 }

  PrintSBIT(ch, "3:3 CAS precharge time (tCP)", reg, DRAMCON_TCP, 
   "1=2CLK", "0=1CLK");

  PrintSBIT(ch, "7 RAS to CAS delay(tRC or tRCD)", reg, DRAMCON_TRC, 
   "1=2CLK", "0=1CLK");

 {
  ABIT trp_bt[] = {
    {"00=1CLK", DRAMCON_TRP_1CLK},
    {"01=2CLK", DRAMCON_TRP_2CLK},
    {"10=3CLK", DRAMCON_TRP_3CLK},
    {"11=4CLK", DRAMCON_TRP_4CLK},
  };

  PrintABIT(ch, "9:8 RAS pre-charge time (tRP)", reg, DRAMCON_TRP, trp_bt); 
 }

 {
// 19:10 DRAM bank base pointer /////////////////////////////////////////////////
  int cn;
  PrintMBIT("19:10 DRAM bank base pointer ");
  for(cn = 0; cn < cnt; ++cn) 
   {
    if(cn == ch || ch < 0) 
     {
      Print("%-*x", len, (reg[cn] >> 10) & 0x3FF );
     }
   }
 }
 
 {
// 29:20 DRAM bank next pointer /////////////////////////////////////////////////
  int cn;
  PrintMBIT("29:20 DRAM bank next pointer ");
  for(cn = 0; cn < cnt; ++cn) 
   {
    if(cn == ch || ch < 0) 
     {
      Print("%-*x", len, (reg[cn] >> 20) & 0x3FF );
     }
   }
 }

 {
// [31:30]  Number of column address bits in DRAM bank # (CAN)
  ABIT can_bt[] = {
    {"00= 8bits", DRAMCON_CAN_8BITS  },
    {"01= 9bits", DRAMCON_CAN_9BITS  },
    {"10=10bits", DRAMCON_CAN_10BITS },
    {"11=11bits", DRAMCON_CAN_11BITS },
    { 0, 0}
  };  

  PrintABIT(ch, "31:30 Number of column bits (CAN)", reg, DRAMCON_CAN, can_bt);
 }
}

// print DRAM Refresh and External I/O Control register (REFEXRCON) /////////////

static void PrintREFEXTCON(void)
{
 U32 reg[1];
 reg[0] = REFEXTCON; 

 Print("\nREFEXTCON=0x%08x", reg[0]);
 PrintMBIT("9:0 External I/O bank 0 base pointer");
 Print("%04x", (REFEXTCON & 0x3FF) );

 PrintUBIT(0,"15 Validity of special reg field(VSF)", reg, REFEXTCON_VSF);
 PrintUBIT(0,"16 Refresh enable (REN)", reg, REFEXTCON_REN);

 {
// [19:17] CAS hold time(tCHR), ROW Cycle Time in SDRAM mode
  ABIT trc_bt[] = {
    {"000=1 cycle",  REFEXTCON_TRC_1CLK},
    {"001=2 cycles", REFEXTCON_TRC_2CLK},
    {"010=3 cycles", REFEXTCON_TRC_3CLK},
    {"011=4 cycles", REFEXTCON_TRC_4CLK},
    {"100=5 cycles", REFEXTCON_TRC_5CLK},
    {"101=6 cycles", REFEXTCON_TRC_6CLK},
    { 0, 0 }
  };

  PrintABIT(0, "19:17 ROW Cycle Time", reg, REFEXTCON_TRC, trc_bt);
 }

// [20] CAS setup time(t CSR) (note2)
 PrintSBIT(0,"20 CAS setup time(t CSR)", reg, REFEXTCON_TCSR,
   "1=2 cycles", "0=1 cycle");

 PrintMBIT("31:21 Refresh count value (duration)");
 Print("%d", ((reg[0] >> 21) * 0x7FF));
}


static void SysRegsView(void)
{
 while(1) {
   U8 it;
   Print("\n[S] SYSCFG - System Configuration Register.");
   Print("\n[C] CLKCON - Clock Control Register.");
   Print("\n[E] EXTACON 0&1 - External I/O access timing register 0,1.");
   Print("\n[W] EXTDBWTH - Data bus width of each bank.");
   Print("\n[R] ROMCON0-5  - ROM/SRAM/FLASH control register 0,1,2,3,4,5 .");
   Print("\n[D] DRAMCON0-3 - DRAM control registers 0,1,2,3.");
   Print("\n[F] REFEXTCON");
   Print("\n[Q] Quit.");

   Print("\nSelect Test Item: ");
   it = get_upper();
   switch(it) {
     case 'S' : PrintCacheConfig(); break;
     case 'C' : PrintCLKCON(); break;
     case 'E' : PrintEXTACON(); break;
     case 'W' : PrintEXTDBWTH(); break;
     case 'R' : PrintROMCON(-6); break;
     case 'D' : PrintDRAMCON(-4); break;
     case 'F' : PrintREFEXTCON(); break;
// 
     case 'Q' : 				// exit from menu 
      return;
     default  : break;
   }
   Print("\nPress any key to continue.\n");
   it = get_upper();
   if(it == 'Q') {
     break;
   } 
 }
}


/************************************************************************/
/*           CACHE & INTERNAL STRAM TEST TOP MODULE                     */
/************************************************************************/

void CacheTest(void)
{
 char it;

 while(1) 
  {
   Print("\nKS32C50100 CACHE & SRAM TEST");
   Print("\n[1] Tag RAM(256words) 10N march test.");	// 
   Print("\n[2] Internal SRAM(4kbytes) 10N march test.");
   Print("\n[3] Internal SRAM(8kbytes) 10N march test.");
   Print("\n[4] Cache Set0(4kbytes) 10N march test.");
   Print("\n[5] Cache Set1(4kbytes) 10N march test.");
   Print("\n[6] Internal SRAM R/W test at 4k or 8k mode.");
   Print("\n    ->SRAM address used as data pattern.");
   Print("\n[7] Cache start up dialog for setup cache mode.");
   Print("\n[8] Cache configuration.");
   Print("\n[9] Change CPU Clock use by clkcon register.");
   Print("\n[C] Cache Memory(SET0[4k]/SET1[4k]) Clear function.");
   Print("\n[B] Pattern search in cache memory region.");
   Print("\n[V] System registers (SYSCFG, CLKCON, ROMCON...).");
   Print("\n[A] All 10N March Test.");
   Print("\n[Q] QUIT - Return main menu.");

   Print("\nSelect Test Item: ");
   it = get_upper();

   switch(it) 
    {
     case '1' : TagMarch10();         break; 	// test tag ram (256 words)
     case '2' : SramMarch10_4k();     break;	// test SRAM in 4k mode
     case '3' : SramMarch10_8k();     break;	// test SRAM in 8k mode	
     case '4' : Set0March10();        break;	// test cache set 0 in SRAM disable mode
     case '5' : Set1March10();        break;	// test cache set 1 in SRAM disable mode
     case '6' : InterSramTest();      break;	// test internal SRAM
     case '7' : CacheConfigure();     break;	// configure cache

     case '8' : 
// show cache configuration ////////////////////////////////////////////////////
      Print("\n\nCache configurations.\n");
      PrintCacheConfig();   
      break;	

     case '9' : CpuClockConfigure();  break;	// Configure CLKCON
     case 'C' : CacheClear();         break;	// Disable Stall En,Cache,Write En, and clear cache RAM
     case 'B' : SearchPattern();      break;	// Search pattern
     case 'A' : March10NAllTest();    break;	//
     case 'V' : SysRegsView();        break;	//

// 
     case 'Q' : return;
     default  : break;
    }

   Print("\nPress any key to continue.\n");
   it = get_upper();
   if(it == 'Q')
    {
     break;
    } 
  } 
}


/*
 *  All 10N March Test
 *  March-10N Test for Tag-RAM, 4K-SRAM, 8K-SRAM, Set0, Set1
 */


int March10NAllTest(void)
{
 unsigned int * tag;		// cache tag RAM base pointer 
 unsigned int * sram;		// SRAM base pointer  
 unsigned int * set1;		// cache SET1 base pointer  
 unsigned int * set0;		// cache SET0 base pointer	

//
 int result = 1;		// return value 
 int tagerr = 0;  		// Tag memory error flag for march test int delay = 0;
 int sramerr = 0; 		// sram flag for march error
 int seterr = 0;  		// set0 flag for march error
 int i;

//////////////////////////////////////////////////////////////////////////////// 
// test cache TAG RAM ////////////////////////////////////////////////////////// 
//////////////////////////////////////////////////////////////////////////////// 

 tag  = (unsigned int *)TagRAM;

/* Cache off,wr buf off,stall off */

 SYSCFG &= 			// 
 ~(
   SYSCFG_WRITE_BUFF	|	// write buffer enable (WE)
   SYSCFG_CACHE		|	// cache enable (CE)
   SYSCFG_STALL			// stall enable (SE)
  );
 Print("\nTag(256words) 10N March Test       ..... ");
 
/* tag(256 words) test by 10N march */
 if(March10N32(tag,256,0x00000000,1) == 0) { tagerr = 1; }
 if(March10N32(tag,256,0x0000ffff,1) == 0) { tagerr = 1; }
 if(March10N32(tag,256,0x00ff00ff,1) == 0) { tagerr = 1; }
 if(March10N32(tag,256,0x0f0f0f0f,1) == 0) { tagerr = 1; }
 if(March10N32(tag,256,0x33333333,1) == 0) { tagerr = 1; }
 if(March10N32(tag,256,0x55555555,1) == 0) { tagerr = 1; }

 if(tagerr) 
  {
   Print("Fail.") ;
   result = 0;
  }
 else
  {
   Print("Ok.") ;
  }


//////////////////////////////////////////////////////////////////////////////// 
// test SRAM in 4Kb mode ///////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

sram = (unsigned int *) (((SYSCFG >> 6) & 0x3FF) << 16);
// [15:6] = Internal SRAM Base Pointer  

Print("\nSRAM(4K bytes) 10N March Test      ..... ");

SYSCFG = 
 (SYSCFG & ~SYSCFG_CACHE_MASK) |	// 
  SYSCFG_CACHE_MODE_4KB_CACHE;		// 4 Kb cache, 4 Kb SRAM 

/* SRAM(2048 words) test by 10N march */

 if(March10N32(sram,1024,0x00000000,1) == 0) { sramerr = 1; }
 if(March10N32(sram,1024,0x0000ffff,1) == 0) { sramerr = 1; }
 if(March10N32(sram,1024,0x00ff00ff,1) == 0) { sramerr = 1; }
 if(March10N32(sram,1024,0x0f0f0f0f,1) == 0) { sramerr = 1; }
 if(March10N32(sram,1024,0x33333333,1) == 0) { sramerr = 1; }
 if(March10N32(sram,1024,0x55555555,1) == 0) { sramerr = 1; }

 if(sramerr) 
  {
   Print("Fail.");
   result = 0;
  }
 else 
  {
   Print("Ok.") ;
  }


//////////////////////////////////////////////////////////////////////////////// 
// test SRAM in 8Kb mode ///////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

 sramerr = 0; 				// clear SRAM error flag 

 sram = (unsigned int *) (((SYSCFG >> 6) & 0x3FF) << 16);

 Print("\nSRAM(8K bytes) 10N March Test      ..... ");

 SYSCFG = 
  (SYSCFG & ~SYSCFG_CACHE_MASK) | 	// clear cache bits
   SYSCFG_CACHE_MODE_8KB_SRAM;		// 8Kb SRAM, 0Kb cache     

/* SRAM(2048 words) test by 10N march */

 if(March10N32(sram,2048,0x00000000,1) == 0) { sramerr = 1; }
 if(March10N32(sram,2048,0x0000ffff,1) == 0) { sramerr = 1; }
 if(March10N32(sram,2048,0x00ff00ff,1) == 0) { sramerr = 1; } 
 if(March10N32(sram,2048,0x0f0f0f0f,1) == 0) { sramerr = 1; } 
 if(March10N32(sram,2048,0x33333333,1) == 0) { sramerr = 1; } 
 if(March10N32(sram,2048,0x55555555,1) == 0) { sramerr = 1; } 

 if(sramerr) 
  {
   Print("Fail.");
   result = 0;
  }
 else 
  {
   Print("Ok.") ;
  }


////////////////////////////////////////////////////////////////////////////////
// test cache SET0/1 in 8kb mode ///////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

 Print("\nCache[SET1]4K bytes 10N March Test ..... ");

 SYSCFG = 
  (SYSCFG & ~SYSCFG_CACHE_MASK) | 	// WE off, SE off, CE off 
   SYSCFG_CACHE_MODE_8KB_CACHE;		// 0Kb SRAM, 8Kb cache 

 seterr = 0; 				// clear march error flag

 set1 = (unsigned int *) Set1CacheRAM;
 for(i=0; i < 1024; i++) 
  {
   *set1 = 0x00000000;   		// Clear set1 RAM 
    set1++; 				// 
  }
	
 set1 = (unsigned int *) Set1CacheRAM;
 for(i=0; i < 1024; i++) 
  {
   if(*set1 != 0x00000000) 
    {
     seterr = 1; 
     result = 0;
     Print("[CACHE:ERROR] SET1[0x%x] = 0x%x!!\n", set1, *set1);
    }
   set1++; 
  } 

 if(seterr == 0)
  {
   set1 = (unsigned int *)Set1CacheRAM;
/* SET1(1024 words) test by 10N march */
   
   if(March10N32(set1,1024,0x00000000,1) == 0) { seterr = 1; } 
   if(March10N32(set1,1024,0x0000ffff,1) == 0) { seterr = 1; }
   if(March10N32(set1,1024,0x00ff00ff,1) == 0) { seterr = 1; } 
   if(March10N32(set1,1024,0x0f0f0f0f,1) == 0) { seterr = 1; } 
   if(March10N32(set1,1024,0x33333333,1) == 0) { seterr = 1; } 
   if(March10N32(set1,1024,0x55555555,1) == 0) { seterr = 1; } 
  }


 if(seterr) 
  {
   Print("Fail.");
   result = 0;
  }
 else 
  {
   Print("Ok.");
  }

////////////////////////////////////////////////////////////////////////////////
// test cache SET0 in 8Kb mode /////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

 Print("\nCache[SET0]4K bytes 10N March Test ..... ");

 SYSCFG = 
  (SYSCFG & ~SYSCFG_CACHE_MASK) |	// WE off, SE off, CE off
   SYSCFG_CACHE_MODE_8KB_CACHE;		// 8 Kb Cache, 0 Kb SRAM

// Clear SET0 Cache SRAM

 set0 = (unsigned int *)Set0CacheRAM;	// cache set 0 base pointer 
 for(i=0; i < 1024; i++) 		// 1K words 
  {
   *set0 = 0x00000000;   		// Clear ram 
    set0++; 
  }

 seterr = 0; 				// clear march error flag
 set0 = (unsigned int *)Set0CacheRAM;
 for(i=0; i < 1024; i++) 
  {
   if(*set0 != 0x00000000) 
    {
     seterr = 1; 			// clear march error flag
     result = 0;
     Print("[CACHE:ERROR] SET0[0x%x] = 0x%x!!\n",set0, *set0);
    }
   set0++; 
  }


 if(seterr == 0)
  {
   set0 = (unsigned int *)Set0CacheRAM;

/* SET0(1024 words) test by 10N march */

   if(March10N32(set0,1024,0x00000000,1) == 0) { seterr = 1; }
   if(March10N32(set0,1024,0x0000ffff,1) == 0) { seterr = 1; }
   if(March10N32(set0,1024,0x00ff00ff,1) == 0) { seterr = 1; }
   if(March10N32(set0,1024,0x0f0f0f0f,1) == 0) { seterr = 1; }
   if(March10N32(set0,1024,0x33333333,1) == 0) { seterr = 1; }
   if(March10N32(set0,1024,0x55555555,1) == 0) { seterr = 1; }
  }

 if(seterr) 
  {
   Print("Fail.");
   result = 0;
  }
 else 
  {
   Print("Ok.");
  }

 return(result);
}


////////////////////////////////////////////////////////////////////////////////
// init cache //////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////


void CacheInit(int cmd)
{
/* Disable cache before cache mode change */  

 SYSCFG &= 
  ~(
    SYSCFG_STALL     |			// stall enable bit 
    SYSCFG_CACHE     |			// cache enable bit 
    SYSCFG_CACHE_MODE|			// cache mode bits
    SYSCFG_WRITE_BUFF			// write buffer enable bit
   ); 

 switch(cmd) 
  {
   case CACHEINIT_4K	: 		/* 4K Cache,4K SRAM */

    SYSCFG |=
     (
      SYSCFG_CACHE_MODE_4KB_CACHE |	// set cache mode 00
      SYSCFG_WRITE_BUFF			// enable write buffer 
     ); 
    CacheFlush();			// cache flush 
    SYSCFG |= SYSCFG_CACHE; 		/* Cache Enable */ 
    break; 

   case CACHEINIT_8K	: 		/* 8K Cache */

    SYSCFG |=
     (
      SYSCFG_CACHE_MODE_8KB_CACHE |	// set cache mode 01 
      SYSCFG_WRITE_BUFF			// enable write buffer 
     ); 
    CacheFlush();			// cache flush
    SYSCFG |= SYSCFG_CACHE; 		/* Cache Enable */ 
    break; 

   case  CACHEINIT_0K 	: 		/* CACHE OFF: 8K SRAM */

    SYSCFG |=
     (
      SYSCFG_CACHE_MODE_8KB_SRAM  | 	// set cache mode 10
      SYSCFG_WRITE_BUFF			// enable write buffer 	
     );  
    CacheFlush();			// cache flush 

   default : break;
  }                
}