system.c

本source code 為s3c4510的bootloader

// 
   brgmin = 0xFFFFFFFF;			// init baudrate difference
//   
   if(un == 0)				// UART0 =>
    {					// read UARTBRD0
     brgout = UARTBRD0;			// register 
    }
   else
    {					// UART1 => 
     brgout = UARTBRD1;			// read UARTBRD1
    } 					// register


//
   cnt0 = (brgout >> 4) & 0xFFF;	// init min counter 0 (12 bit)	
   cnt1 =  brgout & 0xF;		// init min counter 1 

//
   for(c0 = 0; c0 < 4096; ++c0)		// c0 loop
    {
     for(c2 = 0; c2 <= 1; ++c2)		// c1 loop
      {
       switch(c2)
        {
         case  0 : c1 =  1; break;	// divide by  1
         case  1 : c1 = 16; break; 	// divide by 16
         default : break;
        }


// calculate baud rate /////////////////////////////////////////////////////////

       brgout = (CpuClk / 2) / (c0 + 1) / c1 / 16;

//
       if(brgout >= 38400)
        {				// 
         brgdif = brgout - 38400;	// 
        }
       else
        {
         brgdif = 38400 - brgout;
        }     

       if(brgdif < brgmin)
        {
         brgmin = brgdif;		// set min brg difference 
         cnt0 = c0;			// set min cnt0 counter  
         cnt1 = c2;			// set min cnt1 counter 
        }
      }
    }

// UARTBRD0/UARTBRD1 register //////////////////////////////////////////////////
 
   uartbrd = ((cnt0 & 0xFFF) << 4) | cnt1; 

   if(un == 0)
    {					
     uartbrd0 = uartbrd;		// UARTBRG0	
    }
   else
    {
     uartbrd1 = uartbrd;		// UARTBRG1
    } 
  } 

// new UART0 baudrate //////////////////////////////////////////////////////////

 cnt0 = (uartbrd0 >> 4) & 0xFFF;		// 
 cnt1 =  uartbrd0 & 0xF;			// 
 if(cnt1 == 0)
  {
   cnt1 = 1;
  }
 else
  {
   cnt1 = 16;
  }
 uartclk0 = (CpuClk / 2) / (cnt0 + 1) / cnt1 / 16;	

// new UART1 baudrate //////////////////////////////////////////////////////////

 cnt0 = (uartbrd1 >> 4) & 0xFFF;		// 
 cnt1 =  uartbrd1 & 0xF;			// 
 if(cnt1 == 0)
  {
   cnt1 = 1;
  }
 else
  {
   cnt1 = 16;
  } 
 uartclk1 = (CpuClk / 2) / (cnt0 + 1) / cnt1 / 16;	
#endif

/* Change DRAM refresh cycle */

// Get refresh count value /////////////////////////////////////////////////////
 BuffReg   = (REFEXTCON & 0xffe00000) >> 21;   // Get original refresh cycle
 RefCycle  = (2048 - BuffReg + 1) / fMCLK;     // Calculate refresh cycle
 BuffReg   =  2048 + 1 - (RefCycle * fMCLK / (divider + 1));

//Set refresh cycle //////////////////////////////////////////////////////////// 
 refextcon = (REFEXTCON & ~0xffe00000) | (BuffReg << 21);   

#ifndef EX_UCLK
 Print("\nUart Board Rate & DRAM refresh cycle");
 Print("\nwere changed automaitcally.\n");
#else
 Print("\nDRAM refresh cycle changed automaitcally.\n");
#endif

#ifndef EX_UCLK
 Print("\nUARTBRD0=0x%08x <- 0x%08x [%d]", UARTBRD0, uartbrd0, uartclk0);
 Print("\nUARTBRD1=0x%08x <- 0x%08x [%d]", UARTBRD1, uartbrd1, uartclk1);
#endif
 Print("\nREFEXTCON=0x%08x 0x%08x",refextcon,REFEXTCON);

/* Write divider value to clkcon register for change CPU clock  */
// Set CPU clock will be fMCLK/(divider+1)
 CLKCON = (divider & 0xFFFF) | (CLKCON & 0xFFFF0000);
 {
  int i; 
  for(i = 0; i < Delay4ClkCange; ++i); 	// delay for clock stabilizations
 }

/* Change UART Board Rate */
#ifndef EX_UCLK
 UARTBRD0 = uartbrd0; 			// set UARTBRD0 register 
 UARTBRD1 = uartbrd1; 			// set UARTBRD1 register 
#endif

/* Change DRAM refresh cycle */
 REFEXTCON = refextcon;   
}

////////////////////////////////////////////////////////////////////////////////  
// Search Pattern in cache SET0/1, DRAM bank 0/1/2/3 ///////////////////////////  
////////////////////////////////////////////////////////////////////////////////  


static void SearchPattern(void)
{
 unsigned long int  pattern;		// pattern 
 unsigned long int *Set0Pointer;	// base pointer for cache SET0 
 unsigned long int *Set1Pointer;	// base pointer for cache SET1
 unsigned long int *DramBasePoint;	// DRAM bank base point
 unsigned long int *DramNextPoint;	// DRAM bank next point
 unsigned long int i;
 U8 ch;

// 
 Print("\n\nEntern Search Pattern. 0x"); 
 pattern = get_number(16,0);

// search in cache SET 0 /////////////////////////////////////////////////////// 

 Print("\nSearch in Cache Set0."); 
 Set0Pointer  = (unsigned long int *)(Set0CacheRAM);
 for(i = 0; i < 1024; ++i) 
  {
   if(pattern == Set0Pointer[i]) 
    {
     Print
      (
       "\nSet 0 : Address = %08x, Data = %08x\n",
	  Set0Pointer + i, 
	*(Set0Pointer + i)
      );
    }
  }

// search in cache SET 1 /////////////////////////////////////////////////////// 

 Print("\nSearch in Cache Set1."); 
 Set1Pointer  = (unsigned long int *)(Set1CacheRAM);
 for(i = 0; i < 1024; ++i) 
  {
   if(pattern == Set1Pointer[i]) 
    {
     Print("Set 1 : Address = %08x, Data = %08x\n",
	Set1Pointer + i, Set1Pointer[i]);
    }
  }

 if((EXTDBWTH & EXTDBWTH_DSD0) != 0)
  {
   Print("\nSearch in DRAM Bank 0 [Y/N]"); 
   ch = get_upper();
 
   if(ch == 'Y')
    {
// DRAM bank 0 enabled => search in DRAM bank 0 ////////////////////////////////

     DramBasePoint = (unsigned long int *) (((DRAMCON0 >> 10) & 0x3FF) << 16);
     DramNextPoint = (unsigned long int *) (((DRAMCON0 >> 20) & 0x3FF) << 16);

     i = 0;
     while(DramBasePoint < DramNextPoint)
      {
       if (pattern == *DramBasePoint) 
        {
         Print
          (
           "DRAM 0 : Address = %08x, Data = %08x\n",
            DramBasePoint 	, 
           *DramBasePoint
          );
        }
       DramBasePoint += 1;
 
       i++;
       if((i % 1024) == 0)
        {
         PrintRotSlash((i / 1024) & 0x3);
        } 
      }
    }
  }

 if((EXTDBWTH & EXTDBWTH_DSD1) != 0)
  {
// DRAM bank 1 is enabled //////////////////////////////////////////////////////

   Print("\nSearch in DRAM Bank 1 [Y/N]"); 
   ch = get_upper(); 
 
   if(ch == 'Y')
    { 
     DramBasePoint = (unsigned long int *) (((DRAMCON1 >> 10) & 0x3FF) << 16);
     DramNextPoint = (unsigned long int *) (((DRAMCON1 >> 20) & 0x3FF) << 16);

     i = 0;
     while(DramBasePoint < DramNextPoint)
      {
       if (pattern == *DramBasePoint) 
        {
         Print
          (
           "\nDRAM 1 : Address = %08x, Data = %08x\n",
            DramBasePoint 	, 
           *DramBasePoint
          );
        }
       DramBasePoint += 1;
       i++;
       if((i % 1024) == 0)
        {
         PrintRotSlash((i / 1024) & 0x3);
        } 
      }
    }
  }

 if((EXTDBWTH & EXTDBWTH_DSD2) != 0)
  {
// DRAM base bank 2 is enabled /////////////////////////////////////////////////

   Print("\nSearch in DRAM Bank 2 [Y/N]"); 
   ch = get_upper();
   
   if(ch == 'Y')
    {
     DramBasePoint = (unsigned long int *) (((DRAMCON2 >> 10) & 0x3FF) << 16);
     DramNextPoint = (unsigned long int *) (((DRAMCON2 >> 20) & 0x3FF) << 16);

     i = 0;
     while(DramBasePoint < DramNextPoint)
      {
       if(pattern == *DramBasePoint) 
        {
         Print
          (
           "\nDRAM 0 : Address = %08x, Data = %08x\n",
              DramBasePoint 	, 
             *DramBasePoint
          );
        }
       DramBasePoint += 1;
       i++;
       if((i % 1024) == 0)
        {
         PrintRotSlash((i / 1024) & 0x3);
        } 
      }
    }
  }

 if((EXTDBWTH & EXTDBWTH_DSD3) != 0)
  {
// DRAM base bank 3 is enabled /////////////////////////////////////////////////

   Print("\nSearch in DRAM Bank 3 [Y/N]"); 
   ch = get_upper();
   if(ch == 'Y')
    {
     DramBasePoint = (unsigned long int *) (((DRAMCON3 >> 10) & 0x3FF) << 16);
     DramNextPoint = (unsigned long int *) (((DRAMCON3 >> 20) & 0x3FF) << 16);

     i = 0;
     while(DramBasePoint < DramNextPoint)
      {
       if (pattern == *DramBasePoint) 
        {
         Print
          (
           "DRAM 0 : Address = %08x, Data = %08x\n",
            DramBasePoint 	, 
           *DramBasePoint
          );
        }
       DramBasePoint += 1;
       i++;
       if((i % 1024) == 0)
        {
         PrintRotSlash((i / 1024) & 0x3);
        } 
      }
    }
  }
}

/////////////////////////////////////////////////////////////////////////////////
// print CLKCON content /////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////

static void PrintCLKCON(void)
{
 U32 reg[2];
 reg[0] = reg[1] = CLKCON; 
 PrintMBIT("CLKCON (Clock control register)");
 Print("0x%08x", CLKCON);
// 
 PrintMBIT("15:0 Clock Divided Value");
 Print("%x", (CLKCON & CLKCON_DIV_MASK));
// 16 ROM bank 5 wait enable
 PrintSBIT(0, "16 ROM bank 5 wait enable",       reg,CLKCON_ROM5_WAIT_EN   ,"1","0");     
// 
 PrintEBIT(0, "17 ROM bank 5 address/data Mux en",reg,CLKCON_ROM5_MUX_EN);     
 {
  ABIT mx_bt[] = {
    {"00(1 MCLK)", CLKCON_ROM5_MUX_TAC_1  },
    {"01(2 MCLK)", CLKCON_ROM5_MUX_TAC_2  },
    {"10(3 MCLK)", CLKCON_ROM5_MUX_TAC_3  },
    {"11(unused)", CLKCON_ROM5_MUX_TAC_UN },
    { 0, 0} 
  };
 
  PrintABIT(0, "19:18 Mux bus Address Cycle (tAC)",reg,CLKCON_ROM5_MUX_TAC,mx_bt);
 }

#ifdef _S3C4530_
 if(is_s3c4530(syscfg_pd_id)) {
   PrintEBIT(0,"20 ROM bank 5 wait 1 cycle delay",reg,CLKCON_ROM5_WAIT_DELAY); 
// 
   PrintEBIT(0,"21 ROM bank 4 wait enable",       reg,CLKCON_ROM4_WAIT_EN   );
   PrintEBIT(0,"22 ROM bank 4 wait 1 cycle delay",reg,CLKCON_ROM4_WAIT_DELAY);  
// 
   PrintEBIT(0,"23 ROM bank 3 wait enable",       reg,CLKCON_ROM3_WAIT_EN   );  
   PrintEBIT(0,"24 ROM bank 3 wait 1 cycle delay",reg,CLKCON_ROM3_WAIT_DELAY);
// 
   PrintEBIT(0,"25 ROM bank 2 wait enable",       reg,CLKCON_ROM2_WAIT_EN   );
   PrintEBIT(0,"26 ROM bank 2 wait 1 cycle delay",reg,CLKCON_ROM2_WAIT_DELAY);
// 
   PrintEBIT(0,"27 ROM bank 1 wait enable",       reg,CLKCON_ROM1_WAIT_EN   );
   PrintEBIT(0,"28 ROM bank 1 wait 1 cycle delay",reg,CLKCON_ROM1_WAIT_DELAY);
// 
   PrintEBIT(0,"29 ROM bank 0 wait enable",       reg,CLKCON_ROM0_WAIT_EN   );
   PrintEBIT(0,"30 ROM bank 0 wait 1 cycle delay",reg,CLKCON_ROM0_WAIT_DELAY);
 }
#endif								/* _S3C4530_ */

 PrintSBIT(0, "Test bit", reg, CLKCON_TEST_BIT,"1", "0");
}


static void PrintEXTACON(void)
{
//
 PrintMBIT("EXTACON 0&1");
 Print("0x%08x 0x%08x", EXTACON0, EXTACON1);
 Print("\nChip selection set-up time on nOE (tCOS0, tCOS1, tCOS2, tCOS3)");
 PrintMBIT("0:2   EXTACON0 tCOS0");Print("%d",(EXTACON0>>EXTACON0_TCOS0_OFFSET)&7);
 PrintMBIT("0:2   EXTACON1 tCOS2");Print("%d",(EXTACON1>>EXTACON1_TCOS2_OFFSET)&7);
 PrintMBIT("18:16 EXTACON0 tCOS1");Print("%d",(EXTACON0>>EXTACON0_TCOS1_OFFSET)&7);
 PrintMBIT("18:16 EXTACON1 tCOS3");Print("%d",(EXTACON1>>EXTACON1_TCOS3_OFFSET)&7);
//
 Print("\nAddress set-up time before nECS (tACS0, tACS1, tACS2, tACS3)");
 PrintMBIT("5:3   EXTACON0 tACS0");Print("%d",(EXTACON0>>EXTACON0_TACS0_OFFSET)&7);
 PrintMBIT("5:3   EXTACON1 tACS2");Print("%d",(EXTACON1>>EXTACON1_TACS2_OFFSET)&7);
 PrintMBIT("21:19 EXTACON0 tACS1");Print("%d",(EXTACON0>>EXTACON0_TACS1_OFFSET)&7);
 PrintMBIT("21:19 EXTACON1 tACS3");Print("%d",(EXTACON1>>EXTACON1_TACS3_OFFSET)&7);
//
 Print("\nChip selection hold time on nOE (tCOH0,tCOH1,tCOH2,tCOH3)");
 PrintMBIT("8:6   EXTACON0 tCOH0");Print("%d",(EXTACON0>>EXTACON0_TCOH0_OFFSET)&7);
 PrintMBIT("8:6   EXTACON1 tCOH2");Print("%d",(EXTACON1>>EXTACON1_TCOH2_OFFSET)&7);
 PrintMBIT("24:22 EXTACON0 tCOH1");Print("%d",(EXTACON0>>EXTACON0_TCOH1_OFFSET)&7);
 PrintMBIT("24:22 EXTACON1 tCOH2");Print("%d",(EXTACON1>>EXTACON1_TCOH3_OFFSET)&7);
//
 Print("\nAccess cycles (nOE low time (tACC0,tACC1,tACC2,tACC3)");
 PrintMBIT("11:9  EXTACON0 tACC0");Print("%d",(EXTACON0>>EXTACON0_TACC0_OFFSET)&7);
 PrintMBIT("11:9  EXTACON1 tACC2");Print("%d",(EXTACON1>>EXTACON1_TACC2_OFFSET)&7);
 PrintMBIT("27:25 EXTACON0 tACC1");Print("%d",(EXTACON0>>EXTACON0_TACC1_OFFSET)&7);
 PrintMBIT("27:25 EXTACON1 tACC2");Print("%d",(EXTACON1>>EXTACON1_TACC3_OFFSET)&7);
}

// print external bus width register content //////////////////////////////////// 

static void PrintEXTDBWTH(void) 
{
 int wn;
 PrintMBIT("EXTDBWTH Data Bus Width Register");
 Print("0x%0x", EXTDBWTH);

 for(wn  = 0; wn < 14; ++wn) {  
   U32 reg[2];
   static ABIT wd_bt[] = {
    {"00(disable)"  , 0},
    {"01(byte)"     , 1},
    {"10(half word)", 2},
    {"11(word)"     , 3},
    { 0, 0}
   };

   static ABIT wd_off[] = {
    {"ROM/SRAM/FLASH bank 0", EXTDBWTH_DSR0_OFF},
    {"ROM/SRAM/FLASH bank 1", EXTDBWTH_DSR1_OFF},
    {"ROM/SRAM/FLASH bank 2", EXTDBWTH_DSR2_OFF},
    {"ROM/SRAM/FLASH bank 3", EXTDBWTH_DSR3_OFF},
    {"ROM/SRAM/FLASH bank 4", EXTDBWTH_DSR4_OFF},
    {"ROM/SRAM/FLASH bank 5", EXTDBWTH_DSR5_OFF },

    {"DRAM bank 0"          , EXTDBWTH_DSD0_OFF},
    {"DRAM bank 1"          , EXTDBWTH_DSD1_OFF},
    {"DRAM bank 2"          , EXTDBWTH_DSD2_OFF},
    {"DRAM bank 3"          , EXTDBWTH_DSD3_OFF},

    {"External I/O bank 0"  , EXTDBWTH_DSX0_OFF},
    {"External I/O bank 1"  , EXTDBWTH_DSX1_OFF},
    {"External I/O bank 2"  , EXTDBWTH_DSX2_OFF},
    {"External I/O bank 3"  , EXTDBWTH_DSX3_OFF},
    { 0, 0}  
   };

   reg[0] = (EXTDBWTH >> wd_off[wn].val) & 0x3;
   PrintABIT(0, wd_off[wn].str, reg, 0x03, wd_bt);  
  }
}

// print ROMCON content  

static void PrintROMCON(int ch)
{
 U32 reg[6]; 				// regs content 
 int cnt;				// reg count 
 int cn;				// reg number 

 reg[0] = ROMCON0; 			// bank 0 config reg 
 reg[1] = ROMCON1; 			// bank 1 conf reg 	
 reg[2] = ROMCON2; 			// bank 2 conf reg
 reg[3] = ROMCON3; 			// bank 3 conf reg 	
 reg[4] = ROMCON4; 			// bank 4 conf reg
 reg[5] = ROMCON5; 			// bank 5 conf reg

 if(ch >= 0) {
   cnt = ch + 1;
 } else {
   cnt = -ch;
 }

// print ROMCON content /////////////////////////////////////////////////////////
 Print("\nROMCON"); 
 if(ch >= 0 && ch < 6) {
  Print("%d 0x%08x", ch, reg[ch]);
 } else {
   for(cn = 0; cn < cnt; ++cn) {
    Print("%d=%08x", cn, reg[cn]);
   } 
 }

 { 
// page mode configuration //////////////////////////////////////////////////////
  PrintMBIT("1:0 Page mode configuration (PMC)");
  for(cn = 0; cn < cnt; ++cn) 
   {
    if((cn == ch || ch < 0) == 0) 
     {
      continue;
     } 
//
    switch(reg[cn] & ROMCON_PMC) 
     {
      case ROMCON_PMC_NORMAL : Print(" 00/N "); break;
      case ROMCON_PMC_4WPAGE : Print(" 01/4w"); break;
      case ROMCON_PMC_8WPAGE : Print(" 10/8w"); break;
      case ROMCON_PMC_16WPAGE: Print(" 11/16"); break;
      default :
       break;    
     }
   }
  Print("\n00=Normal ROM; 01=4-word page; 10=8-word page; 11=16-word page");
 }

 {
// [3:2] Page address access time (tPA) /////////////////////////////////////////
  PrintMBIT("3:2 Page address access time (tPA)");
  for(cn = 0; cn < cnt; ++cn) 
   {
    if((cn == ch || ch < 0) == 0)
     {
       continue;
     }
    switch(reg[cn] & ROMCON_TPA)
     {
      case ROMCON_TPA_5CLK: Print(" 00/5 "); break;
      case ROMCON_TPA_2CLK: Print(" 01/2 "); break;
      case ROMCON_TPA_3CLK: Print(" 10/3 "); break;
      case ROMCON_TPA_4CLK: Print(" 11/4 "); break;
      default:
       break;
     }
   }
  Print("\n00=5 CLK;01=2 CLK;10=3 CLK; 11=4 CLK");
 }

 {
// [6:4]   Programmable access cycle (tACC) /////////////////////////////////////
  PrintMBIT("6:4 Programmable access cycle (tACC)");
  
  for(cn = 0; cn < cnt; ++cn)
   {
    if((cn == ch || ch < 0) == 0)
     {
      continue;
     }

    switch(reg[cn] & ROMCON_TACC)
     {
      case ROMCON_TACC_DISABLE : Print(" 000/D"); break;
      case ROMCON_TACC_2CLK    : Print(" 001/2"); break;
      case ROMCON_TACC_3CLK    : Print(" 010/3"); break;
      case ROMCON_TACC_4CLK    : Print(" 011/4"); break;
      case ROMCON_TACC_5CLK    : Print(" 100/5"); break;
      case ROMCON_TACC_6CLK    : Print(" 101/6"); break;
      case ROMCON_TACC_7CLK    : Print(" 110/7"); break;
      case ROMCON_TACC_UNUSED  : Print(" 111/R"); break;
      default:
       break;
     }
   }

   Print("\n000=Disable  ;001=2 cycles;010=3 cycles;011=4 cycles)");
   Print("\n100=5 cycles);101=6 cycles;110=7 cycles;111=Reserved)");
  }

//
 PrintMBIT("19:10  base pointer");
 for(cn = 0; cn < cnt; ++cn) {