system.c

本source code 為s3c4510的bootloader

int SramMarch10_8k(void)
{
 unsigned int * sram;			// internam SRAM pointer 
 U32 syscfg;				// saved SYSCFG
 int err = 0;  				// sram flag for march error

 Print("\n\nSRAM(8K bytes) test by 10N march algorithm.");

 syscfg = SYSCFG;			// save SYSCFG 
 CacheClear();    			// Clear the cache memory

 sram = (unsigned int *) (((SYSCFG >> 6) & 0x3FF) << 16);

//[0]	Stall Enable (SE)
//[1]	Cache Enable (CE)
//[2] 	Write Buffer Enable (WE)
//[3]	0
//[5:4] Cache Mode (CM)
// 	00 = 4Kb SRAM, 4Kb Cache 
//	01 = 0Kb SRAM, 8Kb Cache 
//	10 = 8Kb SRAM, 0Kb Cache
//NOTE: When you write 10 to this field, the cache enable bit is cleared
// 	automatically
//[15:6]Internal SRAM base pointer     
 

// 
 SYSCFG = 
  (
    SYSCFG & 				// clear cache bits
   ~SYSCFG_CACHE_MASK			// 
  ) |
 SYSCFG_CACHE_MODE_8KB_SRAM;		// set internal SRAM to 8Kb mode
 PrintCacheConfig();			// print cache configuration

/* SRAM(2048 words) test by 10N march */
 Print("\n");
 if(March10N32(sram,2048,0x00000000,256) == 0) { err = 1; }
 if(March10N32(sram,2048,0x0000ffff,256) == 0) { err = 1; }
 if(March10N32(sram,2048,0x00ff00ff,256) == 0) { err = 1; }
 if(March10N32(sram,2048,0x0f0f0f0f,256) == 0) { err = 1; }
 if(March10N32(sram,2048,0x33333333,256) == 0) { err = 1; }
 if(March10N32(sram,2048,0x55555555,256) == 0) { err = 1; } 

//
 SYSCFG = syscfg; 			// restore SYSCFG

// 
 if(err) 
  {
   Print("\nFail.\n");
   return(0);
  }
 else 
  {
   Print("\nOk.\n");
   return(1);
  }
}

////////////////////////////////////////////////////////////////////////////////
// test SET1 RAM (Cache in 8Kb mode) ///////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////


int Set1March10(void)
{
 unsigned int * set1;			// Cache SET1 pointer
 U32 syscfg;				// saved SYSCFG
 int err = 0;  				// set0 flag for march error

// 
 Print("\n\nCache[SET1]4K bytes tested by 10N march algorithm.\n");

// 
 syscfg = SYSCFG;			// save SYSCFG		
 CacheClear();    			// Clear the cache memory

// 
 set1 = (unsigned int *) Set1CacheRAM;	// cache set1 pointer 

 SYSCFG = 
  (
    SYSCFG & 				// clear cache bits 
   ~SYSCFG_CACHE_MASK			// 
  )|
 SYSCFG_CACHE_MODE_8KB_CACHE;		// 01 0Kb SRAM, 8Kb cache 
 PrintCacheConfig();			// print cache config 

//
 Print("\n");
 if(March10N32(set1,1024,0x00000000,256) == 0) { err = 1; }
 if(March10N32(set1,1024,0x0000ffff,256) == 0) { err = 1; }
 if(March10N32(set1,1024,0x00ff00ff,256) == 0) { err = 1; }
 if(March10N32(set1,1024,0x0f0f0f0f,256) == 0) { err = 1; }
 if(March10N32(set1,1024,0x33333333,256) == 0) { err = 1; }
 if(March10N32(set1,1024,0x55555555,256) == 0) { err = 1; }


// 
 CacheFlush();				// clear cache tag RAM 
 SYSCFG = syscfg;			//
 
 if(err) 
  {
   Print("\nFail.\n");
   return(0);
  }
 else 
  {
   Print("\nOk.\n");
   return(1);
  }
}

////////////////////////////////////////////////////////////////////////////////
// test cache set0 RAM (cache in 8Kb mode) /////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////


int Set0March10(void)
{
 unsigned int * set0;			// cache set0 pointer
 U32 syscfg;				// saved SYSCFG
 int err = 0; 				// error flag 

 Print("\n\nCache Set0,4K bytes,tested by 10N march algorithm.\n");

//
 syscfg = SYSCFG;			// save SYSCFG
 CacheClear();    			// Clear the cache memory

// 
 set0 = (unsigned int *) Set0CacheRAM;	// set0 pointer 

 SYSCFG = 
  (
    SYSCFG & 				// clear cache bits
   ~SYSCFG_CACHE_MASK			//
  )|
 SYSCFG_CACHE_MODE_8KB_CACHE;		// 8 Kb Cache 
 PrintCacheConfig();			// print cache configuration
 

/* SET0(1024 words) test by 10N march */

 Print("\n");
 if(March10N32(set0,1024,0x00000000,256) == 0) { err = 1; } //
 if(March10N32(set0,1024,0x0000ffff,256) == 0) { err = 1; } //
 if(March10N32(set0,1024,0x00ff00ff,256) == 0) { err = 1; } //
 if(March10N32(set0,1024,0x0f0f0f0f,256) == 0) { err = 1; } //
 if(March10N32(set0,1024,0x33333333,256) == 0) { err = 1; } //
 if(March10N32(set0,1024,0x55555555,256) == 0) { err = 1; } //


//
 CacheFlush();				// clear cache tag ram 
 SYSCFG = syscfg;			// restore SYSCFG

 if(err) 
  {
   Print("\nFail.\n");
   return(0);
  }
 else 
  {
   Print("\nOk.\n");
   return(1);
  }
}


////////////////////////////////////////////////////////////////////////////////
// Internal SRAM read & write, compare test  ///////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

static void InterSramTest(void)
{
 unsigned int * addr;			// pointer in internal SRAM
 unsigned int * base;  			// Internal SRAM Base Address
 U32 syscfg;				// saved SYSCFG
 int cnt;				// internal ram words count 
 int err;				// error flag 
 char ch;
 int i;

//
 syscfg = SYSCFG;

// 
 base = (unsigned int *) (((SYSCFG >> 6) & 0x3FF) << 16);  


//[0]	Stall Enable (SE)
//[1]	Cache Enable (CE)
//[2] 	Write Buffer Enable (WE)
//[3]	0
//[5:4] Cache Mode (CM)
// 	00 = 4Kb SRAM, 4Kb Cache 
//	01 = 0Kb SRAM, 8Kb Cache 
//	10 = 8Kb SRAM, 0Kb Cache
//NOTE: When you write 10 to this field, the cache enable bit is cleared
// 	automatically
//[15:6]Internal SRAM base pointer     


 Print("\n\nInternal SRAM test."); 
 Print("\n8K SRAM test? If NO,default 4K SRAM tested?[Y/N]"); 

 ch = get_upper();
          
 if(ch == 'Y') 
  {
//////////////////////////////////////////////////////////////////////////////// 
// set cache mode : SRAM - 8Kb , 0Kb Cache ///////////////////////////////////// 

   SYSCFG = 
    (
     SYSCFG & 				// clear cache bits
    ~SYSCFG_CACHE_MASK
    )|
   SYSCFG_CACHE_MODE_8KB_SRAM;		// 8Kbyte cache mode 

   cnt = 2048;				// 
   PrintCacheConfig();			// print cache config
   Print("\nSRAM Address:0x%08x~0x%08x",base, base+cnt); 
  }
 else 
  {
// set cache mode : SRAM - 4Kb, 4Kb cache //////////////////////////////////////  

   SYSCFG = 
    (
      SYSCFG & 				// clear cache mask
     ~SYSCFG_CACHE_MASK
    )|
   SYSCFG_CACHE_MODE_4KB_CACHE;		// set 4Kb cache mode 
  
   cnt = 1024;				// internal RAM size = 4Kb (1K words)
   PrintCacheConfig();			// print cache config		
   Print("\nSRAM Address:0x%08x~0x%08x",base,base+cnt); 
  }

 Print("\n");

// 
 addr = base;				// 

 for(i = 0; i < cnt; ++i) 
   {
    * addr = (unsigned int) addr;     	// write memory data
      addr++;				// increment address pointer 
   }

//
 err = 0;

 addr = base;

 for(i = 0; i < cnt; ++i) 
  {
   if(*addr != (unsigned int) addr)
    {
     err = 1;
     Print("\nError [0x%08x] == 0x%08x",addr,*addr);
    } 
   addr++;
  }

// 
 CacheFlush();				// clear cache tag ram 
 SYSCFG = syscfg; 			// restore syscfg

// 
 if(err == 1)
  {
   Print("\nFail.\n");
  }
 else
  {
   Print("\nOk.\n");
  }
}

////////////////////////////////////////////////////////////////////////////////
// Cache flush function for re-configuration cache mode ////////////////////////
////////////////////////////////////////////////////////////////////////////////

void CacheFlush(void)
{
 int i;
 unsigned int * tagram; 

 tagram = (unsigned int *)TagRAM;
 SYSCFG &= ~SYSCFG_CACHE;  		// Disable cache before cache flush

 for(i = 0; i < 256; ++i) 
  {
   *tagram = 0x00000000;   		// Clear tag ram 
    tagram += 1; 
  }
 Print("\nCache Tag Ram cleared.");
}


////////////////////////////////////////////////////////////////////////////////
// Setup System manager dialog for Cache & SRAM test ///////////////////////////
////////////////////////////////////////////////////////////////////////////////


static void CacheConfigure(void)
{
 unsigned int n;
 REG32  Reg;
 char ch;

 Print("\n\nCache Configurations."); 

////////////////////////////////////////////////////////////////////////////////
// Select Stall enable or disable //////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

 while(1) 
  {
   Print("\nStall Enable?         [Y/N]"); 
   ch = get_upper(); 
   if(
     ch == 'N' || 
     ch == 'Y'
    )
    {
     break; 
    }
  } 

 if(ch == 'Y') 
  {
   SYSCFG |=  SYSCFG_STALL;		// enable stall
  }
 else
  {
   SYSCFG &= ~SYSCFG_STALL;		// disable stall
  }  

////////////////////////////////////////////////////////////////////////////////
// Select write buffer enable/disable //////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

 while(1) 
  {
   Print("\nWrite buffer Enable?  [Y/N]"); 
   ch = get_upper(); 
   if(
     ch == 'N' || 
     ch == 'Y'
    )
    {
     break; 
    }
  }

 if(ch == 'Y') 
  {
   SYSCFG |=  SYSCFG_WRITE_BUFF; 	// enable write buffer
  }
 else 
  {
   SYSCFG &= ~SYSCFG_WRITE_BUFF; 	// disable write buffer
  }

////////////////////////////////////////////////////////////////////////////////
// Select Cache mode ///////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

 SYSCFG &= ~SYSCFG_CACHE;      		// Disable cache before cache mode change  
 Reg = (~SYSCFG_CACHE_MODE & SYSCFG);	// clear previous CM bit
 while(1) 
  {
   Print("\nCache Mode"); 
   Print("\n0. 4K-bytes SRAM, 4K-bytes Cache."); 
   Print("\n1. 0K-bytes SRAM, 8K-bytes Cache."); 
   Print("\n2. 8K-bytes SRAM, 0K-bytes Cache."); 
   Print("\nSelect number ");
   n = get_upper();

   if(n == '0')
    {
// 4K-bytes SRAM, 4K-bytes Cache
     Reg |= SYSCFG_CACHE_MODE_4KB_CACHE; 
     break;
    }
   else
   if(n == '1')
    {
// 0K-bytes SRAM, 8K-bytes Cache
     Reg |= SYSCFG_CACHE_MODE_8KB_CACHE; 
     break;
    }
   else 
   if(n == '2')
    {
// 8K-bytes SRAM, 0K-bytes Cache
     Reg |= SYSCFG_CACHE_MODE_8KB_SRAM; 
     break;
    }
   else
    {
     continue;
    }
  }

 SYSCFG = Reg;

////////////////////////////////////////////////////////////////////////////////
// Select Cache enable/disable /////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

 if( (SYSCFG & SYSCFG_CACHE_MODE) == SYSCFG_CACHE_MODE_8KB_SRAM)
  {
   Print("\nCache Disabled"); 
   ch = 'N';
  }
 else
  { 
   do 
    {
     Print("\nCache Enable?         [Y/N]"); 
     ch = get_upper(); 
    } 
   while((ch != 'N') && (ch != 'Y'));
  }

// 
 CacheFlush();   			// Tag ram clear before cache enable

 if(ch == 'Y') 
  {
   SYSCFG |=  SYSCFG_CACHE; 
  }
 else 
  {
   SYSCFG &= ~SYSCFG_CACHE; 
  }

// print cache configuration ///////////////////////////////////////////////////

 PrintCacheConfig();
}

////////////////////////////////////////////////////////////////////////////////
// CPU clock control function //////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

static void CpuClockConfigure(void)
{
 unsigned int divider;			// clock divider 
 unsigned int CpuClk; 			// CPU Clock  
 unsigned long RefCycle;  		// for refresh cycle
 unsigned long BuffReg; 

// 
 U32 refextcon;				// new content REFEXTCON

//
#ifndef EX_UCLK				// 
 U32 uartbrd0;				// new content UARTBRD0
 U32 uartbrd1;				// new content UARTBRD1
 U32 uartclk0; 				// new UART0 baudrate 
 U32 uartclk1; 				// new UART1 baudrate 
 U32 cnt0;				// min counter 0
 U32 cnt1;				// min counter 1 
 U32 un;				// UART number 
#endif					// 

//  
 Print("\n\nCPU Clock change.");
      
 while(1)
  {
   unsigned int tmpdiv;			// clock divider 
   char ch;				//
   int i;				//

// 
   Print("\nEnter Clock divider value 0x");
//argument value is the number of hexa digit.
   divider = get_number(16, 0);  	// read divider from console 

// 
   tmpdiv = divider & 0xFFFF;		// clear upper 16 bits
   for(i = 0; i < 16; ++i)		// find first non sero bit
    {
     if((tmpdiv & (1 << i)) != 0)
      {
       tmpdiv &= (1 << i);		// clear other bits
/*[15:0] Clock Divided Value 						*/
/* 	 If all bits are 0, a non-divided clock is used. Only one bit 	*/ 
/*	 can be set in CLKCON[15:0]. That is, the clock dividing 	*/
/* 	 values is defined as 1,2,4,8,16 ... 				*/ 
/* 	 Internal system clock, fMCLK = fICLK / (CLKCON + 1) 		*/ 
       break;
      }
    }

   if(divider != tmpdiv)
    {
// input value for divider is not equal to checked /////////////////////////////
     Print("\nNot correct input divider = 0x%x", divider);
     Print("\nOnly one bit can be set in CLKCON[15:0]");
     Print("\nUsed = 0x%x", tmpdiv); 
     divider = tmpdiv;
    }

/* Calculate CPU Clock from arqument divider value */
          
   CpuClk = fMCLK / (divider + 1); 

   Print
    (
     "\nCPU clock frequency is %d.%d Mhz.", 
        CpuClk / 1000000, 
       (CpuClk / 1000) % 1000
    ); 
// 
   Print("\nReset clkcon register?[Y/N]"); 
   ch = get_upper();
   if(ch == 'Y')
    {
     break;
    }  
   else
   if(ch == 'N')
    {
     return; 
    }
  } 

//
 Print("\nNow Clock changed CLKCON=0x%x",divider);

/******************************************************************************/ 
/* [3:0]        Baud rate divisor value CNT1 				      */
/*               xxx0 = divide by 1 					      */
/*               xxx1 = divide by 16 					      */
/* [15:4] 	Time constant value for CNT0 				      */
/* 									      */
/* BRGOUT = (MCLK2 or UCLK) / (CNT0 + 1) / (16^CNT1) / 16		      */
/******************************************************************************/ 

/* Change UART Board Rate */
#ifndef EX_UCLK
 for(un = 0; un < 2; ++un)		// for UART0/UART1 
  {
   U32 uartbrd;				// UART baud rate
   U32 brgmin;				// min baudrate difference 
   U32 brgout;				// temp baudrate
   U32 brgdif;				// temp baudrate difference
   U32 c0;				// temp counter 0  
   U32 c1;				// temp counter 1
   U32 c2;