system.c

本source code 為s3c4510的bootloader

/*************************************************************************/
/*                                                                       */
/* FILE NAME                                      VERSION                */
/*                                                                       */
/*      system.c                   KS32C5000, KS32C50100   : version 1.0 */
/*                                                                       */
/* COMPONENT                                                             */
/*                                                                       */
/*                                                                       */
/* DESCRIPTION                                                           */
/*                                                                       */
/*                                                                       */
/* AUTHOR                                                                */
/*                                                                       */
/*      Young Sun KIM, Samsung Electronics, Inc.                         */
/*                                                                       */
/* DATA STRUCTURES                                                       */
/*                                                                       */
/*                                                                       */
/* FUNCTIONS                                                             */
/*                                                                       */
/*            Cache & internal SRAM test module.                         */
/*                                                                       */
/* DEPENDENCIES                                                          */
/*                                                                       */
/*                                                                       */
/* HISTORY                                                               */
/*                                                                       */
/*         NAME            DATE                    REMARKS               */
/*                                                                       */
/*        in4maker      09-15-1998      Created initial version 1.0      */
/*                                                                       */
/*************************************************************************/

/* 			*/
/* Modified by 		*/
/* Dmitriy Cherkashin 	*/
/* [e-mail]	*/
/* 2002			*/
/*			*/

#include "ks32c50.h"
#include "evm50100.h"


/************************************************************************/
/*  This function is parts of 10N march Algorithms			*/
/*  Memory  read[pattern] & write[~pattern] or 				*/
/*          read[~pattern] & write[~pattern] 				*/
/*  on increment or decrement address.					*/
/*									*/	
/*  MarchSub1(base or end address,word count, pattern,address direction)*/
/************************************************************************/


static int MarchSub1(unsigned int * addr, int unit, unsigned int pattern, int dir, int prog)
{
 unsigned int i;
 unsigned int rdata;			/* read data */
 int rvl = 1;				// return value

// 
 for(i = 0; i < unit; ++i)
  {
   if(prog != 0)
    {
     PrintRotSlash((i / prog) & 0x3);
    }
  
   rdata = *addr;     			/* read memory data */
   if(rdata != (~pattern)) 
    {
     Print("\nError [0x%08x] = 0x%08x. Must be 0x%08x", addr, rdata, ~pattern);
     rvl = 0; 				// clear return value
    }
  *addr = pattern;   			/* write data pattern */
   addr += dir;				// to net position 
  }

 return(rvl); 				
}


/************************************************************************/
/* Main 10N March Algorithm						*/
/* March10N32(base address, word size, pattern)				*/
/************************************************************************/


int March10N32(unsigned int *addr, int unit, unsigned int pattern, int prog)
{
 unsigned int *tempAddr;
 int rvl = 1; 				/* error flag for march test */
 int i;

//     
 tempAddr = addr;  
   
/* Write pattern on memory */

 for(i = 0; i < unit; i++)
  {
   *tempAddr++ = pattern;
// 
   if(prog != 0)
    {
     PrintRotSlash((i / prog) & 0x3);
    }
  }
   
 /* Sub Algorithm for Read & Write compare in memory 
  * _MarchSub1(end or base address,memory word size,pattern,addr dir); 
  *1 means increment, -1 is decrement address 
  */

/* test from start to end */

//  
 if(
   MarchSub1
    (
     addr	,			/* start address */
     unit	,			/* word count */
     ~pattern	,			/* xor pattern */
      1		,			/* from start fo end */
     prog 
    ) == 0				
  ) 
  {
   rvl = 0;				// clear return value
  }

//   
 if(
   MarchSub1
    (
     addr	,			/* start */
     unit	,			/* number of words */
     pattern    , 			/* pattern */
     1		,			/* from the start to end */
     prog 
    ) == 0
  ) 
  {
   rvl = 0;				// clear return value
  }

/* from end */

 if(
   MarchSub1
    (
     addr+unit-1,			/* end word address */
     unit	,			/* number of the words */
     ~pattern	,			/* */
     -1		,			/* post decrement */
     prog 
    ) == 0
  ) 
  {
   rvl = 0;				// clear return value
  }

//   
 if(
   MarchSub1
   (
    addr+unit-1	,			/* end adress item */
    unit	,			/* number of the words */
    pattern 	,			/* pattern */
    -1		,			/* post decrement ! */
    prog 
   ) == 0
  ) 
  {
   rvl = 0;      			// clear return value
  } 

 tempAddr = addr;

/* Read & test memory */

 for(i = 0; i < unit; ++i)
  {
   if(prog != 0)
    {
     PrintRotSlash((i / prog) & 0x3);
    }

   if(*tempAddr != pattern)
    {
     rvl = 0;
     Print("\nError [0x%08x] = 0x%08x. Must be 0x%08x",tempAddr,*tempAddr,pattern);
    }
   tempAddr++;
  }

 if(prog != 0)
  {
   put_byte(' ');
   put_byte('\b');
  }

// 
 return(rvl);  				/* return error code */	
}

////////////////////////////////////////////////////////////////////////////////
// print content of SYSCFG /////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////


void PrintCacheConfig(void)
{
 U32 reg[2];
 reg[0] = reg[1] = SYSCFG;
 PrintMBIT("SYSCFG");
 Print("0x%08x", SYSCFG);
// (SE) Stall enable bit ///////////////////////////////////////////////////////
 PrintEBIT(0, "Stall enable (SE)", reg, SYSCFG_STALL);
// (CE) Cache enable bit ///////////////////////////////////////////////////////
 PrintEBIT(0, "Cache enable (CE)", reg, SYSCFG_CACHE);
// (WE) Write enable bit ///////////////////////////////////////////////////////
 PrintEBIT(0, "Write enable (WE)", reg, SYSCFG_WRITE_BUFF);

#ifdef _S3C4530_
 if(is_s3c4530(syscfg_pd_id)) {	
    PrintEBIT(0, "Fixed priority (FP)", reg, SYSCFG_FP);
 }	
#endif								/* _S3C4530_ */

 {
// (CM) Cache mode /////////////////////////////////////////////////////////////
  ABIT cm_bt[] = {
    {"00(4Kb SRAM, 4Kb cache)", SYSCFG_CACHE_MODE_4KB_CACHE},
    {"01(0Kb SRAM, 8Kb cache)", SYSCFG_CACHE_MODE_8KB_CACHE},
    {"10(8Kb SRAM, 0Kb cache)", SYSCFG_CACHE_MODE_8KB_SRAM},
    { 0, 0}
  };
  PrintABIT(0, "Cache mode (CM)", reg, SYSCFG_CACHE_MODE, cm_bt);
 }

 {
// product ID ///////////////////////////////////////////////////////////////////
  char *pstr = "(unknown)"; 	
#ifdef _S3C4530_
// compiled with S3C4530 support
  switch(SYSCFG & SYSCFG_PD_ID)
   {
    case SYSCFG_PD_KS32C50100 : pstr = "S3C4510"; break;
    case SYSCFG_PD_S3C4510B   : pstr = "S3C4510B"; break;
    case SYSCFG_PD_S3C4530X   : pstr = "S3C4530X"; break;
    case SYSCFG_PD_S3C4530A   : pstr = "S3C4530A"; break;
    default : break;	
   }
#else
#ifdef _KS32C50100_
// compiled with KS32C50100 support
  switch(SYSCFG & SYSCFG_PD_ID)
   {
    case SYSCFG_PD_KS32C5000  : pstr = "KS32C5000"; break;
    case SYSCFG_PD_KS32C50100 : pstr = "KS32C50100"; break;
    default : break;	
   }
#endif
#endif								/* _S3C4530_ */
  PrintMBIT("Product Identifier");
  Print("%s", pstr);
 }
}


/************************************************************************/
/*  Cache Memory(256 word Tag RAM,8k-bytes SRAM 			*/
/*  Cache memory test use by 10N march algorithm			*/
/*  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~		*/
/*  - Cache memory address range					*/
/*     Tag  = 0x1100_0000~0x1100_0400 (256word)				*/
/*  									*/
/*     . at Cache Mode : 8kb SRAM, 0kb Cache				*/
/*        SRAM = 0x3fe0000~0x3fe02000  (8k bytes)			*/
/************************************************************************/


int TagMarch10(void)
{
 unsigned int *tag;			// Tag memory address 	
 U32 syscfg;				// saved syscfg
 int rvl = 1;  				// Tag memory error flag for march test int delay = 0;
	
 tag  = (unsigned int *) TagRAM;	// tag RAM base address

// Disable Cache,Disable write buffer off,clear stall enable bit ///////////////

 syscfg  = SYSCFG;			// save syscfg 
 SYSCFG &= 				// Clear Cache Configuration Bits
  ~(
    SYSCFG_WRITE_BUFF	|		// clear write buffer bit
    SYSCFG_CACHE	|		// clear cache enable bit
    SYSCFG_STALL			// clear stall enable bit
   );


 Print("\n\nTag(256words) Test by 10N march algorithm");
 PrintCacheConfig();			// print new cache mode

/* tag(256 words) test by 10N march */

 Print("\n");
 if(March10N32(tag,256,0x00000000,32) == 0) { rvl = 0; } // 
 if(March10N32(tag,256,0x0000ffff,32) == 0) { rvl = 0; } // 
 if(March10N32(tag,256,0x00ff00ff,32) == 0) { rvl = 0; } // 
 if(March10N32(tag,256,0x0f0f0f0f,32) == 0) { rvl = 0; } // 
 if(March10N32(tag,256,0x33333333,32) == 0) { rvl = 0; } // 
 if(March10N32(tag,256,0x55555555,32) == 0) { rvl = 0; } // 

 if(rvl == 0) 
  {
   Print("\nFail.\n");
  }
 else
  {
   Print("\nOk.\n");
  }

//
 CacheFlush();				// clear tag memory 
 SYSCFG = syscfg;			// restore SYSCFG  
 return(rvl);
}


/************************************************************************/
/* Set0, Set1 Cache memory clear function 				*/
/* clear Stall Enable, Write Buffer Enable, Cache enable bits, and set  */
/* cache mode bits to 01 (0K - SRAM, 8K - CACHE). Then cache sets 0,1	*/ 
/* are cleared. Tag RAM is not cleared.					*/
/************************************************************************/


int CacheClear(void)
{
 unsigned int * tagram; 		// pointer to tag RAM
 unsigned int * set0;			// pointer to set 0 RAM
 unsigned int * set1;			// pointer to set 1 RAM
 U32 syscfg; 				// saved syscfg
 int rvl;				// return code (1 = success, 0 = failure)
 int err;				// error flag
 int i;					// index

//
 rvl = 1;				// start return value

// 
 set0 = (unsigned int *) Set0CacheRAM;	// pointer to set0 RAM
 set1 = (unsigned int *) Set1CacheRAM;	// pointer to set1 RAM

// 
 err  = 0;				// no error

 Print("\nSET0(4k),SET1(4K) Cache memory clear Start");

 syscfg = SYSCFG;			// save SYSCFG
 SYSCFG = 
  (
// Clear CACHE Configuration bits in SYSCFG: ///////////////////////////////////
     SYSCFG & 			/* Stall Enable(SE), Cache Enable (CE) */	
    ~SYSCFG_CACHE_MASK		/* Write Buffer enable (WE), Cache mode (CM)*/
   )
  |
// and set CACHE/SRAM mode to : SRAM 0k, cache 8k //////////////////////////////
 SYSCFG_CACHE_MODE_8KB_CACHE;		
 									
// Clear Cache SET0 ram (4K) ///////////////////////////////////////////////////
 for(i=0; i < 1024; i++) 	/* 1024 words */	
  {
   * set0 = 0x00000000;   	/* clear set 0 RAM word */		
     set0++; 			/* increment pointer in set0 */
  }

// Check set0 RAM is cleared ///////////////////////////////////////////////////

 set0 = (unsigned int *)Set0CacheRAM;	/* restore pointer */

 for(i = 0; i < 1024; ++i) 	/* for set0 items */
  {
   if(*set0 != 0x00000000) 
    {												
// non zero => set error flag and print diagnostig message /////////////////////
     err = 1;
     Print("\nClear Cache SET0 ERROR. SET0[0x%x] = 0x%x",set0, *set0);
    }
   set0++; 
  }
    
 if(err) 
  {
   rvl = 0;
   Print("\nFail. SET0 Cache Memory Not Cleared.");
  }
 else 
  {
   Print("\nSET0 Cache Memory Cleared.");
  }   

									
// Clear SET1 RAM //////////////////////////////////////////////////////////////

 for(i = 0; i < 1024; ++i) 
  {
   * set1 = 0x00000000;			// clear set 1 word 
   ++set1; 				// increment set 1 pointer 
  }

// 
 err = 0;

// check set 1 is cleared //////////////////////////////////////////////////////				 

 set1 = (unsigned int *)Set1CacheRAM;	// restore set 1 pointer 

 for(i = 0; i < 1024; ++i) 		// check set 1 items (4Kb = 1K words)
  {
   if(*set1 != 0x00000000) 
    {
// item is nozero ////////////////////////////////////////////////////////////// 

     err = 1;
     Print("\nClear Cache SET1 ERROR. SET1[0x%x] = 0x%x",set1, *set1);
    }

   set1++; 				// increment set1 pointer 
  }
    
 if(err) 
  {
   rvl = 0;
   Print("\nFail. SET1 Cache Memory Not Cleared.");
  }
 else 
  {
   Print("\nSET1 Cache Memory Cleared.");
  }

//
 err = 0;
 tagram = (unsigned int *) TagRAM;
 for(i=0; i < 256; i++) 
  {
   *tagram = 0x00000000;   // Clear tag ram 
    tagram += 1; 
  }

// 
 tagram = (unsigned int *) TagRAM;
 for(i = 0; i < 256; ++i) 
  {
   if(*tagram != 0x00000000)
    {
     err = 1;
     Print("Clear Cache Tag Ram Error. [0x%x] = 0x%x.\n",tagram, *tagram);
    }
   tagram += 1; 
  }


 if(err) 
  {
   rvl = 0;
   Print("\nFail. Tag Ram Not Cleared.");
  }
 else 
  {
   Print("\nTag Ram Cleared.");
  }

//
 SYSCFG = syscfg;			// restore syscfg
 return(rvl);
}

////////////////////////////////////////////////////////////////////////////////
// test internal SRAM in 4K mode ///////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////


int SramMarch10_4k(void)
{
 unsigned int * sram;			// internal SRAM pointer 
 U32 syscfg;				// saved syscfg
 int err = 0;  				// sram flag for march error

//
 Print("\n\nSRAM(4K bytes) test by 10N march algorithm.");

//
 syscfg = SYSCFG;			// save SYSCFG
 CacheClear();    			// Clear the cache memory

// get pointer to internal SRAM from SYSCFG ////////////////////////////////////
 sram = (unsigned int *) 
  (
    ((SYSCFG >> 6) & 0x3FF) << 16	// 6 - Internal SRAM base pointer offset
  );					// field length - 10 bit

//[0]	Stall Enable (SE)
//[1]	Cache Enable (CE)
//[2] 	Write Buffer Enable (WE)
//[3]	0
//[5:4] Cache Mode (CM)
// 	00 = 4Kb SRAM, 4Kb Cache 
//	01 = 0Kb SRAM, 8Kb Cache 
//	10 = 8Kb SRAM, 0Kb Cache
//NOTE: When you write 10 to this field, the cache enable bit is cleared
// 	automatically
//[15:6]Internal SRAM base pointer     


// Set internal SRAM 4Kb mode //////////////////////////////////////////////////

 SYSCFG = 
  (
    SYSCFG & 				// 
   ~SYSCFG_CACHE_MASK			// 
  )
  | SYSCFG_CACHE_MODE_4KB_CACHE;
 PrintCacheConfig(); 			// print cache mode 

// SRAM(1024 words) test by 10N march //////////////////////////////////////////

 Print("\n");
 if(March10N32(sram,1024,0x00000000,256) == 0) { err = 1; } // 00000000
 if(March10N32(sram,1024,0x0000ffff,256) == 0) { err = 1; } // 0000FFFF
 if(March10N32(sram,1024,0x00ff00ff,256) == 0) { err = 1; } // 00FF00FF
 if(March10N32(sram,1024,0x0f0f0f0f,256) == 0) { err = 1; } // 0F0F0F0F	
 if(March10N32(sram,1024,0x33333333,256) == 0) { err = 1; } // 33333333 
 if(March10N32(sram,1024,0x55555555,256) == 0) { err = 1; } // 55555555

// 
 SYSCFG = syscfg; 

//
 if(err) 
  {
   Print("\nFail.\n");
   return(0);
  }
 else 
  {
   Print("\nOk.\n");
   return(1);
  }
}


////////////////////////////////////////////////////////////////////////////////
// test internal SRAM in 8Kb mode //////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////