init_gnu.s

本source code 為s3c4510的bootloader

#endif 						/* LED_ONLY */ 
#endif 						/* ROM_AT_ADDRESS_ZERO */ 
	
/* Init ZI area */
    	MOV     r2, #0
    	LDR     r1, =_sbss
    	LDR     r3, =_ebss
#ifdef ROM_AT_ADDRESS_ZERO
#ifdef LED_ONLY
#else 
        ORR     r1, r1, #0x1000000
        ORR     r3, r3, #0x1000000
#endif 						/* LED_ONLY */
#endif						/* ROM_AT_ADDRESS_ZERO */
ZI_clear:  	CMP     r1, r3               
    	STRLO   r2, [r1], #4
    	BLO     ZI_clear

/************************************************************************/
/*---+------------+							*/
/*   |            |							*/
/*   |            |        +------------+ Image$$ZI$$Limit (_ebss)	*/
/*   |            |        |            |                 		*/
/*   |            |        | ZI Output  | ZI execution  		*/
/* R |            |        |    section |    region  			*/
/* A |            |        |            |                 		*/
/* M |            |        |            | Image$$ZI$$Base  (_sbss)	*/
/*   |            |        +------------+	    is equal     	*/
/*   |            |        |            | Iage$$RW$$Limit  (_edata)	*/
/*   |            |        |            |                 		*/
/*   |            |        | RW Output  | RW execution 			*/
/*   |            |        |    section |    region 			*/
/*   |            |        |            |                 		*/
/*---+------------+--------+------------+ Image$$RW$$Base  (_sdata)	*/
/*   | RW Output  |        |            |				*/
/* R |    section | single |            |  				*/
/* O +------------+ load   +------------+ Image$$RO$$Limit (_etext)    	*/
/*   |            | region |            |                 		*/
/* M | RO Output  |        | RO Output  | RO execution  		*/
/*   |    section |        |    section |    region   			*/
/*---+------------+--------+------------+ 		   (_stext)	*/	
/*    LOAD VIEW            EXECUTION VIEW				*/
/************************************************************************/

#ifdef ROM_AT_ADDRESS_ZERO
#ifdef LED_ONLY
/* Monitor, DRAM remain start from 0x01000000 (16M-32M)*/
#else 
/* ROM startup test, remap DRAM to 0x00000000, ROM to 0x02000000 */
   	LDR     r0, =SystemWorkDataSDRAM
	LDMIA   r0, {r1-r12}
	LDR	r0, =0x3FF0000 + 0x3010 	/* EXTDBWTH Offset : 0x3010 */
	STMIA   r0, {r1-r12}
#endif 						/* LED_ONLY */
#endif						/* ROM_AT_ADDRESS_ZERO */


/* Call C_Entry application routine with a pointer to the first */
/* available memory address after ther compiler's global data   */
/* This memory may be used by the application.                  */
	/*===========================*/
	/* Now we enter the C Program*/
	/*===========================*/

/* UART0 Baud Rate Register */   
	LDR	r1, =UARTBRD0			/* I/O port data register */
        LDR     r2, =0x00280       		/* 38400 */
/* 0x00a20 //   9600 // cnt0 = 162 cnt1 = 0, 0 */
/* 0x00500 //  19200 // cnt0 =  80 cnt1 = 0, 1 */
/* 0x00280 //  38400 // cnt0 =  40 cnt1 = 0, 2 */
/* 0x001a0 //  57600 // cnt0 =  26 cnt1 = 0, 3 */
/* 0x000d0 // 115200 // cnt0 =  13 cnt1 = 0, 4 */
/* 0x00060 // 230400 // cnt0 =   6 cnt1 = 0, 5 */
/* 0x00020 // 460800 // cnt0 =   2 cnt1 = 0, 6 not available*/
        STR     r2, [r1]

	LDR	r0, =0x3FF0000	   		/* SYSCFG register address */
	LDR 	r1,[r0]		   		/* Read SYSCFG register value */
	LDR	r2, =0x0C000000	   		/* lo bits of PID(product id) */
/* [30:26] */
/* 00000 = KS32C5000 */
/* 00001 = KS32C50100 s3c4510x */
/* 11001 = s3c4510B */
/* 00011 = s3c4530X */
/* 10011 = s3c4530A */
	AND	r0, r1, r2         		
	CMP	r0, r2
	BEQ 	UART0_S3C4530_CONF

UART0_S3C4510_CONF:
/* UART0 Line Control Register */
	LDR	r1, =UARTLCON0			/* I/O port data register */
        LDR     r2, =0x03        		/* ULCON_WL8 0x03, word lengt 8 bit */
        STR     r2, [r1]
/* UART0 Control register */    
	LDR	r1, =UARTCONT0			/* I/O port data register */
        LDR     r2, =0x09        		/* Tx mode int, Rx mode int */
        STR     r2, [r1]
	B 	P16_start

UART0_S3C4530_CONF:
	LDR	r1, =UCON0			/* I/O port data register */
        LDR     r2, =0x00003005       		/* word len 8 bit, tx mode int, rx mode int */
        STR     r2, [r1]

P16_start:

/* write 0/1 to port P16 */

////////////////////////////////////////////////////////////////////////////////
        LDR     r3, =0x4	

P16_write:
	LDR	r0, =0x00000			/* write 0 to port P16 */
	LDR	r1, =IOPDATA			/* I/O port data register */
	MOV	r2, #0x040000			/* loop counter */

P16_write_0:
	STR	r0, [r1]			/* 1 cycle, write to I/O port data register */
	SUBS	r2, r2, #1			/* 1 cycle, Down Count */
	BNE 	P16_write_0			/* 3 cycles */

	LDR	r0, =0x10000			/* write 1 to port P16 */
	MOV	r2, #0x040000			/* loop counter */

P16_write_1:

	STR	r0, [r1]			/* write to I/O port data register */
	SUBS	r2, r2, #1			/* Down Count */
	BNE 	P16_write_1	

        SUBS    r3, r3, #1
        BNE     P16_write

/************************************************************************/
/* Initialise STACK 							*/
/************************************************************************/

INITIALIZE_STACK:
	MRS	r0, cpsr			/* r0 = cpsr */
	BIC	r0, r0, #LOCK_MASK | MODE_MASK	/* clear I,F, mode bits */
	ORR	r2, r0, #USR_MODE		/* r2 : I = 0, F = 0, M[4:0] = USER_MODE  */

/* operand2 = <#expression>, assembler will attept to generate a */
/* shifted immediate 8-bit field to match the expression. If this */
/* is imposible, it will give an error. */

	LDR 	r4, =_end 

/* Undefined instruction cpsr, spsr, sp */
	ORR	r1, r0, #LOCK_MASK | UDF_MODE	/* I=1,F=1,M=UDF_MODE */
	MSR	cpsr, r1			/* cpsr = r1 */
	MSR	spsr, r2			/* spsr (saved CPSR = USER mode, enable FIQ, IRQ) */
	add     r4, r4, #UDF_STACK_SIZE
#ifndef LED_ONLY
	str 	r4, UDF_STACK
#endif 						/* LED_ONLY */
	mov	sp, r4				/* undefined mode stack */

/* Abort mode cpsr, spsr, sp*/
	ORR	r1, r0, #LOCK_MASK | ABT_MODE	/* I=1,F=1,M=ABT=MODE */
	MSR	cpsr, r1			/* cpsr (enter ABORT mode, disable FIQ, IRQ) */
	MSR	spsr, r2			/* spsr (saved CPSR = USER mode, enable FIQ, IRQ) */
	add     r4, r4, #ABT_STACK_SIZE
#ifndef LED_ONLY
	str 	r4, ABT_STACK
#endif 								/* LED_ONLY */
	mov	sp, r4				/* Abort Mode stack (defined in STACK area) */


/* Supervisor mode cpsr, spsr, sp */
	ORR	r1, r0, #LOCK_MASK | SUP_MODE	/* I=1, F=1,M=SUP_MODE */
	MSR	cpsr, r1			/* cpsr */
	MSR	spsr, r2			/* spsr */
	add     r4, r4, #SUP_STACK_SIZE
#ifndef LED_ONLY
	str 	r4, SUP_STACK
#endif 								/* LED_ONLY */
	mov	sp, r4   			/* Change CPSR to SVC mode */

/* IRQ cpsr, spsr, sp */
	ORR	r1, r0, #LOCK_MASK | IRQ_MODE	/* I=1,F=1,M=IRQ_MODE */
	MSR	cpsr, r1			/* cpsr (enter IRQ mode, disable FIQ, IRQ) */
	MSR	spsr, r2			/* spsr (saved CPSR = USER mode, enable FIQ,IRQ) */ 
	add     r4, r4, #IRQ_STACK_SIZE
#ifndef LED_ONLY
	str 	r4, IRQ_STACK
#endif 								/* LED_ONLY */
	mov	sp, r4				/* IRQ stack (defined below in STACK area) */

/* FIQ cpsr, spsr, sp */
	ORR	r1, r0, #LOCK_MASK | FIQ_MODE	/* I=1,F=1,M=FIQ_MODE */
	MSR	cpsr, r1			/* cpsr = r1 (change mode=FIQ, disable FIQ,IRQ) */
	MSR	spsr, r2			/* spsr = r2 (I=0,F=0,M=USER_MODE)   */
	add     r4, r4, #FIQ_STACK_SIZE
#ifndef LED_ONLY
	str 	r4, FIQ_STACK
#endif 								/* LED_ONLY */
	mov	sp, r4				/* FIQ stack (defined below in STACK area) */

/* setup USR stack */
	MSR	cpsr, r2
	add     r4, r4, #USR_STACK_SIZE
#ifndef LED_ONLY
	str 	r4, USR_STACK
#endif 								/* LED_ONLY */
	mov	sp, r4

/* now in user mode */
        BL      C_Entry		

#ifdef ROM_AT_ADDRESS_ZERO
/*======================================================*/
/* DRAM System Initialize Data(KS32C5000 and KS32C50100)*/ 
/*======================================================*/
SystemInitData:
#ifdef EDO_DRAM_CONFIG 
	.word rEXTDBWTH		/* */
	.word initROMCON0	/* */
	.word initROMCON1	/* */ 
    	.word initROMCON2	/* */
	.word initROMCON3	/* */
	.word initROMCON4	/* */
	.word initROMCON5	/* */ 
	.word initDRAMCON0   	/* */
	.word initDRAMCON1	/* */
	.word initDRAMCON2	/* */
	.word initDRAMCON3	/* */
	.word rREFEXTCON  	/* */
#endif 						/* EDO_DRAM_CONFIG */
/*====================================================*/
/*DRAM System Initialize Data	(KS32C50100 only)     */
/*====================================================*/
SystemInitDataSDRAM:
	.word rEXTDBWTH		/* */
	.word initROMCON0	/* */
	.word initROMCON1	/* */
    	.word initROMCON2	/* */
	.word initROMCON3	/* */
	.word initROMCON4	/* */
	.word initROMCON5	/* */
	.word initSDRAMCON0  	/* */
	.word initSDRAMCON1	/* */
	.word initSDRAMCON2	/* */
	.word initSDRAMCON3	/* */
	.word rSREFEXTCON 	/* */

#ifdef LED_ONLY
/* Monitor used only SystemInitDataSDRAM memory map */
#else 
SystemWorkDataSDRAM:
	.word rEXTDBWTH		/* */
	.word workROMCON0	/* */
	.word workROMCON1	/* */
    	.word workROMCON2	/* */
	.word workROMCON3	/* */
	.word workROMCON4	/* */
	.word workROMCON5	/* */
	.word workSDRAMCON0  	/* */
	.word workSDRAMCON1	/* */
	.word workSDRAMCON2	/* */
	.word workSDRAMCON3	/* */
	.word rSREFEXTCON 	/* */
#endif						/* LED_ONLY */
#endif 						/* ROM_AT_ADDRESS_ZERO */ 

#ifdef LED_ONLY
#else 
.globl StartDownPgm
StartDownPgm:
	MOV	PC, r0

.globl UDF_STACK
UDF_STACK: 
    .word 0x0badc0de

.globl ABT_STACK 
ABT_STACK:
    .word 0x0badc0de

.globl SUP_STACK
SUP_STACK: 
    .word 0x0badc0de

.globl IRQ_STACK
IRQ_STACK: 
    .word 0x0badc0de

.globl FIQ_STACK
FIQ_STACK: 
    .word 0x0badc0de

.globl USR_STACK
USR_STACK: 
    .word 0x0badc0de
#endif						/* LED_ONLY */