init_gnu.s

本source code 為s3c4510的bootloader

#else 
        SUB     r0,lr,#4		/* r0 = address of abborted data instruction */
	BL	ISR_AbortHandler	/* undefined handler */
/* ISR_AbortHandler defined in isr.c as: */
/* void ISR_AbortHandler(void *adr) */
#endif 
	LDMFD	sp!, {r0-r12, lr}
	SUBS	pc, lr, #8

/************************************************************************/
/* undefined Handler 							*/
/************************************************************************/
Undefined_Handler:
/************************************************************************/
/*Action on Entering an Exeption. Then handling an exeption, 		*/
/*the ARM7TDMI:								*/
/*1. Preserves the address of the next instruction in the 		*/
/*appropriate Link register. In ARM state address of next instruction	*/
/*(PC+4 or PC=8) is copied into the link register.			*/
/*2. Copies the CPSR in the appropriate SPSR				*/
/*3. Forces the CPSR mode bits to value which depends on exeption	*/
/*4. Forces the PC to fetch the next instruction from the relevant 	*/
/* exeption vector 							*/
/************************************************************************/
/* 1. Then the Undefined Instruction occurs, the following 		*/
/* actions are performed: 						*/
/* 									*/
/* R14_und = address of next instruction after the  			*/
/* undefined instruction 						*/ 
/* SPSR_und = CPSR 							*/
/* CPSR[4:0] = 0b11011 	// enter Undefined mode 			*/
/* CPSR[5] = 0		// execute ARM state 				*/
/* CPSR[6] is unchanged 						*/
/* CPSR[7] = 1								*/
/* PC = 0x00000004   							*/
/* 									*/
/* To return after emulating the undefined instruction use: 		*/
/* MOVS PC,R14 								*/
/* 									*/
/* This restores the PC (from R14_und) and CPSR (from SPSR_und) and	*/
/* return to the instruction following the undefined instruction. 	*/
/* 									*/
/* 2. MOVS Description  						*/
/* Then Rd (destination register) is R15 and S flag is set the 		*/
/* result of the operation is placed in R15 and the SPSR corresponding  */
/* to the current mode is moved to CPSR. This allows state changes which*/
/* atomaticaly restore both PC and CPSR 				*/
/* 									*/ 
/* 3. C code for ISR_UndefHandler :  					*/
/* 									*/
/* void ISR_UndefHandler(void *adr) 					*/
/* {									*/
/*  Print("\rUndefined Address : %08x ",adr); 				*/
/*  Print("\rUndefined Data : %08x ",*adr); 				*/
/* } 									*/
/* 									*/
/* ASM code for ISR_UndefHandler: 					*/
/* STMFD    r13!,{r4,r14} 						*/
/* MOV      r4,r0 							*/
/* MOV      r1,r4 							*/
/* ADD      r0,pc,#0x14 ; #0x58 					*/
/* BL       Print 							*/
/* LDR      r0,[r4,#0] 							*/
/* MOV      r1,r0 							*/
/* ADD      r0,pc,#0x20 ; #0x74 					*/
/* BL       Print 							*/
/* LDMFD    r13!,{r4,pc}  						*/
/* 									*/
/* r0  = undefined (not address of undefined instruction),  		*/
/* r14 = address of next instruction after undefined 			*/
/* LDMFD    r13!,{r4,pc} return control to next instructon after 	*/
/* udefined witout mode change (mode remain undefined mode). 		*/
/************************************************************************/

	STMFD	sp!, {r0-r12,lr}	/* save [r0-r12,r14] */
/* Out to UART0 character */
	LDR	r1, =UARTTXH0		 
	LDR	r0, =0x55		/* 0x54 = 'U' */
	STR	r0, [r1]

        SUB     r0,lr,#4		/* r0 = address undefined instruction */
#ifdef LED_ONLY
#else 
	BL	ISR_UndefHandler	/* conditional branch */
#endif 
	LDMFD	sp!, {r0-r12, pc}^	/* restore r0-r12, CPSR, PC = next instruction */

SWI_Handler:
/************************************************************************/
/* Software Interrupt exception 					*/
/* The software Interrupt instruction (SWI) enters Supervisor mode to 	*/
/* request a particular supervisor (operating system) function. When 	*/
/* a SWI is executed, the following actions are performed:		*/
/*									*/
/* R14_svc = address of next instruction after the SWI instruction	*/
/* SPSR_svc = CPSR							*/
/* CPSR[4:0] = 0b10011		// Enter Supervisor mode 		*/
/* CPSR[5] = 0 		// Execute in ARM state 			*/
/* CPSR[6] = unchanged							*/
/* CPSR[7] = 1			// Disable normal interrupt		*/
/* PC = 0x00000008							*/
/************************************************************************/
	STMFD	sp!, {r0-r12,lr}
/* out to UART0 character S */
	LDR	r1, =UARTTXH0	
	LDR	r0, =0x53		/* 0x53 = 'S' */
	STR	r0, [r1]	

	LDR	r0, [lr, #-4]
	BIC	r0, r0, #0xff000000
	CMP	r0, #0xff
	BEQ	MakeSVC
#ifdef  LED_ONLY
#else 
        BL      ISR_SwiHandler
#endif 
/* Note : r0 contain comment field (24 bits in ARM mode), so SWI handler */
/* may be defined as : void ISR_SwiHandler(int cmd) */
	LDMFD	sp!, {r0-r12, pc}^
MakeSVC:
	MRS	r1, spsr
	BIC	r1, r1, #MODE_MASK
	ORR	r2, r1, #SUP_MODE
	MSR	spsr, r2	
	LDMFD	sp!, {r0-r12, pc}^

/*======================================================================*/
/* The Reset Entry Point				    		*/
/*======================================================================*/
.globl	Reset_Handler
Reset_Handler:                   	/* Reset Entry Point */
/************************************************************************/
/* Assembly control directives - IF, ELSE, and ENDIF			*/
/* Syntax								*/
/* IF logical-expression						*/
/* ...									*/
/* {ELSE								*/
/* ...}									*/
/* ENDIF								*/
/* Symbol [ is a synonym for IF.					*/
/* Symbol | is a synonym for ELSE					*/
/************************************************************************/
#ifdef ROM_AT_ADDRESS_ZERO
#else 
	swi 0xff 				/* Call SWI Vector  */
#endif 						/* ROM_AT_ADDRESS_ZERO */

/*=====================================*/ 
/* LED (back pannel) Display, LED D1 = P16 */ 
/*=====================================*/

INITIALIZE_LED:

/* Configure port P16 as output */

	LDR	r1, =IOPMOD			/* I/O port mode register  */
	LDR	r0, =0x10000			/* [16] I/O port mode bit for port 16,0=input,1=output */
	STR	r0, [r1]			/* write to I/0 port mode register */

/* write 0/1 to port P16 */

	LDR	r1, =IOPDATA			/* I/O port data register */
	LDR	r0, =0x00000			/* write 0 to port P16 */
	STR	r0, [r1]			/* write to I/O port data register */

/*=====================================*/
/* Setup Special Register */
/*=====================================*/

#ifdef EDO_DRAM_CONFIG  
	LDR	r0, =0x3FF0000	   		/* Read SYSCFG register value */
	LDR 	r1,[r0]		   		/* To idetify DRAM type */
	LDR	r2, =0x80000000	   
	AND	r0, r1, r2         		/* Mask DRAM type mode bit */
	CMP	r0, r2
	BNE 	EDO_DRAM_CONFIGURATION
#endif 						/* EDO_DRAM_CONFIG */
	B 	SYNC_DRAM_CONFIGURATION 	

/*==================================================*/
/* Special Register Configuration for EDO mode DRAM */
/* When KS32C5000 and KS32C50100                    */
/*==================================================*/ 
#ifdef EDO_DRAM_CONFIG
EDO_DRAM_CONFIGURATION:
	LDR	r0, =0x3FF0000		 
	LDR	r1, =0x3FFFF90   	/* SetValue = 0x3FFFF91 */
	STR	r1, [r0]	  	/* Cache,WB disable */
                           	        /* Start_addr = 0x3FF00000 */
/* ROM and RAM Configuration(Multiple Load and Store) */
        LDR     r0, =SystemInitData
	LDMIA   r0, {r1-r12}
	LDR	r0, =0x3FF0000 + 0x3010 /* ROMCntr Offset : 0x3010 */
	STMIA   r0, {r1-r12}

	LDR 	r1,=DRAM_BASE
	STR 	r1,[r1] 		/* [DRAM_BASE] = DRAM_BASE */
	LDR 	r2,[r1]			/* Read DRAM Data */
	CMP 	r2,r1
	BEQ 	INITIALIZE_C
#endif 						/* EDO_DRAM_CONFIG */
/************************************************************************/
/* Special Register Configuration for SYNC DRAM				*/
/* Only when KS32C50100							*/
/************************************************************************/

/************************************************************************/
/* System Configuration Register (SYSCFG)   				*/
/* Reset Value = 0x7FFFF91 						*/
/*									*/
/* [0]		Stall enable (SE). Must be set to zero  		*/
/* [1] 	Cache enable. 1 - cache operations are enabled  		*/
/* [2] 	Write buffer enable (WE). Then set to 1, write buffer 		*/
/* 		operatin operations are enabled			 	*/
/* [3] 	0								*/
/* [5:4]	Cacahe mode (CM)					*/
/*		00 = 4-Kbyte SRAM, 4-Kbyte cache			*/
/*		01 = 0-Kbyte SRAM, 8-Kbyte cache			*/
/*		10 = 8-kbyte SRAM, 0-Kbyte cache			*/
/*		Note: 	When you write 10 to this field, the cache 	*/
/*			enable bit is cleared automatically		*/
/* [15-6]	Internal SRAM base pointer				*/
/* [25-16	Special register bank base pointer 			*/
/* [29-26]	Product Identifier (PD_ID) 				*/
/* 		0000=KS32C5000						*/
/* 		0001=KS32C50100						*/
/* [31]	Sync DRAM Mode							*/
/* 		0 = Normal/EDO Dram interface for 4 DRAM banks		*/
/* 		1 = Sync. DRAM interface for 4 DRAM banks		*/
/************************************************************************/

/* Reset value (0x7FFFF91) 						*/
/* 									*/
/* ...0....7....F....F....F....F....9....1 				*/
/* 0000.0111.1111.1111.1111.1111.1001.0001 				*/
/* 1098.7654.3210.9876.5432.1098.7654.3210 				*/
/* .3...........2............1...........0 				*/
/* [0]     Stall enable (SE) = 1  					*/		
/* [1]     Cache enable = 0 						*/
/* [2]     Write buffer enable = 0					*/
/* [5:4]   Cache mode = 01 (no SRAM, 8-Kbyte Cache)			*/
/* [15:6]  Internal SRAM base pointer = 1111.1111.10 = 0x3FE(0x3FE0000)	*/
/* [25:16] Spesial register bank pointer=11.1111.1111= 0x3FF(0x3FF0000)	*/
/* [29:26] Product Identifier = 00.01 = KS32C50100 			*/
/* 									*/
/* Configurated value (0x83FFFFA0) 					*/
/* 									*/
/* ...8....3....F....F....F....F....A....0 				*/
/* 1000.0011.1111.1111.1111.1111.1010.0000 				*/
/* 1098.7654.3210.9876.5432.1098.7654.3210 				*/
/* .3...........2............1...........0 				*/
/* [0]     Stall enable (SE) = 0  					*/
/* [1]     Cache enable = 0  						*/
/* [2]     Write buffer enable = 0 					*/
/* [5:4]   Cache mode = 10 (10 = 8-Kbyte SRAM) 				*/
/* [15:6]  Internal SRAM base pointer = 1111.1111.10=0x3FE(0x3FE 0000)	*/
/* [25:16] Spesial register bank pointer=11.1111.1111=0x3FF(0x3FF 0000) */
/* [29:26] Product identifier (PD_ID) = KS32C5000 			*/
/* [31]    Sync DRAM interface for 4 DRAM banks 			*/

SYNC_DRAM_CONFIGURATION:
#ifdef ROM_AT_ADDRESS_ZERO
/* ROM and RAM Configuration(Multiple Load and Store) */

/* ROM sturtup tests & monitor */
   	LDR     r0, =SystemInitDataSDRAM
	LDMIA   r0, {r1-r12}
	LDR	r0, =0x3FF0000 + 0x3010 /* EXTDBWTH Offset : 0x3010 */
	STMIA   r0, {r1-r12}
#endif 						/* ROM_AT_ADDRESS_ZERO */

	LDR	r0, =0x3FF0000		 
	LDR	r1, =0x83FFFFA0   	/* SetValue = 0x83FFFFA1 */
	STR	r1, [r0]	  	/* Cache,WB disable */
                           		/* Start_addr = 0x3FF00000 */
INITIALIZE_C:
#ifdef ROM_AT_ADDRESS_ZERO
/* ROM_AT_ADDRESS_ZERO defined in ROM startup tests and in Monitor */
#ifdef LED_ONLY
/* Monitor */
/* RO area - ROM bank 0; RW, ZI in internal SDRAM */
/* => copy RW area to internal SDRAM */
    	LDR     r0, =_etext
    	LDR     r1, =_sdata
        LDR     r3, =_edata
RW_copy:
        CMP     r1, r3 			/* while(r1 < r3) */
    	LDRLO   r2, [r0], #4	     	/* [r0 += 4] */
    	STRLO   r2, [r1], #4	     	/* [r1 += 4] */
    	BLO     RW_copy
#else 
/* ROM Startup, copy  RO/RW areas to external DRAM */
        MOV     r0, #0 
        MOV     r1, #0x1000000
    	LDR     r3, =_sbss
RO_RW_copy:   	
        CMP     r0, r3          	/* while(r0 < r3) */
    	LDRLO   r2, [r0], #4	  	/* [r0 += 4] */
    	STRLO   r2, [r1], #4	 	/* [r1 += 4] */
    	BLO     RO_RW_copy