init_gnu.s

本source code 為s3c4510的bootloader

/*************************************************************************/
/*                                                                       */
/* FILE NAME                                            VERSION          */
/*                                                                       */
/*      init.s                              SNDS100 Board version 1.0    */
/*                                                                       */
/* COMPONENT                                                             */
/*                                                                       */
/*                                                                       */
/* DESCRIPTION                                                           */
/*                                                                       */
/*      This file contains the target processor dependent initialization */
/*      routines (boot code) and data.                                   */
/*                                                                       */
/* AUTHOR                                                                */
/*                                                                       */
/*                                                                       */
/* DATA STRUCTURES                                                       */
/*                                                                       */
/*                                                                       */
/* FUNCTIONS                                                             */
/*                                                                       */
/*                                                                       */
/* DEPENDENCIES                                                          */
/*                                                                       */
/*      snds.a                              System constants             */
/*                                                                       */
/* HISTORY                                                               */
/*                                                                       */
/*         NAME            DATE                    REMARKS               */
/*                                                                       */
/*        hbahn         01-25-1998      Created initial version 1.0      */
/*                                                                       */
/*************************************************************************/

/* 			*/
/* Modified by 		*/
/* Dmitriy Cherkashin 	*/
/* [e-mail]	*/
/* 2002,2003,2004	*/
/*			*/

#include "init_gnu.h"

.globl __main
__main:
/* --- Setup interrupt / exception vectors */
#ifdef ROM_AT_ADDRESS_ZERO
/* If the ROM is at address 0 this is just a sequence of branches */
        B       Reset_Handler			/* Reset (mode = Supervisor) */
        B       Undefined_Handler		/* Udefined instruction (mode = Undefined) */
        B       SWI_Handler			/* Software interrupt (mode = Supervisor) */
        B       Prefetch_Handler		/* Abort prefetch (mode = Abort) */
        B       Abort_Handler			/* Abort data (mode = Abort) */
        NOP     				/* Reserved vector (mode = Reserved) */
/* NOP = Pseudo Instruction, translated MOV r0,r0  */
        B       IRQ_Handler			/* IRQ (mode = IRQ) */
        B       FIQ_Handler			/* FIQ (mode = FIQ) */

/************************************************************************/
/* Action on Entering an Exception					*/
/* When handling an exception, the ARM7TDMI:				*/
/* 1. Preserves the address of the next instruction in the 		*/
/* appropriate Link Register. If the exception has been entered from 	*/
/* ARM state, then the address of the next instruction is copied into 	*/
/* the Link Register (that is, current PC + 4 or PC + 8 depending on 	*/
/* the exception. If the exception has been entered from THUMB state,	*/
/* then the value written into the Link Register is the current PC 	*/
/* offset by a value such that the program resumes from the correct 	*/
/* place on return from the exception.					*/	
/* 2. Copies the CPSR into the appropriate SPSR				*/
/* 3. Forces the CPSR mode bits to a value which depends on the 	*/
/*    exception								*/
/* 4. Forces the PC to fetch the next instruction from the relevant 	*/
/*    exception vector							*/
/************************************************************************/

#else 
/* Otherwise we copy a sequence of LDR PC instructions over the vectors */
/* (Note: We copy LDR PC instructions because branch instructions */
/* could not simply be copied, the offset in the branch instruction */
/* would have to be modified so that it branched into ROM. Also, a */
/* branch instructions might not reach if the ROM is at an address */
/* > 32M). */
        MOV     R8, #0
        ADR     R9, Vector_Init_Block
        LDMIA   R9!, {R0-R7}
        STMIA   R8!, {R0-R7}
        LDMIA   R9!, {R0-R7}
        STMIA   R8!, {R0-R7}

/* Now fall into the LDR PC, Reset_Addr instruction which will continue */
/* execution at 'Reset_Handler' */

Vector_Init_Block:
        LDR     PC, Reset_Addr
        LDR     PC, Undefined_Addr
        LDR     PC, SWI_Addr
        LDR     PC, Prefetch_Addr
        LDR     PC, Abort_Addr
        NOP
        LDR     PC, IRQ_Addr
        LDR     PC, FIQ_Addr

Reset_Addr:     .word Reset_Handler
Undefined_Addr: .word Undefined_Handler
SWI_Addr:       .word SWI_Handler
Prefetch_Addr:  .word Prefetch_Handler
Abort_Addr:     .word Abort_Handler
                .word 0       	/* Reserved vector */
IRQ_Addr:       .word IRQ_Handler
FIQ_Addr:       .word FIQ_Handler
#endif 						/* ROM_AT_ADDRESS_ZERO */

/*==========================================================*/
/* The Default Exception Handler Vector Entry Pointer Setup */
/*==========================================================*/

/* Exeption Priorities */
/* 1. Reset (Highest priority) */
/* 2. Data Abort */
/* 3. FIQ */
/* 4. IRQ */
/* 5. Prefetch Abort */
/* 6. Undefined Instruction. Software interrupt (Lowest priority) */

/************************************************************************/
/* FIQ Handler 								*/
/************************************************************************/

FIQ_Handler:
/************************************************************************/
/* The FIQ exeption is generated externally by asserting the FIQ	*/
/* input on the processor. FIQ is designated to support a data 		*/
/* transfer  channel process, and has sufficient private registers 	*/
/* to remove the need for registe saving in sutch applications,		*/
/* therefore minimizing the overhead of context switching.		*/
/*									*/
/* Fast interrupts are disabled when the F bit in the CPSR is set. 	*/
/* If the F bit is clear, ARM checks for an FIQ an instruction		*/
/* boundaries.								*/
/*									*/
/* Then an FIQ is detected, the following actions are performed:	*/
/*									*/
/* F14_fiq = address of next instruction to be executed + 4		*/
/* SPSR_fiq = CPSR							*/
/* CPSR[4:0] = 0b10001		// Enetr FIQ mode			*/
/* CPSR[5] = 0 		// Execute in ARM state				*/
/* CPSR[6] = 1			// Disable fast interrupts 		*/
/* CPSR[7] = 1			// Disable normal interrupts		*/
/* PC = 0x0000001C 							*/
/*									*/
/* To return after servicing the interrupt, use:			*/
/*									*/
/* SUBS PC,R14,#4							*/
/*									*/
/* This restores both the PC (from R14_fiq) and CPSR (from SPSR_fiq), 	*/
/* and resumes execution of the interrupted code.			*/
/*									*/	
/* The FIQ vector is deliberately the last vector to allow the FIQ 	*/
/* exeption-handler software to be placed directly at address 		*/
/* 0x0000001C, without requiring a branch instruction from the vector.  */	
/************************************************************************/
	STMFD	sp!, {r0-r7, lr}
/* out to UART0 character F */
/*	LDR	r1, =UARTTXH0 */
/*	LDR	r0, =0x46 */	/* 0x46 = 'F' */
/*	STR	r0, [r1] */
#ifdef LED_ONLY
#else 	
	BL	ISR_FiqHandler
#endif 								/* LED_ONLY */	
	LDMFD	sp!, {r0-r7, lr}
	SUBS	pc, lr, #4

/************************************************************************/
/* LRM, STM suffixes :							*/
/* IA - Increment after  = EA - Empty ascending stack			*/
/* IB - Increment before = FA - Full ascending stack			*/
/* DA - Decrement after  = ED - Empty descending stack			*/
/* DB - Decrement before = FD - Full descending stack			*/
/* Full stack  - the stack pointer point to the last item in the stack	*/
/* Empty stack - the stack pointer point to the next item in the stack	*/
/* ARM The ARM-Thumb Procedure Call Standard (ATPCS),and ARM and Thumb  */ 
/* C and C++ compilers always use a full descending stack.		*/
/************************************************************************/


/************************************************************************/
/* IRQ Handler 								*/  
/************************************************************************/
IRQ_Handler:
/************************************************************************/
/* The IRQ exeption is generated externally by asserting the IRQ	*/
/* input on the processor. It has a lower priority than FIQ, and	*/
/* is masked out when an FIQ sequence is entered.			*/
/*									*/
/* Interrupts are disabled when the I bit in CPSR is set. If the I 	*/
/* bit is clear, ARM checks for an IRQ at insruction boundaries.	*/
/* The I bit can only be changed from a privileged mode.		*/
/*									*/
/* Then an IRQ is detected, the following actions are performed:	*/
/*									*/
/* R14_irq = adress of next instruction to be executed + 4		*/
/* SPSR_irq = CPSR							*/
/* CPSR[4:0] = 0b10010		// Enter IRQ mode			*/	
/* CPSR[5] = 0			// Execute in ARM state			*/
/* CPSR[6] = unchanged		// FIQ mask bit (1 - disable)		*/
/* CPSR[7] = 1			// Disable normal interrupts		*/
/* PC = 0x00000018							*/
/*									*/
/* To return after servicing the interrupt, use:			*/
/*									*/
/* SUBS PC,R14,#4							*/
/*									*/
/* This restore both PC (from R14_irq) and CPSR (from SPSR_irq),	*/
/* and resumes execution of the interrupted code.			*/
/************************************************************************/
	STMFD	sp!, {r0-r12, lr}

/* out to UART0 character I */
/*	LDR	r1, =UARTTXH0   */		
/*	LDR	r0, =0x49	*/	 /* 0x49 = 'I' */
/*	STR	r0, [r1]	*/	

#ifdef LED_ONLY
#else 	
	BL	ISR_IrqHandler
#endif 							/* LED_ONLY */
	LDMFD	sp!, {r0-r12, lr}
	SUBS	pc, lr, #4

/************************************************************************/
/* Prefetch Handler 							*/
/************************************************************************/
Prefetch_Handler:
/************************************************************************/
/* Prefetch Abort (instruction fetch memory abort)			*/
/* F14_abt = address of the aborted instruction + 4			*/
/* SPSR_abt = CPSR							*/	
/* CPSR[4:0] = 0b10111		// enter Abort mode 			*/
/* CPSR[5] = 0			// Execute in ARM state			*/
/* CPSR[6] = unchanged		// FIQ mask bit				*/
/* CPSR[7] = 1			// Disable normal interrupts		*/
/* PC = 0x0000000C							*/
/*									*/
/* To return after fixing the reason for the abort, use:		*/
/*									*/
/* SUBS PC,R14,#4							*/
/*									*/
/* This restores both PC (from R14_abt) and CPSR (from SPSR_abt),	*/
/* and return to the aborted instruction. 				*/
/************************************************************************/
	STMFD	sp!, {r0-r12, lr}

/* out to UART0 character P*/
	LDR	r1, =UARTTXH0
	LDR	r0, =0x50		/* 0x50 = 'P' */
	STR	r0, [r1]
#ifdef LED_ONLY
#else	
        SUB     r0,lr,#4		/* r0 = address of abborted instruction */
	BL	ISR_PrefetchHandler	/* Branch and link System Prefetch Abort Handler */
/* ISR_PrefetchHandler defined in isr.c as: */
/* void ISR_PrefetchHandler(void *adr), where */
/*      adr = address of abborted instruction */
#endif 							/* LED_ONLY */
	LDMFD	sp!, {r0-r12, lr}
	SUBS	pc, lr, #4

/************************************************************************/
/* Abort Handler 							*/
/************************************************************************/
Abort_Handler:
/************************************************************************/
/* A Data Abort exception occures before any following instructions or	*/
/* exeptions have altered the state of the CPU.				*/
/*									*/
/* F14_abt = address of the aborted instruction + 8			*/
/* SPSR_abt = CPSR							*/
/* CPSR[4:0] = 0b10111			// Enter Abort mode		*/
/* CPSR[5] = 0				// Execite in ARM state		*/
/* CPSR[6] = unchanged							*/
/* CPSR[7] = 1				// Disable normal interrupts	*/
/* PC = 0x00000010							*/
/*									*/
/* To return after fixing the reason for the abort use:			*/
/* 									*/
/*  SUBS PC,R14,#8							*/
/*  									*/
/* This restores both the PC (from R14_abt) and CPSR (from SPSR_abt),	*/	
/* and returns to re-execute the aborted instruction.			*/
/************************************************************************/
	STMFD	sp!, {r0-r12, lr}
/* out to UART0 character 'D'  */
	LDR	r1, =UARTTXH0		
	LDR	r0, =0x44		/* 0x44 = 'D' */ 
	STR	r0, [r1]		

#ifdef LED_ONLY