📄 main.c
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case 1 :// 4Kb Cache mode (4Kb SRAM) /////////////////////////////////////////////////// Print("\n4K Cache ON"); // 4Kb Cache CacheInit(CACHEINIT_4K); // set cache mode break; case 2 :// 8Kb Cache mode (0Kb SRAM) /////////////////////////////////////////////////// Print("\n8K Cache ON"); CacheInit(CACHEINIT_8K); break; } { int lsize = 1; // memory test loop size int rvl = 1;// MEMORY Test ////////////////////////////////////////////////////////////////// Print("\n%d. Memory Test .... ", testnum++); if(msize <= 0) { // internal error rvl = 0; } else { Print("\n Source addr=0x%08x. Dest addr=0x%08x. Words=%d", msrc, mdst, mtsize); Print("\n To skip test press ESC"); rvl = MemTest(msrc,mdst,mtsize,lsize, 0x10000/4); } if(rvl == 0) { err = 1; ALLERR[cm].mem = 1; Print("\nFail."); } else if(rvl == -1) { ALLERR[cm].mem = -1; Print("\nSkipped."); } else { Print("\nOk."); } }// UART Test Print("\n%d. UART Test .... ", testnum++); if(UARTAutoLoopBack(-1) == 0) { err = 1; ALLERR[cm].uart = 1; Print("\nFail."); } else { Print("\nOk."); } Print("\n%d. GDMA Channel 0/1 Test .... ", testnum++); GdmaReset(0); GdmaReset(1); GdmaIntEnable(0); GdmaIntEnable(1); Print("\n Source addr=0x%08x. Dest addr=0x%08x. Words=%d", msrc, mdst, mtsize); if(DmaAutoTest((U32)msrc,(U32)mdst,mtsize,1) == 0) { err = 1; ALLERR[cm].dma = 1; Print("\nFail."); } else { Print("\nOk."); } GdmaIntDisable(0); GdmaIntDisable(1);////////////////////////////////////////////////////////////////////////////////// MAC Test //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// MacInitialize(); if(PhyNoColLoopBack(1) == 0) { err = 1; ALLERR[cm].mac = 1; Print("\nFail."); } else { Print("\nOk."); }////////////////////////////////////////////////////////////////////////////////// HDLC Test /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// HDLC_Init(); Print("\n%d. HDLC Test .... ", testnum++); if( HdlcInternalLoopback(0,1000,1) == 0 || // HdlcInternalLoopback(1,1000,1) == 0 // ) { err = 1; ALLERR[cm].hdlc = 1; Print("\nFail."); } else { Print("\nOk."); }// IIC Test Print("\n%d. IIC Test .... ", testnum++); if(IICWriteReadTest(1) == 0) { err = 1; ALLERR[cm].iic = 1; Print("\nFail."); } else { Print("\nOk."); }// {// 3 seconds time delay //////////////////////////////////////////////////////// U32 start; // start time seconds U32 sec; // current time sec TIME tm; // TIME struct TimerReset(1); // reset timer 1 TimerInit(1,(ONE_SECOND/TICKS_PER_SECOND));// init timer 1 TimerStart(1); // start timer 1 GetSysTime(1,&tm); // get time start = tm.tm_sec + tm.tm_min * 60; // start time while(1) { GetSysTime(1,&tm); // read time from timer 1 sec = tm.tm_sec + tm.tm_min * 60; // time in seconds if(sec > start + 3) { // break; } } // TimerStop(1); // stop timer 1 } }// Print("\n\nAll Test Finished"); CacheInit(CACHEINIT_OFF); Print("\nAll Test Error Report");// #define ALLERRFMT "\n%-20s%12s%12s%12s" // format #define ALLERR_OK "Ok " // Ok message#define ALLERR_FAIL "Fail " // Fail message #define ALLERR_SKIPPED "Skipped " // // Print(ALLERRFMT, "", "Cache OFF", "4K Cache ON", "8K Cache ON" ); Print ( ALLERRFMT, "Internal SRAM", ALLERR[0].sram == 0 ? ALLERR_OK : ALLERR_FAIL, ALLERR[1].sram == 0 ? ALLERR_OK : ALLERR_FAIL, ALLERR[2].sram == 0 ? ALLERR_OK : ALLERR_FAIL ); { char * m0; char * m1; char * m2; switch(ALLERR[0].mem) { case 0 : m0 = ALLERR_OK; break; case 1 : m0 = ALLERR_FAIL; break; case -1 : m0 = ALLERR_SKIPPED; break; default : m0 = ""; break; } switch(ALLERR[1].mem) { case 0 : m1 = ALLERR_OK; break; case 1 : m1 = ALLERR_FAIL; break; case -1 : m1 = ALLERR_SKIPPED; break; default : m1 = ""; break; } switch(ALLERR[2].mem) { case 0 : m2 = ALLERR_OK; break; case 1 : m2 = ALLERR_FAIL; break; case -1 : m2 = ALLERR_SKIPPED; break; default : m2 = ""; break; } Print(ALLERRFMT, "Memory Test", m0 , m1 , m2 ); } Print(ALLERRFMT, "UART Test", ALLERR[0].uart == 0 ? ALLERR_OK : ALLERR_FAIL, ALLERR[1].uart == 0 ? ALLERR_OK : ALLERR_FAIL, ALLERR[2].uart == 0 ? ALLERR_OK : ALLERR_FAIL ); Print(ALLERRFMT, "TIMER Test", ALLERR[0].timer== 0 ? ALLERR_OK : ALLERR_FAIL, ALLERR[1].timer== 0 ? ALLERR_OK : ALLERR_FAIL, ALLERR[2].timer== 0 ? ALLERR_OK : ALLERR_FAIL ); Print(ALLERRFMT, "DMA Test", ALLERR[0].dma == 0 ? ALLERR_OK : ALLERR_FAIL, ALLERR[1].dma == 0 ? ALLERR_OK : ALLERR_FAIL, ALLERR[2].dma == 0 ? ALLERR_OK : ALLERR_FAIL ); Print(ALLERRFMT, "IIC Test", ALLERR[0].iic == 0 ? ALLERR_OK : ALLERR_FAIL, ALLERR[1].iic == 0 ? ALLERR_OK : ALLERR_FAIL, ALLERR[2].iic == 0 ? ALLERR_OK : ALLERR_FAIL ); Print(ALLERRFMT, "MAC Test", ALLERR[0].mac == 0 ? ALLERR_OK : ALLERR_FAIL, ALLERR[1].mac == 0 ? ALLERR_OK : ALLERR_FAIL, ALLERR[2].mac == 0 ? ALLERR_OK : ALLERR_FAIL ); Print(ALLERRFMT, "HDLC Test", ALLERR[0].hdlc == 0 ? ALLERR_OK : ALLERR_FAIL, ALLERR[1].hdlc == 0 ? ALLERR_OK : ALLERR_FAIL, ALLERR[2].hdlc == 0 ? ALLERR_OK : ALLERR_FAIL ); TimerStop(0);// GetSysTime(0, & tm); /* get time from Timer 0 */ Print ( "\ntime = %d:%d:%d.%d" , tm.tm_hour , /* hour */ tm.tm_min , /* minute */ tm.tm_sec , /* second */ tm.tm_ms /* millisecond */ ); if(err != 0 ) { Print("\nFail"); } else { Print("\nOk"); }}////////////////////////////////////////////////////////////////////////////////// main menu ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////void Main(void){// InitEvb();// while(1) { char it; // selected item Print("\n\n") ;#ifdef _S3C4530_ Print("\nS3C4530 TEST");#else Print("\nKS32C50100 TEST");#endif Print("\n[V] View Configuration [C] Cache/SRAM Test"); Print("\n[M] Memory Test [T] Timer Test"); Print("\n[U] UART Test [I] Interrupt Test"); Print("\n[L] MAC/Ethernet Test [H] HDLC Test"); Print("\n[D] GDMA Test [S] I2C Test"); Print("\n[G] I/O Port Functions [A] All Test"); Print("\n[P] Program Download");// Select test item //////////////////////////////////////////////////////////// Print("\nSelect Test Item: "); it = get_upper(); // read character from console switch(it) { case 'V' : ViewSysConfig();break; // Show System Config case 'C' : CacheTest(); break; // cache test dialog case 'M' : MemoryTest(); break; // memory test dialog case 'T' : TimerTest(); break; // Timer 0/1, WatchDog test case 'U' : UartTest(); break; // UART 0/1 test case 'I' : IntTest(); break; // interrupt test case 'L' : MacTest(); break; // Ethernet test case 'H' : HdlcTest(); break; // HDLC test dialog case 'D' : GdmaTest(); break; // GDMA test dialog case 'S' : IICTest(); break; // IIC test dialog case 'G' : IopTest(); break; // I/O Port test case 'A' : AllTests(); break; // All tests case 'P' : ZmTest(); break; // ZModem menu default : Print("\nNo Test Item Selected"); break ; } Print("\nPress Any Key to Continue"); get_byte(); }}////////////////////////////////////////////////////////////////////////////////// Initialize for Command Line Interface ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////void InitEvb(void) {// SYSCFG PD_ID field syscfg_pd_id = (SYSCFG & SYSCFG_PD_ID);// InitInterrupt(); // Init interrupts UART_Initialize(); // Initialize UART channel 0,1 IICSetup(); // MacInitialize(); // init MAC HDLC_Init(); // SysSetInterrupt(nGDMA0_INT, GDMA0isr); // SysSetInterrupt(nGDMA1_INT, GDMA1isr); // CacheInit(CACHEINIT_OFF); // Enable_Int(nGLOBAL_INT); //}
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