main.c

本source code 為s3c4510的bootloader

#include "ks32c50.h"
#include "evm50100.h"
#include "mac.h"

/* 			*/
/* Modified by 		*/
/* Dmitriy Cherkashin 	*/
/* [e-mail]	*/
/* 2002, 2003		*/
/*			*/

extern U32 AllTestResult ;		

U32 syscfg_pd_id;			// SYSCFG PD_ID field

// C Program Entry Point
void C_Entry(void)
{
// UART0 Line Control Register ////////////////////////////////////////////////// 
 
 UARTLCON0 = 				// UART0 Line Control register 
  UARTLCON_WL8    |			// Word Length 8 bit 
  UARTLCON_PMD_NO;   			// No parity

// UART0 Control register /////////////////////////////////////////////////////// 

 UARTCONT0 =  				// UART0 Control Register
  UARTCON_RXM_INTREQ |			// rx mode = interrupt request
  UARTCON_TXM_INTREQ;      		// tx mode = interrupt request

// UART0 BaudRate Register ////////////////////////////////////////////////////// 

 UARTBRD0  = 
//  0x00a20; 	//  9600		// cnt0 = 162 cnt1 = 0, 0
//  0x00500; 	// 19200		// cnt0 =  80 cnt1 = 0, 1
    0x00280; 	// 38400		// cnt0 =  40 cnt1 = 0, 2
//  0x001a0; 	// 57600		// cnt0 =  26 cnt1 = 0, 3
//  0x000d0; 	// 115200		// cnt0 =  13 cnt1 = 0, 4
//  0x00060; 	// 230400		// cnt0 =   6 cnt1 = 0, 5
//  0x00020; 	// 460800   		// cnt0 =   2 cnt1 = 0, 6 not available 
 Main();
}

////////////////////////////////////////////////////////////////////////////////
// View System Configuration ///////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////


void ViewSysConfig(void)
{
 U8 * RO_BaseAddr = (U8 *) Image_RO_Base;	// Image Read Only Base
 U8 * RO_EndAddr  = (U8 *) Image_RO_Limit;	// Image Read Only Limit
 int  RO_Size = RO_EndAddr - RO_BaseAddr;	// Image Read Only Size
// 
 U8 * RW_BaseAddr = (U8 *) Image_RW_Base;	// Image Read/Write Base
 U8 * RW_EndAddr  = (U8 *) Image_RW_Limit;	// Image Read/Write Limit
 int  RW_Size = RW_EndAddr - RW_BaseAddr;	// Image Read/Write Size
// 
 U8 * ZI_BaseAddr = (U8 *) Image_ZI_Base;	// Image Zero Init Base
 U8 * ZI_EndAddr  = (U8 *) Image_ZI_Limit;	// Image Zero Init Limit
 int  ZI_Size = ZI_EndAddr - ZI_BaseAddr;	// Image Zero Init Size

 Print("\nSystem Configuration");

// Data Bus width for ROM bank 0 ///////////////////////////////////////////////

 Print("\nROM/Flash Bank 0 Data Bus Size is.");
 switch(EXTDBWTH & EXTDBWTH_DSR0)
  {
   case 1 : Print("BYTE");  break;	// ROM/Flash Bank 0 bus size = byte
   case 2 : Print("SHORT"); break;	// ROM/Flash Bank 0 bus size = half word
   case 3 : Print("WORD");  break;	// ROM/Flash Bank 0 bus size = word	
  }

// Stall Enable bit ////////////////////////////////////////////////////////////

 Print("\nSystem Manager Status") ;
 Print("\n  Stall Enabled (SE)..............");

 if((SYSCFG & SYSCFG_STALL) != 0)
  {
   Print("1(enabled)");
  } 
 else
  {
   Print("0(disabled)");
  } 


// Cacahe enable ///////////////////////////////////////////////////////////////

 Print("\n  Cache Enabled (CE)..............");
 if((SYSCFG & SYSCFG_CACHE) != 0)
  {
   Print("1(enabled)");
  } 
 else
  {
   Print("0(disabled)");
  } 


// Cache size //////////////////////////////////////////////////////////////////

 Print("\n  Cache Mode (CM).................");
 switch(SYSCFG & SYSCFG_CACHE_MODE)
  {
   case SYSCFG_CACHE_MODE_4KB_CACHE :
    Print("00 (4K SRAM, 4K CACHE)");
    break;

   case SYSCFG_CACHE_MODE_8KB_CACHE :
    Print("01 (0K SRAM, 8K CACHE)");
    break;

   case SYSCFG_CACHE_MODE_8KB_SRAM  :  
    Print("10 (8K SRAM, 0K CACHE)");
    break;

   default 			    :		
    Print("11 (unused)"); 
    break;
  }

/* Write buffer enable */

 Print("\n  Write Buffer Enabled (WE).......");
 if((SYSCFG & SYSCFG_WRITE_BUFF) != 0)
  {
   Print("1 (enabled)");
  }
 else
  {
   Print("0 (disabled)");
  } 

//
 Print("\n  Internal SRAM Base Address......0x%08x",((SYSCFG & 0xFFC0) << 10) );
 Print("\n  Special Register Bank Base Ptr..0x%08x",( SYSCFG & 0x3FF0000) );

 Print("\n  Product Identifier..............0x%x",   (SYSCFG >> 26) & 0x7);
 Print("\n  Sync. DRAM Mode.................%d"  ,   (SYSCFG >> 31));

//////////////////////////////////////////////////////////////////////////////// 
// content of CLCCON /////////////////////////////////////////////////////////// 
//////////////////////////////////////////////////////////////////////////////// 


 Print("\nClock control register CLKCON.....0x%08x", CLKCON);
 Print("\n  Clock Divided Value.............0x%08x",(CLKCON & CLKCON_DIV_MASK));

//
 Print("\n  ROM bank 5 wait.................");
 if((CLKCON & CLKCON_ROM5_WAIT_EN) != 0)
  {
   Print("1 (enable)");			// enable additional wait state
  }
 else
  {
   Print("0 (disable)");
  }

//////////////////////////////////////////////////////////////////////////////// 
//  
//////////////////////////////////////////////////////////////////////////////// 
//////////////////////////////////////////////////////////////////////////////// 

 Print("\n  ROM bank 5 address/data bus Mux.");
 if((CLKCON & CLKCON_ROM5_MUX_EN) != 0)
  {
   Print("1 (enable)");
  }
 else
  {
   Print("0 (disable)");
  }


 Print("\n  Mux bus Address Cycle (tAC).....");
 switch(CLKCON & CLKCON_ROM5_MUX_TAC) 
  {
   case CLKCON_ROM5_MUX_TAC_1   : Print("(00) 1 MCLK"); break;
   case CLKCON_ROM5_MUX_TAC_2   : Print("(01) 2 MCLK"); break;
   case CLKCON_ROM5_MUX_TAC_3   : Print("(02) 3 MCLK"); break;
   case CLKCON_ROM5_MUX_TAC_UN  : Print("(unused)");    break; 
   default 			: break;
  }


// 
 Print("\n  Test bit is set.................");
 if((CLKCON & CLKCON_TEST_BIT) != 0)
  {
   Print("1");
  }
 else
  {
   Print("0");
  }


/* Image ReadOnly Base, Limit, Size */ 
/* Print("\nRead Only Memory Used"); */
 Print("\n  Read Only Base..................0x%08x"   , RO_BaseAddr);
 Print("\n  Read Only End...................0x%08x"   , RO_EndAddr );
 Print("\n  Read Only Size..................0x%08x %d", RO_Size, RO_Size);

/* Image ReadWriet Base, Limit, Size */
/* Print("\nRead/Write Memory Used"); */
 Print("\n  Read/Write Base.................0x%08x"   , RW_BaseAddr);
 Print("\n  Read/Write End..................0x%08x"   , RW_EndAddr );
 Print("\n  Read/Write Size.................0x%08x %d", RW_Size, RW_Size);

/* Image ZI Base, Limit, Size */
/* Print("\nRead/Write Memory Used") ; */
 Print("\n  ZI Base.........................0x%08x"   , ZI_BaseAddr);
 Print("\n  ZI End..........................0x%08x"   , ZI_EndAddr );
 Print("\n  ZI Size.........................0x%08x %d", ZI_Size, ZI_Size);
}


////////////////////////////////////////////////////////////////////////////////
// Type definition for Error Report ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

struct ALLERRRPT 
{
 int sram;				// 0 internal SRAM test 
 int mem;				// 1 memory test 
 int uart;				// 2 UART test 
 int timer;				// 3 timer test 
 int dma;				// 4 DMA test 
 int iic;				// 5 IIC test 
 int mac;				// 6 MAC test 	
 int hdlc;				// 7 HDLC test 
} 
 ALLERR[4];


////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////


void AllTests(void)
{
 U32 rbase [12];			// free mem region base 
 U32 rlimit[12];			// free mem region limit 
 int rcnt; 				// count of regions 
 U32 mbase;				// max free mem region base address
 int msize;				// max free mem region size 
 U32 * msrc;  			 	// memory test source address
 U32 * mdst;   				// memory test destination address
 U32 mtsize;  				// memory test size

 int testnum = 0;			// test number 
 int err = 0;				// error flag 
 TIME tm;				// time struct
 int  cm;				// cache mode

//
 rcnt = 12;
 if(FreeDramRegions(rbase,rlimit,&rcnt) == 0)
  {
   rcnt = 0;
  }

 msize = 0;				// max free mem region size 
 for(cm = 0; cm < rcnt; ++cm)
  {
   int size; 
   size = rlimit[cm] - rbase[cm];
   if(size > msize)
    {
     msize = size;
     mbase = rbase[cm];
    }
  } 

 Print("\nMax free DRAM region address=0x%08x size=%d", mbase, msize);


 if(msize > 0)
  {
// allign mem test region to 64K
   U32 base; 
   if(mbase == 0)
    {
     mbase  = 0x10000;
     msize -= 0x10000;
    }   

   base = ((mbase + 0xFFFF) >> 16) << 16;
   msize -= (base - mbase);		// reset size 
   mbase  = base;			// reset base 
   msrc = (U32 *) mbase;   		// memory source address
   mtsize = msize / 8;  		// memory Test size (words)
   mdst = msrc + mtsize;   		// memory destination address
  }


// TIMER 0 Initialized for mesuring the test time //////////////////////////////

 TimerReset(0);					// reset timer 0
 TimerInit (0,(ONE_SECOND/TICKS_PER_SECOND));	// init timer  0
 TimerStart(0);					// start timer 0

 for(cm = 0; cm < 4; ++cm)
  { 
// Clear Error Report //////////////////////////////////////////////////////////
   ALLERR[cm].sram  = 0;		// clear SRAM  test error flag 
   ALLERR[cm].mem   = 0; 		// clear MEM   test error flag 
   ALLERR[cm].uart  = 0;		// clear UART  test error flag 
   ALLERR[cm].timer = 0; 		// clear TIMER test error flag 	
   ALLERR[cm].dma   = 0;		// clear DMA   test error flag 
   ALLERR[cm].iic   = 0; 		// clear IIC   test error flag 
   ALLERR[cm].mac   = 0;		// clear MAC   test error flag 
   ALLERR[cm].hdlc  = 0; 		// clear HDLC  test error flag 
  }

////////////////////////////////////////////////////////////////////////////////
// Cache/Internal SRAM test ////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

 CacheInit(CACHEINIT_OFF);
 Print("\nCache OFF");
 Print("\n%d.Cache tag Set0 Set1 10N March Test .... ", testnum++);

// 
 Print("\n8K Cache ON");
 CacheInit(CACHEINIT_8K);
 if(	
   TagMarch10()  == 0 ||  		// test tag ram (256 words)
   Set0March10() == 0 ||     		// test cache set 0 in SRAM disable mode
   Set1March10() == 0        		// test cache set 1 in SRAM disable mode
  )
  {
   err = 1;
   ALLERR[0].sram = 1;
  }

// 4Kb Cache mode (4Kb SRAM) /////////////////////////////////////////////////// 
 Print("\n%d.Internal SRAM (4Kb mode) 10N March Test .... ", testnum++);
 Print("\n4K Cache ON");		// 4Kb Cache 
 CacheInit(CACHEINIT_4K);		// set cache mode 
 if(SramMarch10_4k() == 0)		// test SRAM in 4k mode
  {
   err = 1;
   ALLERR[1].sram = 1;
  }

// 8Kb SRAM mode /////////////////////////////////////////////////////////////// 
 Print("\n%d.Internal SRAM (8Kb mode) 10N March Test .... ", testnum++);
 Print("\nCache OFF");			// Cache Off
 CacheInit(CACHEINIT_OFF);		// Set cache Mode
 if(SramMarch10_8k() == 0)		// test SRAM in 8k mode	
  {
   err = 1;
   ALLERR[2].sram = 1;
  }

 for(cm = 0; cm < 3; ++cm) 
  {
   switch(cm)
    {
     case 0 :
// disable CACHE // (8Kb SRAM mode) //////////////////////////////////////////// 
      Print("\nCache OFF");		// Cache Off
      CacheInit(CACHEINIT_OFF);		// Set cache Mode
      break;