macinit.c

本source code 為s3c4510的bootloader

// 
 Disable_Int(nGLOBAL_INT);		// disable global int

// 
 cnt = gRxFDCnt;			// Rx BD count 
 frame = (sFrameDes *) gRRxFDPtr;	// current readed frame 
 for(fn = 0; fn < cnt; fn++)  
  {
   if(frame == 0)
    {					// null list	
     return(0);				// 
    } 

   if((frame->DataPtr & fOwnership_BDMA))
    {					// allready set BDMA owner bit 
     break;				// => break
    } 

   frame->DataPtr |= fOwnership_BDMA;	// set DMA owner bit 
   frame->Reserved = (U32)0x0;		// clear reserved field 
   frame->StatusLength = (U32)0x0;	// clear status & length 
   frame = (sFrameDes *)frame->NextDes;	// move to next descriptor 
  }

// 
 gRxFDCnt -= fn;			// 
 Enable_Int(nGLOBAL_INT);		// enable global int 
 return(1);
}


int MACRxBD_count(void)
{
 return(gRxFDCnt);
}

////////////////////////////////////////////////////////////////////////////////
// Interrupt Service Routine for BDMA Rx Ethenet Frame is received in //////////
// BDMA_Rx_isr /////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

void BDMA_Rx_isr(void)
{
 sFrameDes * frame;			// pointer to Rx descriptor 
 U32 status; 				// RX frame status
 U32 CRxPtr;				// current Rx DBMA pointer (content of BDMARXPTR)

// Check Null List Interrupt ///////////////////////////////////////////////////
 if(BDMASTAT & BDMASTAT_BRxNL) 
  {
   BDMASTAT |= BDMASTAT_BRxNL;		// Clear BDMA Rx NULL List Interrupt 
   gsBdmaRxStatus.BRxNLErr++; 		// calculate BDMA NUll List Interrupt count
   MacInitialize();			// Reinitialize MAC  
   return;
  }

// Step 1. Get current frame descriptor
 CRxPtr    = BDMARXPTR;			// current BDMA Rx descriptor pointer

// Step 2. Clear BDMA status register bit by write 1
 BDMASTAT |= BDMASTAT_BRxRDF;		// BDMA Rx Done Every Received Frame 	

 do 
  {
// Step 3. Get Rx Frame Descriptor /////////////////////////////////////////////
   frame = (sFrameDes *) gCRxFDPtr;	// RX Descriptor pointer 	
   if((frame->DataPtr & fOwnership_BDMA) != 0)
    {					// owner BDMA => break  
     break;
    } 
//
   gsBdmaRxStatus.BdmaRxCnt++;		// Total received packets
   status =(frame->StatusLength >> 16) & 0xFFFF;// RX status 

// Step 4. If Rx frame is good, then process received frame ////////////////////
   if(status & RXFDST_RxGood) 
    {
     gsBdmaRxStatus.BdmaRxGood++;	// total received good packets
    } 
   else 
    {
////////////////////////////////////////////////////////////////////////////////
// Step 5. If Rx frame has error, then process error frame /////////////////////
////////////////////////////////////////////////////////////////////////////////
     gRxErrorPacketCnt++ ;

// Save Error status
// Check each status, because, error can duplicated

     if(status & RXFDST_OvMax)    gsMacRxStatus.OvMaxSize++; // Over Maximum Size
     if(status & RXFDST_CtlRecd)  gsMacRxStatus.sCtlRecd++;  // set if packet received is a MAC control frame.
     if(status & RXFDST_Rx10Stat) gsMacRxStatus.sRx10Stat++; // set if packet was received via the 10bits interface
     if(status & RXFDST_AlignErr) gsMacRxStatus.AllgnErr++;  // Alignment Error 
     if(status & RXFDST_CRCErr)   gsMacRxStatus.sCRCErr++;   // CRC error
     if(status & RXFDST_Overflow) gsMacRxStatus.OverflowErr++;// MAC receive FIFO was full 
     if(status & RXFDST_LongErr)  gsMacRxStatus.sLongErr++;  // received a frame longer than 1518 bytes 
     if(status & RXFDST_RxPar)    gsMacRxStatus.RxParErr++;  // MAC receive FIFO has detected a parity error
     if(status & RXFDST_RxHalted) gsMacRxStatus.sRxHalted++; // Transmission was halted by clearing RxEn
    }

// Step 6. Get Next Frame Descriptor pointer to process
   gCRxFDPtr = (U32)(frame->NextDes);
   gRxFDCnt++;	
  } 
 while (CRxPtr != gCRxFDPtr);

// Step 7. Check NotOwner status ///////////////////////////////////////////////
 if(BDMASTAT & BDMASTAT_BRxNO) 
  {
   BDMASTAT |= BDMASTAT_BRxNO;		// BDMA Rx Not Owner
   gsBdmaRxStatus.BRxNOErr++;		// count of BDMA Rx Ont owner errors
  }
}

////////////////////////////////////////////////////////////////////////////////
// Descripton : Send ethernet frame function ///////////////////////////////////
// Input      : frame data pointer, frame length ///////////////////////////////
// Output     : transmit ok(1) or error(0) /////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////


int MACSend(U8 * data, int size)
{
 sFrameDes * frame;			// frame descriptor pointer 
 U32 * dst;
 U32 * src;
 int wlen;

// 1. Get Tx frame descriptor & data pointer ///////////////////////////////////
 frame = (sFrameDes *)gWTxFDPtr;	// pointer to frame
// 2. Check BDMA ownership /////////////////////////////////////////////////////
 if((frame->DataPtr & fOwnership_BDMA) ) 
  {					// descriptor is used by BDMA 
   return(0); 				// not enough frame descriptors
  }

// 3. Prepare Tx Frame data to Frame buffer ////////////////////////////////////

 size += sizeof(etheader);
 if(size > MaxRxFrameSize)
  {
   size = MaxRxFrameSize;
  } 
 wlen = (size + 3) >> 2;
 dst = (U32 *) frame->DataPtr;		// pointer to frame descriptor data
 src = (U32 *) data;		
 while(wlen-- > 0)
  {
   *dst++ = *src++; 
  } 


// 4. Set TX Frame flag & Length Field

#ifdef LITTLE
 frame->Reserved = 
  (
   TXFDCTRL_PaddingMode 	| 	// Padding mode 	
   TXFDCTRL_CRCMode 		| 	// CRC mode
   TXFDCTRL_SourceAddrIncrement | 	// Frame data pointer increment
   TXFDCTRL_LittleEndian 	| 	// Little-endian 
   TXFDCTRL_WidgetAlign00 	| 	// No Invalid bytes
   TXFDCTRL_MACTxIntEn		  	// transmit interrupt enable after transmission
  );
#else
 frame->Reserved = 
  (
   TXFDCTRL_PaddingMode 	| 	// Padding mode
   TXFDCTRL_CRCMode 		| 	// CRC Mode
   TXFDCTRL_SourceAddrIncrement | 	// Frame Data pointer Increment 
   TXFDCTRL_BigEndian 		| 	// Big Endian 
   TXFDCTRL_WidgetAlign00 	| 	// No invalid bytes
   TXFDCTRL_MACTxIntEn		  	// after frame fransfer interrupt 	
  );
#endif
 frame->StatusLength = size;

// 5. Cheange ownership to BDMA ////////////////////////////////////////////////

 frame->DataPtr |= fOwnership_BDMA;

// 6. Enable MAC and BDMA Tx control register //////////////////////////////////

 if((BDMATXCON & BDMATXCON_TxEn) == 0)  
  {
   BDMATXCON |= BDMATXCON_TxEn;
  }
 MACTXCON |= MACTXCON_TxEn;

// 7. Change the Tx frame descriptor for next use //////////////////////////////
 gWTxFDPtr = (U32)(frame->NextDes); 	// next descriptor to write 	

 if((INTMASK & GLOBAL_INT) != 0)
  {					// global interrupt disabed
   INTMASK &= ~GLOBAL_INT;		// enable global interrupt
  } 
 return(1);
}

////////////////////////////////////////////////////////////////////////////////
// Transfer Control Frame Data to another Host /////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

// To Send a Pause control packet, you write the CAM0 entry with the 
// destination address, the CAM1 entry with the source address,
// and CAM18 entry with length/type,opcode, and operand. You then 
// set the pause bit in the MAC transmit control register.   

void ControlFrameTransfer(void) 
{
 U8 it;

// 
 gBdmaTxCon |= BDMATXCON_TxCPIE;	// BDMA Tx Complete to send control 
 BDMATXCON   = gBdmaTxCon;		// set BDMA Transmit Register  
 MACTXCON    = gMacTxCon;		// set MAC Transmit Register 

 while(1) 
  {
   Print("\nSelect Transmit(T) or Quit(Q) ? ");
   it = get_upper();
   if(it == 'Q')
    {
     break;
    }
   else
   if(it != 'T')
    { 
     continue;
    } 

// Step 1. set destination address to CAM #0
// Step 2. set source address to CAM #1
// CAM #0 : 0000f0110000 (Destin Addr)
// CAM #1 : 11f000000000 (Source Addr)
   VPint(CAM_BaseAddr) = 0x0000f011 ;	
   VPint(CAM_BaseAddr + 0x4) = 0x000011f0;	
   VPint(CAM_BaseAddr + 0x8) = 0x00000000;	

// Step 3. set length or type field, opcode, and operand to CAM #18
// CAM #18 : Opcode & Operand
// CAM #18 : Pause Count Value
   VPint(CAM_BaseAddr + 0x6c) = 0x88080001;	

// Step 4. set to zero preceed CAM #18
// CAM #19 - #20 : Filled with Zero
   VPint(CAM_BaseAddr + 0x70) = 0x12340000;	
   VPint(CAM_BaseAddr + 0x74) = 0x00000000;	
   VPint(CAM_BaseAddr + 0x78) = 0x00000000;	
   VPint(CAM_BaseAddr + 0x7c) = 0x00000000;	

// Step 5. Enable CAM location
// CAM Enable
   CAMEN = 0x1c0003; 

// Step 6. Enable transmit control frame by 
//         set SendPause bit in MACTXCON
   MACTXCON |= MACTXCON_SdPause | MACTXCON_TxEn;

// Step 7. Wait control frame finished
   while((BDMASTAT & BDMASTAT_BTxCCP) == 0)
    {
/* [16] 	BDMA Tx complete to send control packet (BTxCCP) 	      */
/*              Bit [16] is set each time the MAC sends a complete control    */
/*              packet. 						      */
/* 									      */
/* 		0 = Normal operation. 					      */
/* 		1 = MAC send the control packet. 			      */
     ;
    }
  } 

 gBdmaTxCon &= ~BDMATXCON_TxCPIE;	// BDMA Tx Complete to send control 
}

////////////////////////////////////////////////////////////////////////////////
// View MAC status, and other //////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

void MacDebugStatus(void) 
{
 sFrameDes * pRxFDptr;
 sFrameDes * pTxFDptr;
 U32 * pFDPtr ;

 pRxFDptr =  (sFrameDes *) gCRxFDPtr;	// current Rx Frame descriptor pointer 
 pFDPtr = (U32 *)pRxFDptr;		

////////////////////////////////////////////////////////////////////////////////
// Print Receive Statistics ////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

 Print("\n\n\nMAC Rx Frame : Good ( %d ), Error ( %d ) ",
 
  gsBdmaRxStatus.BdmaRxGood	, 
  gRxErrorPacketCnt
 );

// pointer to current Rx frame descriptor ////////////////////////////////////// 
 Print("\n Current Frame Descriptor Pointer : %08x", pFDPtr ); 

// 
 Print("\nFrame Data Ptr          : %08x", *pFDPtr++); // pointer to data buffer 
 Print("\nReserved Field          : %08x", *pFDPtr++); // reserved field  
 Print("\nStatus and Frame Length : %08x", *pFDPtr++); // status and length field 
 Print("\n Next Frame Descriptor   : %08x", *pFDPtr  ); // pointer to next Rx frame descriptor 

// 
 Print("\nBDMARXPTR : %08x", BDMARXPTR); // Receive frame descriptor start address	
 Print("  BDMASTAT  : %08x", BDMASTAT ); // BDMA Status Register 
 Print("\nBDMARXCON : %08x", BDMARXCON); // BDMA Receive Control Register  
 Print("  BDMARXLSZ : %08x", BDMARXLSZ); // Receive frame maximum size
 Print("  BDMARXBUF : %08x", BDMARXBUF); // BDMA receive (Rx) buffer (64 words)
 Print("\nCAM Base  : %08x", CAM_BASE ); // CAM Base Address
 Print("  CAMCON    : %08x", CAMCON   ); // CAM Control Register 
 Print("\nMACCON    : %08x", MACCON   ); // MAC Control Register 
 Print("\nMACRXCON  : %08x", MACRXCON ); // MAC Receive Control Register 
 Print("  MACRXSTAT : %08x", MACRXSTAT); // MAC Receive Statistics

////////////////////////////////////////////////////////////////////////////////
// Print Transmit statistics ///////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

 pTxFDptr =  (sFrameDes *) gCTxFDPtr ;
 pFDPtr = (U32 *)pTxFDptr ;

 Print("\n\nMAC Tx Frame : Good ( %d )",gsMacTxStatus.MacTxGood);

// Current Transmit Frame Descriptor Pointer ///////////////////////////////////
 Print("\nCurrent Frame Descriptor Pointer : %08x", pFDPtr); 
// Fields of current transmit frame ////////////////////////////////////////////
 Print("\nFrame Data Ptr          : %08x", *pFDPtr++); // data buffer pointer 
 Print("\nReserved Field          : %08x", *pFDPtr++); // reserved field
 Print("\nStatus and Frame Length : %08x", *pFDPtr++); // status & length field 
 Print("\nNext Frame Descriptor   : %08x", *pFDPtr);   // next frame descriptor pointer 	

// 
 Print("\nBDMATXPTR : %08x", BDMATXPTR ); 
 Print("  BDMATXCON : %08x", BDMATXCON ); // BDMA Transmit Control Register 
 Print("\nBDMATXBUF : %08x", BDMATXBUF ); 
 Print("  MACTXCON  : %08x", MACTXCON  ); // MAC Transmit Control Register 	
 Print("\nMACTXSTAT : %08x", MACTXSTAT ); // MAC Transmit Status Register 
 Print("\nEMISSCNT  : %08x", EMISSCNT  ); 
 Print("  EPZCNT    : %08x\n\n", EPZCNT); 
}