macinit.c

本source code 為s3c4510的bootloader

/*************************************************************************/
/*                                                                       */
/* FILE NAME                                      VERSION                */
/*                                                                       */
/*      macinit.c                  KS32C5000, KS32C50100   : version 1.0 */
/*                                                                       */
/* COMPONENT                                                             */
/*                                                                       */
/* DESCRIPTION                                                           */
/*                                                                       */
/* AUTHOR                                                                */
/*                                                                       */
/*                                                                       */
/* DATA STRUCTURES                                                       */
/*                                                                       */
/*                                                                       */
/* FUNCTIONS                                                             */
/*                                                                       */
/*          Include All MAC & BDMAC Initialize Routine                   */
/*                                                                       */
/* DEPENDENCIES                                                          */
/*                                                                       */
/*                                                                       */
/* HISTORY                                                               */
/*                                                                       */
/*         NAME            DATE                    REMARKS               */
/*                                                                       */
/*      hbahn           09-15-1998      Created initial version 1.0      */
/*                                                                       */
/*************************************************************************/

/* 			*/
/* Modified by 		*/
/* Dmitriy Cherkashin 	*/
/* [e-mail]	*/
/* 2002			*/
/*			*/

//#include <string.h>
#include "ks32c50.h"
#include "evm50100.h"
#include "mac.h"

/* Define MAC address source, IIC EEPROM or set value by manual */

#define MAC_ADDR_FROM_IIC_EEPROM 0

////////////////////////////////////////////////////////////////////////////////
// Rx/Tx Frame descriptors, Rx/Tx data /////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

sFrameDes RxFrameDes[MAC_MAX_RX_DES];  	// Rx Frame Descriptor
sMACFrame RxFrameBuf[MAC_MAX_RX_DES];	// Rx Frame Buffer

sFrameDes TxFrameDes[MAC_MAX_TX_DES];   // Tx Frame Descriptor
sMACFrame TxFrameBuf[MAC_MAX_TX_DES];	// Tx Frame Buffer

////////////////////////////////////////////////////////////////////////////////
// Global variables  used for MAC driver ///////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

// MACCON (MAC Control Register) ///////////////////////////////////////////////  
volatile U32 gMacCon    = 

 MACCON_FullDup;	// full-duplex
// MACCON_HaltReg	// stop tx & rxx after completion of ant current packets 
// MACCON_HaltImm	// Stop tx & rx immediately 
// MACCON_SwReset 	// reset all Ethernet controller state machines and FIFOs 
// MACCON_MACLoop	// MAC loopback
// MACCON_ConnM00	// Automatic-default 
// MACCON_ConnM01	// Force 10Mbits endec
// MACCON_ConnM10	// Force MII 
// MACCON_MIIOFF	// Force MII 
// MACCON_Loop10	// Loop 10Mbps 
// MACCON_MissRoll	// Missed error counter rolled over 
// MACCON_MDCOFF	// MII Station Management Clock Off
// MACCON_EnMissRoll	// Interrupt when missed error counter rolls over 
// MACCON_Link10	// Link status 10Mbps 


// MACTXCON (Transmit Control Register) ////////////////////////////////////////
volatile U32 gMacTxCon  = 

 MACTXCON_EnComp;	// + interrupt when the MAC transmits or defer one packet
// TxEn			// - transmit Enable 
// TxHalt		// - Transmit Halt Request 
// NoPad		// - suppress Padding 
// NoCRC		// - Suppress CRC 
// FBack		// - Fast Back-off
// NoDef		// - Disable the defer counter
// SdPause		// - Send Pause
// MII10En		// - MII 10Mbps mode enable
// EnUnder		// - Enable Underrun
// EnDefer		// - Enable Deferral
// EnNCarr		// - Enable No Carrier 
// EnExColl		// - interrupt if 16 collision occur in the same packet 
// EnLateColl		// - interrupt if collision occurs after 512 bit times(64 bytes times) 
// EnTxPar		// - interrupt if the MAC transmit FIFO has a parity error 

// MACRXCON (Receive Control Register) /////////////////////////////////////////

volatile U32 gMacRxCon  = 
 MACRXCON_RxEn 	  | 	// + Receive enable (RxEn)
 MACRXCON_StripCRC; 	// + Strip CRC
// RxHalt		// - Receive halt request 
// LongEn		// - Long enable
// ShortEn		// - Short enable
// PassCtl		// - Pass control packet
// IgnoreCRC		// - Ignore CRC value
// EnAlign		// - Enable alignment interrupt 
// EnCRCErr		// - Enable CRC error interrupt 
// EnOver		// - Enable overflow interrupt 
// EnLongErr		// - Enable long error interrupt 
// EnRxPar		// - Enable receive parity
// EnGood		// - Enable Good

////////////////////////////////////////////////////////////////////////////////
// BDMATXCON // Buffered DMA Trasmit Control Register //////////////////////////
////////////////////////////////////////////////////////////////////////////////

volatile U32 gBdmaTxCon = 
 
 BDMATXCON_TxBRST   | 	// + BDMA Tx Burst Size Mask = 16 
 BDMATXCON_TxSTSKO  |	// + BDMA Tx Stop (1)/Skip (0) Frame or Interrupt in case
			//   of not Owner the current frame 
// BDMATXCON_TxCPIE	// - BDMA Tx Complete to send control packet interrupt Enable
// BDMATXCON_TxNLIE     // - BDMA Tx Null list interrupt enable
// BDMATXCON_TxNOIE	// - BDMA Tx Buffer Not Owner
// BDMATXCON_TxEmpty	// - BDMA Tx Buffer Empty Interrupt 
 BDMATXCON_TxMSL110; 	// + wait to fill 6/8 of the BDMA
// BDMATXCON_TxEn	// - BDMA Tx Enable 
// BDMATXCON_TxRS	// - BDMA Rx Reset 


#ifdef LITTLE

volatile U32 gBdmaRxCon = 

 BDMARXCON_RxBRST   |	// + BDMA Rx Burst Size
 BDMARXCON_RxDIE    | 	// + BDMA Rx Every Received Frame Interrupt Enable
 BDMARXCON_RxEn     | 	// + BDMA Rx Enable
 BDMARXCON_RxLittle | 	// + BDMA Rx Big/Little Endian 
 BDMARXCON_RxMAINC  | 	// + BDMA Rx Memory Address Inc/Dec 
 BDMARXCON_RxNLIE   | 	// + BDMA Rx NULL List Interrupt Enable 
 BDMARXCON_RxNOIE   | 	// + BDMA Rx Not Owner Interrupt Enable
 BDMARXCON_RxSTSKO;	// + BDMA Rx Stop/Skip  Frame or Interrupt(=1) 

// BDMARXCON_RxMSOIE	// - BDMA Rx Maximum Size over Interrupr Enable 
// BDMARXCON_RxBig 	// - BDMA Rx Big/Little Endian
// BDMARXCON_RxWA01	// - BDMA Rx Word Alignment- one invalid byte 
// BDMARXCON_RxWA10	// - BDMA Rx Word Alignment- two invalid byte
// BDMARXCON_RxWA11	// - BDMA Rx Word Alignment- three invalid byte 
// BDMARXCON_RxRS	// - BDMA Rx Reset
// BDMARXCON_RxEmpty	// - BDMA Rx Buffer empty interrupt 
// BDMARXCON_RxEarly	// - BDMA Rx Early notify Interrupt

#else
volatile U32 gBdmaRxCon = BRxDIE | BRxEn | BRxBig | BRxMAINC | BRxBRST | \
                          BRxNLIE | BRxNOIE | BRxSTSKO ;
#endif

///////////////////////////////////////////////////////////////////////////////
// CAMCON // CAM control register /////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////

volatile U32 gCamCon = 

 CAMCON_CompEn	| 	// + Compare Enable mode
 CAMCON_BroadAcc;	// + Accept any packet with a broadcast station station address  

// StationAcc		// - Accept any packet with a unicast station address 
// GroupAcc		// - Accept any packet with multicast-group  
// NegCAM		// - 


volatile U32 gCTxFDPtr;		/* Current Tx BDMA descriptor (moved by ISR)*/
volatile U32 gWTxFDPtr;		/* Write Tx Frame descriptor (moved by Send)*/
volatile U32 gCRxFDPtr;		/* Current Rx Frame descriptor (moved by ISR)*/
volatile U32 gRRxFDPtr;		/* Read Rx Frame descriptor (moved by Recv)*/
volatile U32 gRxFDCnt=0;	
volatile U32 gCam0_Addr0 = 0;	/* Content of CAM entry 0 */
volatile U32 gCam0_Addr1 = 0;	/* Content of CAM entry 1 */
volatile U32 gStaCon = 0;	/* MDC clock [15:13] STACON*/
volatile U8  MyMacSrcAddr[6];	/* MAC Stantion Adress */
volatile int gRxErrorPacketCnt=0;/* Total Received with error packets */


////////////////////////////////////////////////////////////////////////////////
// Global variable structure for store status //////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

// MAC Transmit status /////////////////////////////////////////////////////////

pMACTxStatus gsMacTxStatus = 
{
 0	,	// MacTxGood
 0	,	// ExCollErr	 (Transmit collission count) 
 0	,	// TxDefferedErr (Transmit deferred)
 0	,	// sPaused	 (Paused)
 0	,	// UnderErr	 (Underrun)
 0	,	// DeferErr	 (Deferral)
 0	,	// NCarrErr	 (No carrier)
 0	,	// sSQE		 (Signal quality error)
 0	,	// LateCollErr	 (Late collision)
 0	,	// TxParErr	 (Transmit parity error)
 0		// sTxHalted	 (Transmission halted)
};


// MAC Receive status //////////////////////////////////////////////////////////

pMACRxStatus gsMacRxStatus = 
{
 0	,	 // OvMaxSize
 0	,	 // sCtlRecd	 (Control frame received)
 0	,	 // sRx10Stat	 (Receive 10-Mb/s status)
 0	,	 // AllgnErr	 (Alignment error)
 0	,	 // sCRCErr	 (CRC error)
 0	,	 // OverflowErr	 (Overflow error)
 0	,	 // sLongErr	 (Long error)
 0	,	 // RxParErr	 (Receive parity error)
 0		 // sRxHalted	 (Reception halted)
};


// BDMA Transmit Status ////////////////////////////////////////////////////////


pBDMATxStatus gsBdmaTxStatus = 
{
 0	,	// BTxNLErr	(BDMA Tx null list)
 0	,	// BTxNOErr     (BDMA Tx not owner)
 0		// BTxEmptyErr	(BDMA Tx buffer empty)
};


// BDMA Receive Status /////////////////////////////////////////////////////////

pBDMARxStatus gsBdmaRxStatus = 
{
 0	,	// BdmaRxCnt
 0	,	// BdmaRxGood
 0	,	// BRxNLErr	(BDMA Rx null list)
 0	,	// BRxNOErr	(BDMA Rx not owner) 
 0		// BRxMSOErr	(BDMA Rx maximum size over)
};

// 
extern TIME tm0 ;

////////////////////////////////////////////////////////////////////////////////
// Initialize Tx frame descriptor area-buffers /////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

static void TxFDInitialize(void)
{
 sFrameDes * pFrame;			// current frame descriptor pointer 
 sFrameDes * pStart;			// start frame descriptor pointer 
 sFrameDes * pLast = NULL;		// last frame desriptor pointer 
 U32 DataAddr;				// data buffer pointer 
 U32 i;

// Get Frame descriptor's base address.   
// +0x4000000 is for setting this area to non-cacheable area. 

 BDMATXPTR = (U32)TxFrameDes+0x4000000;	// BDMA Transmit Pointer  
 gWTxFDPtr = gCTxFDPtr = BDMATXPTR;	// 

// Get Transmit buffer base address ////////////////////////////////////////////
 DataAddr = (U32)TxFrameBuf + 0x4000000;

// Generate linked list ////////////////////////////////////////////////////////
 pFrame = (sFrameDes *) gCTxFDPtr;	// current frame descriptor 
 pStart = pFrame;			// start frame descriptor 

 for(i=0; i < MAC_MAX_TX_DES; i++)  
  {
   if(pLast != NULL)
    {
     pLast->NextDes = (U32) pFrame;	//  
    }

// 
   pFrame->DataPtr      = (U32)(DataAddr & fOwnership_CPU); // data pointer	
   pFrame->Reserved     = (U32)0x0;	// reserved field 
   pFrame->StatusLength = (U32)0x0;	// status & length field
   pFrame->NextDes      = NULL;		// next descriptor pointer 
// 
   pLast = pFrame;			// reset last frame descriptor pointer 
   pFrame++;				// move to next descriptor pointer 
   DataAddr += sizeof(sMACFrame);	// pointer to next data buffer
  }

// Make Frame descriptor to ring buffer type ///////////////////////////////////     

 pFrame--; 
 pFrame->NextDes = (U32)pStart;
}

////////////////////////////////////////////////////////////////////////////////
// Initialize Rx frame descriptor area-buffers /////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

static void RxFDInitialize(void)
{
 sFrameDes * pFrame;			// current frame descriptor pointer 
 sFrameDes * pStart;			// pointer to start of list 
 sFrameDes * pLast = NULL;		// previous frame descriptor 
 U32 DataAddr;				// data buffer address
 U32 i;

// Get Frame descriptor's base address.  
// +0x4000000 is for setting this area to non-cacheable area. 
 BDMARXPTR = (U32)RxFrameDes + 0x4000000;// 
 gRRxFDPtr = gCRxFDPtr = BDMARXPTR;
 gRxFDCnt=0;	
	
// Get Transmit buffer base address.  
 DataAddr = (U32)RxFrameBuf + 0x4000000;

// Generate linked list. 
 pFrame = (sFrameDes *) gCRxFDPtr;
 pStart = pFrame;
	
 for(i=0; i < MAC_MAX_RX_DES; i++)  
  {
   if(pLast != NULL)
    {
     pLast->NextDes = (U32) pFrame;	// set NextDes field  
    }

// frame descriptor data pointer ///////////////////////////////////////////////
   pFrame->DataPtr =(U32)(DataAddr | fOwnership_BDMA | 0x4000000);
//
   pFrame->Reserved = (U32)0x0;		// reserved field 
   pFrame->StatusLength = (U32)0x0;	// status & length 
   pFrame->NextDes = NULL;		// next descriptor pointer 

// 		
   pLast = pFrame;			// reset last pointer 
   pFrame++;				// move to next pointer descriptor
   DataAddr += sizeof(sMACFrame); 	// pointer to next data buffer
  } 
      
// Make Frame descriptor to ring buffer type.     
 pFrame--; 
 pFrame->NextDes = (U32)pStart;