memory.c

本source code 為s3c4510的bootloader

       return(-1); 
      } 
     else
     if(rvl == 0)
      {
       Print("Fail.");
       return(0);
      }

// 
     if(hash > 0)
      {
       break;
      }
     else
      {   
       PrintRotSlash(j);
      }
    }
  }

// 
 Print("Ok") ;
 return(1);
}


////////////////////////////////////////////////////////////////////////////////
// Memory Copy Test Top Program ////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////


static void MemoryCopyTest(void) 
{
 U32 MemCopySrc; 				// memory test source address
 U32 MemCopyDest; 				// memory test destination address
 U32 MemTestSize; 				// memory test size
 U32 *src;    					// memory source address
 U32 *dst;    					// memory destination address
 int tsize;   					// memory Test size
 int lsize;   					// memory test loop size

 Print("\n\nMemory Copy Test");

// memory copy test source location ////////////////////////////////////////////

 Print("\nInput Memory Test Source Location (0x01300000)    : 0x");
 MemCopySrc = get_number(16,0);
 if(MemCopySrc == 0) 
  {						/* default source */
   MemCopySrc = 0x1300000;
  }

// memory copy test destination location ///////////////////////////////////////

 Print("\nInput Memory Test Destination Location(0x01400000): 0x");
 MemCopyDest = get_number(16,0);
 if(MemCopyDest == 0) 
  {						/* default destination */
   MemCopyDest=0x1400000;
  }

// memory copy test size ///////////////////////////////////////////////////////
  
 Print("\nInput Memory Test Size (word) (0x10000)           : 0x");
 MemTestSize = get_number(16,0);
 if(MemTestSize==0) 
  {
   MemTestSize=0x10000;				/* default test size */
  }

// memory copy test repeat count ///////////////////////////////////////////////

 Print("\nInput Memory Test repeat number(0x00005)          : 0x");
 lsize = get_number(16,0);
 if(lsize==0) 
  {				
   lsize= 5; 				/* default repeat count */
  }

 src = (U32 *) MemCopySrc;
 dst = (U32 *) MemCopyDest;
 tsize = (int) MemTestSize;
        
 Print("\nSource Memory Location      : 0x%08x",src);
 Print("\nDestination Memory Location : 0x%08x",dst);
 Print("\nMemory Test Size (words)    : 0x%08x",tsize);
 Print("\nMemory Test Loop Count      : %d\n"  ,lsize);

 if( 
  !MemTest
   (
    src		,		/* memory source address */
    dst		,		/* memory destination address */
    tsize	,		/* test size */
    lsize	,		/* loop count */
    0
   )
  ) 
  { 
   Print("\nFail.\n");
  }
 else 
  {
   Print("\nOk.\n");
  }
}

////////////////////////////////////////////////////////////////////////////////
// External I/O Bank Test //////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////


static void ExtIOBankTest(void)
{
 U32 * base0;			// External Bank 0 Base Address
 U32 * base1;			// External Bank 1 Base Address
 U32 * base2;			// External Bank 2 Base address
 U32 * base3;			// External bank 3 base Address
 U32 testSize; 			// -test size (words)
 int lsize = 5; 		// -Ext IO test loop count

 U32 * src;			// 
 U32 val;			// 
 U8 it;				// -bank num
 U8 cfg;			// 
 int i;				// 

// 
 U32 TCOS0;		 	// -Bank 0 Chip selection set-up time on nOE
 U32 TCOS1;		 	// -Bank 1 Chip selection set-up time on nOE
 U32 TCOS2;		 	// -Bank 2 Chip selection set-up time on nOE
 U32 TCOS3;			// -Bank 3 Chip selection set-up time on nOE

// Address set-up time before nECS (tACS0, tACS1, tACS2, tACS3)	////////////////
 U32 TACS0;			// -Bank 0 Address set-up time before nECS
 U32 TACS1;			// -Bank 1 Address set-up time before nECS
 U32 TACS2;			// -Bank 2 Address set-up time before nECS
 U32 TACS3;			// -Bank 3 Address set-up time before nECS

// Chip selection hold time on nOE (tCOH0,tCOH1,tCOH2,tCOH3) ///////////////////
 U32 TCOH0; 			// -Bank 0 Chip selection hold time on nOE 
 U32 TCOH1;			// -Bank 1 Chip selection hold time on nOE 
 U32 TCOH2;			// -Bank 2 Chip selection hold time on nOE 
 U32 TCOH3;			// -Bank 3 Chip selection hold time on nOE 

 U32 TACC0;			// -Bank 0 Access cycles (nOE Low time)
 U32 TACC1; 			// -Bank 1 Access cycles (nOE Low time)
 U32 TACC2; 			// -Bank 2 Access cycles (nOE Low time)
 U32 TACC3;			// -Bank 3 Access cycles (nOE Low time)

// 
 Print("\nExternal I/O Bank Test");

/* REFEXTCON = DRAM Refresh and External I/O control register */
/* [9:0] External I/O Bank 0 Base pointer */

// External I/O bank 0 base pointer ////////////////////////////////////////////
 base0 = (U32 *) ((REFEXTCON & 0x3FF) << 16 ); 	

 base1 = base0 + 4096;		// External I/O bank 1 base pointer
 base2 = base1 + 4096;		// External I/O bank 2 base pointer
 base3 = base2 + 4096;		// External I/O bank 3 base pointer

 Print("\n  External I/O Bank #0 Base Addr : 0x%08x", base0);
 Print("\n  External I/O Bank #1 Base Addr : 0x%08x", base1);
 Print("\n  External I/O Bank #2 Base Addr : 0x%08x", base2);
 Print("\n  External I/O Bank #3 Base Addr : 0x%08x", base3);

// test source address /////////////////////////////////////////////////////////
 src = (U32 *) 0x01300000;
 Print("\nTest External I/O Bank source address (0x%08x)_0x", src);
 val = get_number(16,0);
 if(val != 0)
  {
   src = (U32 *) val; 
  }

// test size ///////////////////////////////////////////////////////////////////
 testSize = 0x1000; 			/* size in words (4K words)*/
 Print("\nTest External I/O Bank size (words) (0x%08x)  _0x", testSize);
 val = get_number(16,0);
 if(val != 0)
  {
   testSize = val; 
  }

// 
 Print("\nConfigure External I/O Bank Bus Width      [Y/N]_");
 cfg = get_upper();
 if(cfg == 'Y')
  {
////////////////////////////////////////////////////////////////////////////////
// configure external banks bus width //////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

   U32 extbdwth;		// bus width register value 
   U32 dsx0; 			// Data bus width for external I/O bank 0
   U32 dsx1; 			// Data bus width for external I/O bank 1
   U32 dsx2; 			// Data bus width for external I/O bank 2
   U32 dsx3; 			// Data bus width for external I/O bank 3

// 
   extbdwth = EXTDBWTH;		// bus width register value 

/*[21:20] Data bus width for external I/O bank 0 (DSX0)	*/
/*[23:22] Data bus width for external I/O bank 1 (DSX1)	*/
/*[25:24] Data bus width for external I/O bank 2 (DSX2)	*/
/*[27:26] Data bus width for external I/O bank 3 (DSX3)	*/  

// extract banks bus width /////////////////////////////////////////////////////

   dsx0 = (extbdwth>>20) & 0x3; // Data bus width for external I/O bank 0
   dsx1 = (extbdwth>>22) & 0x3; // Data bus width for external I/O bank 1
   dsx2 = (extbdwth>>24) & 0x3; // Data bus width for external I/O bank 2
   dsx3 = (extbdwth>>26) & 0x3; // Data bus width for external I/O bank 3

////////////////////////////////////////////////////////////////////////////////
// read from console bus width for bank 0 //////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

   switch(dsx0)			 	/* Data bus width for external I/O bank 0 */
    {	
     case  0 : dsx0 = 'D'; break; 	// disable 
     case  1 : dsx0 = 'B'; break; 	// byte (8 bit)
     case  2 : dsx0 = 'H'; break; 	// half word (16 bit)
     case  3 : dsx0 = 'W'; break; 	// word (32 bit)
     default : dsx0 = 'D'; break; 
    }

   do
    {
     Print
      (
       "\nExternal I/O Bank 0 Bus Width "
       "[D]isable/[B]yte/[H]alf word/[W]ord (%c)_", 
        dsx0
      );

// 
     cfg = get_upper();			// read upper character  
     switch(cfg)			// convert character to numeric value 
      {
       case 'D' : dsx0 = 0; break; 	// Disable bank 0  
       case 'B' : dsx0 = 1; break; 	// Bank 0 bus width is byte
       case 'H' : dsx0 = 2; break; 	// Bank 0 bus width is half word
       case 'W' : dsx0 = 3; break; 	// Bank 0 bus width is word
       default  : cfg  = 0; break;
      }
    } 
   while(cfg == 0);

////////////////////////////////////////////////////////////////////////////////
// read from console bus width for bank 1 //////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

   switch(dsx1)			 	// conver numeric value to letter
    {
     case  0 : dsx1 = 'D'; break; 	// Disable bank 1
     case  1 : dsx1 = 'B'; break; 	// Bank 1 bus width is byte 
     case  2 : dsx1 = 'H'; break; 	// Bank 1 bus width is half word
     case  3 : dsx1 = 'W'; break; 	// Bank 1 bus width is word
     default : dsx1 = 'D'; break; 	// Disable bank 1
    }

   do
    {
// 
     Print
      (
       "\nExternal I/O Bank 1 Bus Width "
       "[D]isable/[B]yte/[H]alf word/[W]ord (%c)_", 
        dsx1
      );

     cfg = get_upper();			// read character from console 
     switch(cfg)			// conver character to numeric value 	
      {
       case 'D' : dsx1 = 0; break; 	// Disable bank 1 
       case 'B' : dsx1 = 1; break; 	// Bank 1 bus width is byte
       case 'H' : dsx1 = 2; break; 	// Bank 1 bus width is half word
       case 'W' : dsx1 = 3; break; 	// Bank 1 bus width is word
       default  : cfg  = 0; break;	// 	
      }
    } 
   while(cfg == 0);

////////////////////////////////////////////////////////////////////////////////
// read bank 2 bus width from console ///////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

   switch(dsx2)			 	// convert numerical value to letter
    {
     case  0 : dsx2 = 'D'; break; 	// Disable Bank 2	
     case  1 : dsx2 = 'B'; break; 	// Bank 2 bus width is byte
     case  2 : dsx2 = 'H'; break; 	// Bank 2 bus width is half byte
     case  3 : dsx2 = 'W'; break; 	// Bank 2 bus width is word
     default : dsx2 = 'D'; break; 	// Disable Bank 2	
    }

   do
    {
     Print
      (
       "\nExternal I/O Bank 2 Bus Width "
       "[D]isable/[B]yte/[H]alf word/[W]ord (%c)_", 
        dsx2
      );

// 
     cfg = get_upper();			// read character from console 
     switch(cfg)			// convert character to numeriacal value 
      {
       case 'D' : dsx2 = 0; break; 	// Disable bank 
       case 'B' : dsx2 = 1; break; 	// Bank 2 bus size is byte
       case 'H' : dsx2 = 2; break; 	// Bank 2 bus size is half word 
       case 'W' : dsx2 = 3; break; 	// Bank 2 bus size is word
       default  : cfg  = 0; break;
      }
    } 
   while(cfg == 0);

////////////////////////////////////////////////////////////////////////////////
// read bank 3 bus width from console //////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

   switch(dsx3)			 	/* Data bus width for external I/O bank 0 */
    {
     case  0 : dsx3 = 'D'; break; 	// Disable Bank 3
     case  1 : dsx3 = 'B'; break; 	// Bank 3 bus size is byte 
     case  2 : dsx3 = 'H'; break; 	// Bank 3 bus size is half word
     case  3 : dsx3 = 'W'; break; 	// Bank 3 bus size is word
     default : dsx3 = 'D'; break; 	// Disable bank 3
    }

   do
    {
     Print
      (
       "\nExternal I/O Bank 3 Bus Width "
       "[D]isable/[B]yte/[H]alf word/[W]ord (%c)_", 
        dsx3
      );
// 
     cfg = get_upper();
     switch(cfg)			/* Data bus width for external I/O bank 0 */
      {
       case 'D' : dsx3 = 0; break; 
       case 'B' : dsx3 = 1; break; 
       case 'H' : dsx3 = 2; break; 
       case 'W' : dsx3 = 3; break; 
       default  : cfg = 0; break;
      }
    } 
   while(cfg == 0);

// 
   extbdwth &= ~EXTDBWTH_DSX0; 		/* Data bus width for external I/O bank 0 */
   extbdwth &= ~EXTDBWTH_DSX1; 		/* Data bus width for external I/O bank 1 */
   extbdwth &= ~EXTDBWTH_DSX2; 		/* Data bus width for external I/O bank 2 */
   extbdwth &= ~EXTDBWTH_DSX3; 		/* Data bus width for external I/O bank 3 */

//
   extbdwth      |=

    (dsx0 << 20) |
    (dsx1 << 22) |
    (dsx2 << 24) |
    (dsx3 << 26);

   Print("\nEXTDBWTH = 0x%08x",extbdwth);
   EXTDBWTH = extbdwth; 		/* Data bus width for external I/O bank 0 */
  } 

////////////////////////////////////////////////////////////////////////////////
// read tested bank num from console ///////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

 Print("\nSelect Test External I/O Bank  (0, 1, 2, 3, Q)  _");
 it = get_upper();
 if(it >= '0' && it <= '3')
  {
   it = it - '0';			// Bank 0 
  }
 else
 if(it == 'Q')
  {
   return; 
  }
 else
  {
   Print("\n  Invalid External I/O Bank Selected [%c]", it);
   return;
  } 	


////////////////////////////////////////////////////////////////////////////////
// configure external I/O bank /////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

 Print("\nConfigure External I/O Bank %c [Y]es/[N]o/[D]efault/[A]ll/[Q]uit]? ", it);
 cfg = get_upper();
 if(cfg == 'Q')
  {
// Quit ////////////////////////////////////////////////////////////////////////
   return;
  }

 if(cfg == 'D')
  {
// default configuration // [D]efault //////////////////////////////////////////

/* Chip selection set-up time on nOE (tCOS0, tCOS1, tCOS2, tCOS3) */
/* [0:2]   EXTACON0 tCOS0 */
/* [0:2]   EXTACON1 tCOS2 */
/* [18:16] EXTACON0 tCOS1 */
/* [18:16] EXTACON1 tCOS3 */

   TCOS0 = (0x7 << EXTACON0_TCOS0_OFFSET); // Bank 0 Chip selection set-up time on nOE
   TCOS1 = (0x7 << EXTACON0_TCOS1_OFFSET); // Bank 1 Chip selection set-up time on nOE
   TCOS2 = (0x7 << EXTACON1_TCOS2_OFFSET); // Bank 2 Chip selection set-up time on nOE
   TCOS3 = (0x7 << EXTACON1_TCOS3_OFFSET); // Bank 3 Chip selection set-up time on nOE

/* Address set-up time before nECS (tACS0, tACS1, tACS2, tACS3)	*/ 
/* [5:3]   EXTACON0 tACS0 */
/* [5:3]   EXTACON1 tACS2 */
/* [21:19] EXTACON0 tACS1 */
/* [21:19] EXTACON1 tACS3 */
   TACS0 = (0x6 << EXTACON0_TACS0_OFFSET); // Bank 0 Address set-up time before nECS
   TACS1 = (0x6 << EXTACON0_TACS1_OFFSET); // Bank 1 Address set-up time before nECS
   TACS2 = (0x6 << EXTACON1_TACS2_OFFSET); // Bank 2 Address set-up time before nECS
   TACS3 = (0x6 << EXTACON1_TACS3_OFFSET); // Bank 3 Address set-up time before nECS

// Chip selection hold time on nOE (tCOH0,tCOH1,tCOH2,tCOH3) ///////////////////
/* [8:6]   EXTACON0 tCOH0 */
/* [8:6]   EXTACON1 tCOH2 */
/* [24:22] EXTACON0 tCOH1 */
/* [24:22] EXTACON1 tCOH3 */
   TCOH0 = (0x6 << EXTACON0_TCOH0_OFFSET); // Bank 0 Chip selection hold time on nOE 
   TCOH1 = (0x6 << EXTACON0_TCOH1_OFFSET); // Bank 1 Chip selection hold time on nOE 
   TCOH2 = (0x6 << EXTACON1_TCOH2_OFFSET); // Bank 2 Chip selection hold time on nOE 
   TCOH3 = (0x6 << EXTACON1_TCOH3_OFFSET); // Bank 3 Chip selection hold time on nOE 

// Access cycles (nOE low time (tACC0,tACC1,tACC2,tACC3)
// [11:9]  EXTACON0 tACC0 
// [11:9]  EXTACON1 tACC2 
// [27:25] EXTACON0 tACC1 
// [27:25] EXTACON1 tACC3 
   TACC0 = (0x7 << EXTACON0_TACC0_OFFSET); // Bank 0 Access cycles (nOE Low time)
   TACC1 = (0x7 << EXTACON0_TACC1_OFFSET); // Bank 1 Access cycles (nOE Low time)
   TACC2 = (0x7 << EXTACON1_TACC2_OFFSET); // Bank 2 Access cycles (nOE Low time)
   TACC3 = (0x7 << EXTACON1_TACC3_OFFSET); // Bank 3 Access cycles (nOE Low time)
  }
 else
 if(cfg != 'N')
  {
////////////////////////////////////////////////////////////////////////////////
// [Y]es / [A]ll ///////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

// Chip selection set-up time on nOE (tCOS0, tCOS1, tCOS2, tCOS3) //////////////
   TCOS0 = (EXTACON0 >> EXTACON0_TCOS0_OFFSET) & 0x7; // Bank 0 Chip selection set-up time on nOE
   TCOS1 = (EXTACON0 >> EXTACON0_TCOS1_OFFSET) & 0x7; // Bank 1 Chip selection set-up time on nOE
   TCOS2 = (EXTACON1 >> EXTACON1_TCOS2_OFFSET) & 0x7; // Bank 2 Chip selection set-up time on nOE
   TCOS3 = (EXTACON1 >> EXTACON1_TCOS3_OFFSET) & 0x7; // Bank 3 Chip selection set-up time on nOE

// Address set-up time before nECS (tACS0, tACS1, tACS2, tACS3)	////////////////
   TACS0 = (EXTACON0 >> EXTACON0_TACS0_OFFSET) & 0x7; // Bank 0 Address set-up time before nECS
   TACS1 = (EXTACON0 >> EXTACON0_TACS1_OFFSET) & 0x7; // Bank 1 Address set-up time before nECS
   TACS2 = (EXTACON1 >> EXTACON1_TACS2_OFFSET) & 0x7; // Bank 2 Address set-up time before nECS
   TACS3 = (EXTACON1 >> EXTACON1_TACS3_OFFSET) & 0x7; // Bank 3 Address set-up time before nECS

// Chip selection hold time on nOE (tCOH0,tCOH1,tCOH2,tCOH3