memory.c

本source code 為s3c4510的bootloader

   num		?
  "tCOH3"	:
  "tCOH1"	,
  ((val >> 22)& 0x7)
 );


/* [27:25] EXTACON0 tACC1 */
/* [27:25] EXTACON1 tACC3 */

 Print("\n[27:25] Access cycles nOE low time       %s=%d"	,
  num		?
  "tACC3"	:
  "tACC1"	,
  ((val >> 25)& 0x7)
 );

// 
 Print("\n");
 return(1);
}

/////////////////////////////////////////////////////////////////////////////
// Print Memory Configuration ///////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////

static int MemViewConf(void)
{
 while(1)
  {
   U8 it;
   Print("\n\nROM/DRAM Configuration");  
   Print("\n[W] EXTDBWTH External data bus width register.");
   Print("\n[0] ROMCON0  ROM/SRAM/FLASH bank 0 register.");
   Print("\n[1] ROMCON1  ROM/SRAM/FLASH bank 1 register.");
   Print("\n[2] ROMCON2  ROM/SRAM/FLASH bank 2 register.");
   Print("\n[3] ROMCON3  ROM/SRAM/FLASH bank 3 register.");
   Print("\n[4] ROMCON4  ROM/SRAM/FLASH bank 4 register.");
   Print("\n[5] ROMCON5  ROM/SRAM/FLASH bank 5 register.");
   Print("\n[A] DRAMCON0 DRAM bank 0 control register.");
   Print("\n[B] DRAMCON1 DRAM bank 1 control register.");
   Print("\n[C] DRAMCON2 DRAM bank 2 control register.");
   Print("\n[D] DRAMCON3 DRAM bank 3 control register.");
   Print("\n[R] REFEXTCON.");
   Print("\n[E] EXTACON0.");
   Print("\n[X] EXTACON1.");
   Print("\n[Q] Quit.");
   Print("\n    Select test item ");
   it = get_upper();
   switch(it)
    {
     case 'W' :  
// EXTDBWTH External data bus width register ///////////////////////////////////
      PrintEXTDBWTH("EXTDBWTH", EXTDBWTH);	//
      break;

     case '0' :
// ROMCON0  ROM/SRAM/FLASH bank 0 register /////////////////////////////////////
      PrintROMCON("ROMCON0", ROMCON0);		//
      break;
      
     case '1' : 
// ROMCON1  ROM/SRAM/FLASH bank 1 register /////////////////////////////////////
      PrintROMCON("ROMCON1", ROMCON1);		//
      break;

     case '2' :
// ROMCON2  ROM/SRAM/FLASH bank 2 register /////////////////////////////////////
      PrintROMCON("ROMCON2", ROMCON2);		//
      break;
      
     case '3' :
// ROMCON3  ROM/SRAM/FLASH bank 3 register /////////////////////////////////////
      PrintROMCON("ROMCON3", ROMCON3);		//
      break;
      
     case '4' :
// ROMCON4  ROM/SRAM/FLASH bank 4 register /////////////////////////////////////
      PrintROMCON("ROMCON4", ROMCON4);		//
      break;
        
     case '5' : 
// ROMCON5  ROM/SRAM/FLASH bank 5 register /////////////////////////////////////
      PrintROMCON("ROMCON5", ROMCON5); 		//
      break;
      
     case 'A' :
// DRAMCON0 DRAM bank 0 control register ///////////////////////////////////////
      PrintDRAMCON("DRAMCON0",DRAMCON0);	//	
      break;
      
     case 'B' :
// DRAMCON0 DRAM bank 1 control register ///////////////////////////////////////
      PrintDRAMCON("DRAMCON1",DRAMCON1);	//
      break;
      
     case 'C' :
// DRAMCON0 DRAM bank 2 control register ///////////////////////////////////////
      PrintDRAMCON("DRAMCON2",DRAMCON2);	//
      break;
      
     case 'D' :
// DRAMCON0 DRAM bank 3 control register ///////////////////////////////////////
      PrintDRAMCON("DRAMCON3",DRAMCON3);	//
      break;
      
     case 'R' :
// REFEXTCON /////////////////////////////////////////////////////////////////// 
      PrintREFEXTCON("REFEXTCON", REFEXTCON);	//
      break; 

     case 'E' :
// EXTACON0 //////////////////////////////////////////////////////////////////// 
      PrintEXTACON(0);				//
      break;

     case 'X' :
// EXTACON1 //////////////////////////////////////////////////////////////////// 
      PrintEXTACON(1);				//
      break;
// 
     case 'Q' :
      return(1);
// 
     default  :
      break;
    } 

   Print("\nPress any key to continue");
   it = get_byte();
   if(it == 'Q' || it == 'q')
    {
     return(1);
    } 
  }
}

// source constant /////////////////////////////////////////////////////////////

#define MemAddrCheck_DRAMCON0 0x0001	// DRAMCON0 (DRAM bank 0) 
#define MemAddrCheck_DRAMCON1 0x0002	// DRAMCON1 (DRAM bank 1)
#define MemAddrCheck_DRAMCON2 0x0004	// DRAMCON2 (DRAM bank 2)
#define MemAddrCheck_DRAMCON3 0x0008	// DRAMCON3 (DRAM bank 3)

#define MemAddrCheck_ROMCON0  0x0010	// ROMCON0 (ROM/SRAM/FLASH bank 0)  
#define MemAddrCheck_ROMCON1  0x0020 	// ROMCON1 (ROM/SRAM/FLASH bank 1)
#define MemAddrCheck_ROMCON2  0x0040 	// ROMCON2 (ROM/SRAM/FLASH bank 2)
#define MemAddrCheck_ROMCON3  0x0080 	// ROMCON3 (ROM/SRAM/FLASH bank 3) 
#define MemAddrCheck_ROMCON4  0x0100 	// ROMCON4 (ROM/SRAM/FLASH bank 4)
#define MemAddrCheck_ROMCON5  0x0200 	// ROMCON5 (ROM/SRAM/FLASH bank 5) 
//

int MemRegions(U32 * base, U32 * limit, U32 * src, int *size, int dramonly)
{
 int cnt = 0;				// 
 int i;				
 int j;

 if(base == 0 || limit == 0 || src == 0 || size == 0)
  {
   return(0);
  } 

//
 if(dramonly == 0)
  {
/* [19:10]  ROM/SRAM/Flash bank # base pointer				      */
/*	    This value is the start address of the ROM/SRAM/Flash bank #.     */
/*          The start address is calculated as ROM/SRAM/FLASH bank # base     */
/*          pointer << 16 						      */
/* 									      */	
/* [29:20]  ROM/SRAM/FLASH bank # next pointer 			              */
/*          This value is the current bank end address << 16 + 1 	      */

   if((EXTDBWTH & EXTDBWTH_DSR0) != 0)
    { 
// Data bus width for ROM/SRAM/FLASH bank 0 ////////////////////////////////////

     if(cnt < *size)
      {
       *(base  + cnt) = (ROMCON0 >> 10) & 0x3FF;// base address of ROM bank 0  
       *(limit + cnt) = (ROMCON0 >> 20) & 0x3FF;// next address for ROM bank 0  
       *(src + cnt++) = MemAddrCheck_ROMCON0;	// source = ROMCON0
      }
    }

   if((EXTDBWTH & EXTDBWTH_DSR1) != 0)
    {
// Data bus width for ROM/SRAM/FLASH bank 1 ////////////////////////////////////
     if(cnt < *size)
      {
       *(base  + cnt) = (ROMCON1 >> 10) & 0x3FF;// base address of ROM bank 1
       *(limit + cnt) = (ROMCON1 >> 20) & 0x3FF;// next address for ROM bank 1
       *(src + cnt++) = MemAddrCheck_ROMCON1;	// source = ROMCON1 
      } 
    }

   if((EXTDBWTH & EXTDBWTH_DSR2) != 0) 
    {
// Data bus width for ROM/SRAM/FLASH bank 2 ////////////////////////////////////
     if(cnt < *size)
      {
       *(base  + cnt) = (ROMCON2 >> 10) & 0x3FF;// base address of ROM bank 2 
       *(limit + cnt) = (ROMCON2 >> 20) & 0x3FF;// next address for ROM bank 2
       *(src + cnt++) = MemAddrCheck_ROMCON2;	// source = ROMCON2 
      }
    }

   if((EXTDBWTH & EXTDBWTH_DSR3) != 0) 
    {
// Data bus width for ROM/SRAM/FLASH bank 3 ////////////////////////////////////
     if(cnt < *size)
      { 
       *(base  + cnt) = (ROMCON3 >> 10) & 0x3FF;// base address of ROM bank 3
       *(limit + cnt) = (ROMCON3 >> 20) & 0x3FF;// next address for ROM bank 3
       *(src + cnt++) = MemAddrCheck_ROMCON3;	// source = ROMCON3
      }
    }
  
   if((EXTDBWTH & EXTDBWTH_DSR4) != 0) 
    {
// Data bus width for ROM/SRAM/FLASH bank 4 ////////////////////////////////////
     if(cnt < *size)
      {
       *(base  + cnt) = (ROMCON4 >> 10) & 0x3FF;// base address of ROM bank 4 	
       *(limit + cnt) = (ROMCON4 >> 20) & 0x3FF;// next address for ROM bank 4
       *(src + cnt++) = MemAddrCheck_ROMCON4;	// source = ROMCON4
      }
    }
  
   if((EXTDBWTH & EXTDBWTH_DSR5) != 0) 
    {
// Data bus width for ROM/SRAM/FLASH bank 5 ////////////////////////////////////
     if(cnt < *size)
      {
       *(base  + cnt) = (ROMCON5 >> 10) & 0x3FF;// base address of ROM bank 5
       *(limit + cnt) = (ROMCON5 >> 20) & 0x3FF;// next address for ROM bank 5
       *(src + cnt++) = MemAddrCheck_ROMCON5;	// source = ROMCON5 
      }
    }
  }

/* [19:10]  DRAM bank # base pointer 					      */
/*          This value indicates the start address of DRAM bank #. 	      */
/*          The start address is calculated as RAM bank # base pointer << 16  */
/* 									      */
/* [29:20]  DRAM bank # Next pointer 					      */
/*          This value isthe current bank end address << 16 + 1               */


 if((EXTDBWTH & EXTDBWTH_DSD0) != 0) 
  {
// Data bus width for DRAM bank 0 //////////////////////////////////////////////
   if(cnt < *size)
    {
     *(base  + cnt) = (DRAMCON0 >> 10) & 0x3FF;	// DRAM bank 0 base address
     *(limit + cnt) = (DRAMCON0 >> 20) & 0x3FF;	// DRAM bank 0 next address	
     *(src + cnt++) = MemAddrCheck_DRAMCON0;	// source = DRAMCON0
    } 
  }

 if((EXTDBWTH & EXTDBWTH_DSD1) != 0) 
  {
// Data bus width for DRAM bank 1 //////////////////////////////////////////////
   if(cnt < *size)
    {
     *(base  + cnt) = (DRAMCON1 >> 10) & 0x3FF;	// DRAM bank 1 base address
     *(limit + cnt) = (DRAMCON1 >> 20) & 0x3FF;	// DRAM bank 1 next address
     *(src + cnt++) = MemAddrCheck_DRAMCON1;	// source = DRAMCON1
    }
  }
  
 if((EXTDBWTH & EXTDBWTH_DSD2) != 0) 
  {
// Data bus width for DRAM bank 2 //////////////////////////////////////////////
   if(cnt < *size)
    {
     *(base  + cnt) = (DRAMCON2 >> 10) & 0x3FF;	// DRAM bank 2 base address
     *(limit + cnt) = (DRAMCON2 >> 20) & 0x3FF;	// DRAM bank 2 next address
     *(src + cnt++) = MemAddrCheck_DRAMCON2;	// source = DRAMCON2
    }
  }

 if((EXTDBWTH & EXTDBWTH_DSD3) != 0) 
  {
// Data bus width for DRAM bank 3 //////////////////////////////////////////////
   if(cnt < *size)
    {
     *(base  + cnt) = (DRAMCON3 >> 10) & 0x3FF;	// DRAM bank 3 base address
     *(limit + cnt) = (DRAMCON3 >> 20) & 0x3FF;	// DRAM bank 3 next address
     *(src + cnt++) = MemAddrCheck_DRAMCON3;	// source = DRAMCON3
    }
  }

// sort base/limit/str /////////////////////////////////////////////////////////

 for(i = 0; i + 1 < cnt; ++i)
  {
   for(j = i + 1; j < cnt; ++j)
    {
     if(*(base + j) < *(base + i))
      {
       U32 tmp;
//
       tmp = *(base + j);
       *(base + j) = *(base + i);
       *(base + i) = tmp;

//
       tmp = *(limit + j);
       *(limit + j) = *(limit + i);
       *(limit + i) = tmp;

//
       tmp = *(src + j);
       *(src + j) = *(src + i);
       *(src + i) = tmp;
      }
    }
  }

// 
 j = 0;
 i = 0;
 while(i < cnt)
  {
   *(base  + j) = *(base + i);
   *(limit + j) = *(limit + i);
   *(src + j) = *(src + i);
   i++;

   while(i < cnt)
    {
     if(*(limit + j) == *(base + i))
      {
       *(limit + j) = *(limit + i);
       *(src + j)  |= *(src + i);
      }
     else
      {
       break;
      }
//
     ++i;
    }
//
   ++j;
  }   

//
 cnt = j;

//
 for(i = 0; i < cnt; ++i)
  {
   *(base  + i) <<= 16;
   *(limit + i) <<= 16;
  }

//
 *size = cnt;
 return(1);
} 
 

/////////////////////////////////////////////////////////////////////////////////
// return free dram regions /////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////

int FreeDramRegions(U32 * base, U32 * limit, int *size)
{
 U32 src[12];				// sourse 
 U32 ubase[3];				// used region base 
 U32 ulimit[3];				// used region limit 
 int cnt;				// count of regions 
 int un;				// used region number
 int n;

 if(base == 0 || limit == 0 || size == 0)
  {
   return(0);
  } 

 if(*size > 12)
  {					// src
   *size = 12;
  } 

// 
 cnt = *size;
 if(MemRegions(base, limit, src, & cnt, 1) == 0)
  {
   return(0);
  } 

// 
 ubase [0] = (U32)Image_RO_Base;	// Image Read Only Base
 ulimit[0] = (U32)Image_RO_Limit;	// Image Read Only Limit
 ubase [1] = (U32)Image_RW_Base;	// Image Read/Write Base
 ulimit[1] = (U32)Image_RW_Limit;	// Image Read/Write Limit
 ubase [2] = (U32)Image_ZI_Base;	// Image Zero Init Base
 ulimit[2] = (U32)Image_ZI_Limit;	// Image Zero Init Limit

 for(un = 0; un < 3; ++un)
  {
   if(ulimit[un] <= ubase[un])
    {					// not used 
     continue;
    } 
// 
   for(n = 0; n < cnt; ++n)
    {
     if(limit[n] <= base[n])
      {					// not used 
       continue;
      } 

     if(ubase[un] >= limit[n] || ulimit[un] <= base[n])
      {
// .....uuuuuuuu.O.uuuuuu 
// ffffff........R......fffffff
       continue;
      } 

     if(ubase[un] <= base[n])
      {
// uuuuuuuuuu
//   fffffff
//   fffffffffff 
       if(limit[n] <= ulimit[un])
        {				
         base[n] = limit[n];		// remove 
        }
       else
        {
         base[n] = ulimit[un];
        }
      }
     else 
      {
//  uuuuuuuuu//
//ffffff
//fffffffffffff 
       if(limit[n] <= ulimit[un])
        {
         limit[n] = ubase[un];		// 
        }
       else
        {
         if(cnt < *size)
          {
           base [cnt] = ulimit[un];
           limit[cnt] = limit[n];
           limit[n]   = ubase[un];
           cnt++;
          }
         else
          {
           return(0);
          }  
        }
      }
    }    
  }

//
// 
 un = 0;
 n = 0;
 while(n < cnt)
  {
   if(*(base + n) < *(limit + n))
    {
     *(base  + un) = *(base  + n);
     *(limit + un) = *(limit + n);
      un++;