memory.c

本source code 為s3c4510的bootloader

/*************************************************************************/
/*                                                                       */
/* FILE NAME                                      VERSION                */
/*                                                                       */
/*      memory.c                   KS32C5000, KS32C50100   : version 1.0 */
/*                                                                       */
/* COMPONENT                                                             */
/*                                                                       */
/*                                                                       */
/* DESCRIPTION                                                           */
/*                                                                       */
/*                                                                       */
/* AUTHOR                                                                */
/*                                                                       */
/*                                                                       */
/* DATA STRUCTURES                                                       */
/*                                                                       */
/*                                                                       */
/* FUNCTIONS                                                             */
/*                                                                       */
/*      Evaluation & debugging utility for memory.                       */
/*                                                                       */
/* DEPENDENCIES                                                          */
/*                                                                       */
/*                                                                       */
/* HISTORY                                                               */
/*                                                                       */
/*         NAME            DATE                    REMARKS               */
/*                                                                       */
/*      hbahn           09-15-1998      Created initial version 1.0      */
/*                                                                       */
/*************************************************************************/

/* 			*/
/* Modified by 		*/
/* Dmitriy Cherkashin 	*/
/* [e-mail]	*/
/* 2002			*/
/*			*/

//#include <stdlib.h>
#include "ks32c50.h"
#include "evm50100.h"


/////////////////////////////////////////////////////////////////////////////
// print content EXTDBWTH ///////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////

static int PrintEXTDBWTH(char * nam, U32 val)
{
 int i;
// 
 if(nam == 0)
  {
   return(0);
  } 

// print register name & value //////////////////////////////////////////////

 Print("\n%12s %08x", nam, val);
 Print("\n%12s ", "");

// 
 for(i = 31; i >= 0; --i)
  {
   if( ((val >> i) & 0x01) != 0)
    {
     Print("1");
    }
   else
    {
     Print("0");
    }
  }
 Print("\n%12s 10987654321098765432109876543210", "");
 Print("\n%12s  3         2         1          ", "");

//
 Print("\nData bus width for:"); 
 Print("\n[ 1: 0] ROM/SRAM/FLASH bank 0 (DSR0)...[%x]", (val >> 0) & 3);
 Print("\n[ 3: 2] ROM/SRAM/FLASH bank 1 (DSR1)...[%x]", (val >> 2) & 3);
 Print("\n[ 5: 4] ROM/SRAM/FLASH bank 2 (DSR2)...[%x]", (val >> 4) & 3);
 Print("\n[ 7: 6] ROM/SRAM/FLASH bank 3 (DSR3)...[%x]", (val >> 6) & 3);
 Print("\n[ 9: 8] ROM/SRAM/FLASH bank 4 (DSR4)...[%x]", (val >> 8) & 3);
 Print("\n[10:11] ROM/SRAM/FLASH bank 5 (DSR5)...[%x]", (val >>10) & 3);
 Print("\n[13:12] DRAM bank 0 (DSD0).............[%x]", (val >>12) & 3);
 Print("\n[15:14] DRAM bank 1 (DSD1).............[%x]", (val >>14) & 3);
 Print("\n[17:16] DRAM bank 2 (DSD2).............[%x]", (val >>16) & 3);
 Print("\n[19:18] DRAM bank 3 (DSD3).............[%x]", (val >>18) & 3);
 Print("\n[21:20] external I/O bank 0 (DSX0).....[%x]", (val >>20) & 3);
 Print("\n[23:22] external I/O bank 1 (DSX1).....[%x]", (val >>22) & 3);
 Print("\n[25:24] external I/O bank 2 (DSX2).....[%x]", (val >>24) & 3);
 Print("\n[27:26] external I/O bank 3 (DSX3).....[%x]", (val >>26) & 3);

//
 Print("\n");
 return(1);
}

/////////////////////////////////////////////////////////////////////////////
// print ROMCON /////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////

static int PrintROMCON(char * nam, U32 val)
{
 int i;
//
 if(nam == 0)
  {
   return(0);
  } 

//
 Print("\n%12s %08x", nam, val);
 Print("\n%12s ", "");
 for(i = 31; i >= 0; --i)
  {
   if( ((val >> i) & 0x01) != 0)
    {
     Print("1");
    }
   else
    {
     Print("0");
    }
  }
 Print("\n%12s 10987654321098765432109876543210", "");
 Print("\n%12s  3         2         1          ", "");

 Print("\n[1:0]   Page mode configuration (PMC)..[%x]", (val >> 0) & 3);
 switch( (val & ROMCON_PMC) )
  {
   case ROMCON_PMC_NORMAL  : Print("\n         00 = Normal ROM"); break;
   case ROMCON_PMC_4WPAGE  : Print("\n         01 = 4-word page"); break;
   case ROMCON_PMC_8WPAGE  : Print("\n         10 = 8-word page"); break;
   case ROMCON_PMC_16WPAGE : Print("\n         11 = 16-word page"); break;
   default :                 Print("\n         Internal error"); break;
  }

//
 Print("\n[3:2]   Page address access time (tPA).[%x]", (val >> 2) & 3);
 switch( (val & ROMCON_TPA) )
  {
   case ROMCON_TPA_5CLK    : Print("\n          00 = 5 cycles"); break;
   case ROMCON_TPA_2CLK    : Print("\n          01 = 2 cycles"); break;
   case ROMCON_TPA_3CLK    : Print("\n          10 = 3 cycles"); break;
   case ROMCON_TPA_4CLK    : Print("\n          11 = 4 cycles"); break;
   default                 : Print("\n          Internal error"); break; 
  }

// 
 Print("\n[6:4]   Programmable access cycle(tACC)[%x]", (val >> 4) & 7);
 switch( (val & ROMCON_TACC) )
  {
   case ROMCON_TACC_DISABLE: Print("\n          000 = Disable bank"); break;
   case ROMCON_TACC_2CLK   : Print("\n          001 = 2 cycles"); break;
   case ROMCON_TACC_3CLK   : Print("\n          010 = 3 cycles"); break;
   case ROMCON_TACC_4CLK   : Print("\n          011 = 4 cycles"); break;
   case ROMCON_TACC_5CLK   : Print("\n          100 = 5 cycles"); break;
   case ROMCON_TACC_6CLK   : Print("\n          101 = 6 cycles"); break;
   case ROMCON_TACC_7CLK   : Print("\n          110 = 7 cycles"); break;
   case ROMCON_TACC_UNUSED : Print("\n          111 = Reserved"); break;
   default :                 Print("\n          Internal error"); break;
  }

// 
 Print("\n[19:10]  ROM/SRAM/Flash base pointer...[%x]",  (val>>10) & 0x3FF);
 Print("\n         ..............................[%x]", ((val>>10) & 0x3FF) << 16);

 Print("\n[29:20]  ROM/SRAM/FLASH next pointer...[%x]",  (val>>20) & 0x3FF);
 Print("\n         ..............................[%x]", ((val>>20) & 0x3FF)<<16);

//
 Print("\n");
 return(1);
}

/////////////////////////////////////////////////////////////////////////////
// print content DRAMCON ////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////


static int PrintDRAMCON(char * nam, U32 val)
{
 int i;
//
 if(nam == 0)
  {
   return(0);
  } 

//
 Print("\n%12s %08x", nam, val);
 Print("\n%12s ", "");
//
 for(i = 31; i >= 0; --i)
  {
   if( ((val >> i) & 0x01) != 0)
    {
     Print("1");
    }
   else
    {
     Print("0");
    }
  }
 Print("\n%12s 10987654321098765432109876543210", "");
 Print("\n%12s  3         2         1          ", "");

////////////////////////////////////////////////////////////////////////////////
 Print("\n [0]      EDO mode(EDO) (note).........[%x]", (val >> 0) & 1);
 switch( (val & DRAMCON_EDO) )
  {
   case DRAMCON_NORMAL     : Print("\n          0 = Normal DRAM (Fast page mode DRAM)"); break;
   case DRAMCON_EDO        : Print("\n          1 = EDO DRAM"); break;
   default                 : Print("\n          Internal error"); break;
  }

////////////////////////////////////////////////////////////////////////////////
 Print("\n [2:1]    CAS strobe time (tCS)........[%x]", (val >> 1) & 3);
 switch( (val & DRAMCON_TCS) ) 
  {
   case DRAMCON_TCS_1CLK   : Print("\n          00 = 1 cycle"); break;
   case DRAMCON_TCS_2CLK   : Print("\n          01 = 2 cycles"); break;
   case DRAMCON_TCS_3CLK   : Print("\n          10 = 3 cycles"); break;
   case DRAMCON_TCS_4CLK   : Print("\n          11 = 4 cycles"); break;
   default                 : Print("\n          Internal error"); break;
  }

//////////////////////////////////////////////////////////////////////////////// 
 Print("\n [3:3]    CAS pre-charge time (tCP )...[%x]", (val >> 3) & 1);
 switch( (val & DRAMCON_TCP) )
  {
   case DRAMCON_TCP_1CLK   : Print("\n          0 = 1 cycle"); break;
   case DRAMCON_TCP_2CLK   : Print("\n          1 = 2 cycles"); break;
   default                 : Print("\n          Internal error"); break;
  }

// 
 Print("\n NOTE     In SDRAM mode, this bit affect SDRAM cycle.");
 Print("\n          tCS value [1] : 0 = 1 cycle, 1 = 2 cycle");

// 
 Print("\n [6:4]    Reserved ....................[%x]", (val >> 4) & 7);
 Print("\n          These bits default value is 000. But, you must set to 001.");

////////////////////////////////////////////////////////////////////////////////  
 Print("\n [7]      RAS to CAS delay(tRC or tRCD)[%x]", (val >> 7) & 1);
 switch( (val & DRAMCON_TRC) )
  {
   case DRAMCON_TRC_1CLK   : Print("\n           0 = 1 cycle"); break;
   case DRAMCON_TRC_2CLK   : Print("\n           1 = 2 cycles"); break;
   default                 : Print("\n           Internal error"); break;
  }

// 
 Print("\n [9:8]    RAS pre-charge time (tRP) ...[%x]", (val >> 8) & 3);
 switch( (val & DRAMCON_TRP) )
  {
   case DRAMCON_TRP_1CLK   : Print("\n           00 = 1 cycle"); break;
   case DRAMCON_TRP_2CLK   : Print("\n           01 = 2 cycles"); break;
   case DRAMCON_TRP_3CLK   : Print("\n           10 = 3 cycles"); break;
   case DRAMCON_TRP_4CLK   : Print("\n           11 = 4 cycles"); break;
  }

//
 Print("\n [19:10]  DRAM bank # base pointer ....[%x] [%x]",  
  (val>>10)&0x3FF		,
 ((val>>10)&0x3FF)<<16);

//
 Print("\n [29:20]  DRAM bank # Next pointer ....[%x] [%x]",  
  (val>>20)&0x3FF		,
 ((val>>20)&0x3FF)<<16);

//////////////////////////////////////////////////////////////////////////////// 
 Print("\n [31:30]  Number of column bits (CAN)..[%x]", (val >> 30) & 3);
 switch( (val & DRAMCON_CAN) )
  {
   case DRAMCON_CAN_8BITS  : Print("\n           00 = 8 bits"); break;
   case DRAMCON_CAN_9BITS  : Print("\n           01 = 9 bits"); break;
   case DRAMCON_CAN_10BITS : Print("\n           10 = 10 bits"); break;
   case DRAMCON_CAN_11BITS : Print("\n           11 = 11 bits"); break;
   default:                  Print("\n           Internal error"); break;
  }

//
 Print("\n");
 return(1);
}

/////////////////////////////////////////////////////////////////////////////
// Print REFEXTCON register /////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////

static int PrintREFEXTCON(char * nam, U32 val)
{
 U32 prd;
 int i;
//
 if(nam == 0)
  {
   return(0);
  } 

//
 Print("\n%12s %08x", nam, val);	// print register name & value   
 Print("\n%12s ", "");			// 
//
 for(i = 31; i >= 0; --i)
  {
   Print
    (
     "%s"		, 		// print register bits
    ((val >> i) & 0x01)	?		
     "1"		:
     "0"
    );
  }
 Print("\n%12s 10987654321098765432109876543210", "");
 Print("\n%12s  3         2         1          ", "");

// 
 Print("\n[9:0]     External I/O base address ...[%x]", ((val>>0) & 0x3FF));
 Print("\n          .............................[%x]", ((val>>0) & 0x3FF)<<16);

////////////////////////////////////////////////////////////////////////////////
 Print("\n[15]      Validity of special reg(VSF).%s"	,
   (val & REFEXTCON_VSF) 		?
  "1(Accessible to memory bank)" 	:
  "0(Not accessible to memory bank)"
  );

////////////////////////////////////////////////////////////////////////////////
 Print("\n[16]      Refresh enable (REN) ........%s"	,
   (val & REFEXTCON_REN) 		?	
   "1(Enable DRAM refresh)"		:
   "0(Disable DRAM refresh)"
  );

//   
 Print("\n[19:17]   CAS hold time(tCHR)..........");
 switch( (val & REFEXTCON_TRC) )
  {
   case REFEXTCON_TRC_1CLK : Print("000 = 1 cycle");  break;
   case REFEXTCON_TRC_2CLK : Print("001 = 2 cycles"); break;
   case REFEXTCON_TRC_3CLK : Print("010 = 3 cycles"); break;
   case REFEXTCON_TRC_4CLK : Print("011 = 4 cycles"); break;
   case REFEXTCON_TRC_5CLK : Print("100 = 5 cycles"); break;
   case REFEXTCON_TRC_6CLK : Print("101 = Not used (6 cycles)"); break;
   default: Print("\nNot used"); break;
  }

// 
 Print("\n NOTE :    In EDO/normal DRAM mode, CAS hold time can be programmed upto");
 Print("\n           5 cycles. But in SDRAM mode, this bit fields function are");
 Print("\n           defined as ROW Cycle Time (tRC) and can be programmed upto");
 Print("\n           6 cycles.");

////////////////////////////////////////////////////////////////////////////////
 Print("\n[20]      CAS setup time(t CSR)........"	,
  (val & REFEXTCON_TCSR) 	?
   "1(2 cycles)"		:
   "0(1 cycle)"
  );

 Print("\nNOTE :    In SDRAM mode, this bit field is reserved.");

//
 Print("\n[31:21]   Refresh count value (duration) ...[%x]", ((val >> 21)));
 Print("\n          The refresh period is calculated as (2 ** 11 - Value + 1) / fMCLK"); 

//
 prd = ( (2048  - (val >> 21) + 1) * 1000 * 1000) / 50000000;  
 Print("\n[31:21]   Refresh period (us) ..............[%d]", prd);

//
 Print("\n");
 return(1);
}

/////////////////////////////////////////////////////////////////////////////
// print EXTACON0/EXTACON1 //////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////


static int PrintEXTACON(int num)
{
 U32 val;				// register value 
// 
 if(num == 0)
  {
   val = EXTACON0;			// EXTACON0 
  }
 else
 if(num == 1) 
  {
   val = EXTACON1;			// EXTACON1 
  }
 else 
  {
   return(0);
  } 


/////////////////////////////////////////////////////////////////////////////
 Print("\nEXTCON%d 0x%08x", num, val);

/* [0:2]   EXTACON0 tCOS0 */
/* [0:2]   EXTACON1 tCOS2 */

 Print("\n[0:2]   Chip selection set-up time on nOE %s=%d"	,
    num 	? 
  "tCOS2"	:
  "tCOS0"	,
  (val & 0x7) 
  );

/* [5:3]   EXTACON0 tACS0 */
/* [5:3]   EXTACON1 tACS2 */

 Print("\n[5:3]   Address set-up time before nECS %s=%d" 	,
   num		?
  "tACS2"	:
  "tACS0"	,
  ((val >> 3) & 0x7) 
  );

/* [8:6]   EXTACON0 tCOH0 */
/* [8:6]   EXTACON1 tCOH2 */

 Print("\n[8:6]   Chip selection hold time on nOE %s=%d"	,
   num		?
   "tCOH2"	:
   "tCOH0"	,
   ((val >> 6) & 0x7)
  );

/* [11:9]  EXTACON0 tACC0 */
/* [11:9]  EXTACON1 tACC2 */

 Print("\n[11:9]  Access cycles nOE low time      %s=%d"	,
   num		?
   "tACC2"	:
   "tACC0"	,
   ((val >> 9) & 0x7) 
  );


/* [18:16] EXTACON0 tCOS1 */
/* [18:16] EXTACON1 tCOS3 */

 Print("\n[18:16] Chip selection set-up time on nOE %s=%d"	,
   num		?
  "tCOS3"	:
  "tCOS1"	,
  ((val >> 16) & 0x7)
 );


/* [21:19] EXTACON0 tACS1 */
/* [21:19] EXTACON1 tACS3 */

 Print("\n[21:19] Address set-up time before nECS   %s=%d"	,
   num		?
  "tACS3"	:
  "tACS1"	,
  ((val >> 19) & 0x7) 
 );


/* [24:22] EXTACON0 tCOH1 */
/* [24:22] EXTACON1 tCOH3 */

 Print("\n[24:22] Chip selection hold time on nOE  %s=%d"	,