evm50100.a

本source code 為s3c4510的bootloader

;
initDRAMCON1   EQU  CAN1+initDRAMEndPtr1+initDRAMBasePtr1+Trp1+Trc1+Tcp1+Tcs1+dumy1+EDO_Mode1    
workDRAMCON1   EQU  CAN1+workDRAMEndPtr1+workDRAMBasePtr1+Trp1+Trc1+Tcp1+Tcs1+dumy1+EDO_Mode1    
;----------------------------------------------------------------------------------
;/* [7] RAS to CAS delay */
SRAS2CASDelay1      EQU  1                      ;(Trc)0=1cycle,1=2cycle
;/* [9:8] RAS pre-charge time */
SRASPrechargeTime1  EQU  1                      ;(Trp)0=1cycle ~ 3=4clcyle
;/* [31:30] Number of column address bits in DRAM bank 1*/
SNoColumnAddr1      EQU  0                      ;0=8bit,1=9bit,2=10bit,3=11bits
;
SCAN1               EQU  SNoColumnAddr1:SHL:30
STrc1               EQU  SRAS2CASDelay1:SHL:7
STrp1               EQU  SRASPrechargeTime1:SHL:8
;
initSDRAMCON1	    EQU	 SCAN1+initDRAMEndPtr1+initDRAMBasePtr1+STrp1+STrc1  		
workSDRAMCON1	    EQU	 SCAN1+workDRAMEndPtr1+workDRAMBasePtr1+STrp1+STrc1  		
;-------------------------------------------------------------------------

;/***********************************************************************/
;/* -> DRAMCON2:RAM Bank2 control register 				*/
;/* 		Offset = 0x3034 					*/
;/***********************************************************************/
;-------------------------------------------------------------------------
;/*[0] EDO Mode : 0=Normal DRAM (Fast page mode DRAM), 1=EDO DRAM */
EDO_Mode2          EQU  0                    	;(EDO)0=Normal, 1=EDO DRAM
;/*[2:1] CAS strobe time : 00=1 cycle, 01=2 cycles, 10=3 cycles, 11=4 cycles */
CasStrobeTime2     EQU  1                   	;(Tcs)0=1cycle ~ 3=4cycle
;/*[3] CAS precharge time*/
CasPrechargeTime2  EQU  0                    	;(Tcp)0=1cycle,1=2cycle
;/*[6:4]Reserved : This bits default value is 000. But, you must set to 001  */
DRAMCON2Reserved   EQU  1                   	; Must be set to 1
;/*[7] RAS to CAS delay */
RAS2CASDelay2      EQU  0                    	;(Trc)0=1cycle,1=2cycle
;/*[9:8] RAS pre-charge time */
RASPrechargeTime2  EQU  0                    	;(Trp)0=1cycle ~ 3=4clcyle
;/*[19:10] DRAM bank 2 base pointer */
initDRAMBasePtr2   EQU  0x240:SHL:10         	
;/*[29:20] DRAM bank 2 Next pointer */
initDRAMEndPtr2    EQU  0x280:SHL:20         	
workDRAMBasePtr2   EQU  0x140:SHL:10         	;=0x14000000  ;
workDRAMEndPtr2    EQU  0x180:SHL:20         	;=0x18000000  ;
;/*[31:30] Number of column address bits in DRAM bank 2 */
NoColumnAddr2      EQU  2                    	;0=8bit,1=9bit,2=10bit,3=11bits
;-------------------------------------------------------------
Tcs2               EQU  CasStrobeTime2:SHL:1	; CAS strobe time 
Tcp2               EQU  CasPrechargeTime2:SHL:3	; CAS precharge time 
dumy2              EQU  DRAMCON2Reserved:SHL:4	; dummy cycle
Trc2               EQU  RAS2CASDelay2:SHL:7	; RAS to CAS delay 
Trp2               EQU  RASPrechargeTime2:SHL:8	; RAS precharge time
CAN2               EQU  NoColumnAddr2:SHL:30	; Number of column address bits 
;
initDRAMCON2   EQU  CAN2+initDRAMEndPtr2+initDRAMBasePtr2+Trp2+Trc2+Tcp2+Tcs2+dumy2+EDO_Mode2    
workDRAMCON2   EQU  CAN2+workDRAMEndPtr2+workDRAMBasePtr2+Trp2+Trc2+Tcp2+Tcs2+dumy2+EDO_Mode2    
;-------------------------------------------------------------
;/* [7] RAS to CAS delay */
SRAS2CASDelay2      EQU  1                      ;(Trc)0=1cycle,1=2cycle
;/* [9:8] RAS precharge time */
SRASPrechargeTime2  EQU  1                      ;(Trp)0=1cycle ~ 3=4clcyle
;/* [31:30]Number of column address bits */
SNoColumnAddr2      EQU  0                      ;0=8bit,1=9bit,2=10bit,3=11bits
;
SCAN2               EQU  SNoColumnAddr2:SHL:30
STrc2               EQU  SRAS2CASDelay2:SHL:7
STrp2               EQU  SRASPrechargeTime2:SHL:8
;
initSDRAMCON2	    EQU	 SCAN2+initDRAMEndPtr2+initDRAMBasePtr2+STrp2+STrc2
workSDRAMCON2	    EQU	 SCAN2+workDRAMEndPtr2+workDRAMBasePtr2+STrp2+STrc2
;-------------------------------------------------------------

;/***********************************************************************/
;/* -> DRAMCON3:RAM Bank3 control register 				*/
;/* 		Offset = 0x3038 					*/
;/***********************************************************************/
;-------------------------------------------------------------------------
;/*[0] EDO Mode: 0=Normal DRAM (Fast page mode DRAM), 1=EDO DRAM */
EDO_Mode3          EQU  0                      ;(EDO)0=Normal, 1=EDO DRAM
;/*[2:1] CAS strobe time : 00=1 cycle,01=2 cycles, 10=3 Cycles, 11=4 cycles*/
CasStrobeTime3     EQU  1                      ;(Tcs)0=1cycle ~ 3=4cycle
;/*[3]CAS pre-charge time*/
CasPrechargeTime3  EQU  0                      ;(Tcp)0=1cycle,1=2cycle
;/*[6:4] Rseserved. This value is set 000. But, you must set to 001*/
DRAMCON3Reserved   EQU  1                      ; Must be set to 1
;/*[7] RAS to CAS delay */
RAS2CASDelay3      EQU  0                      ;(Trc)0=1cycle,1=2cycle
;/*[9:8] RAS pre-charge time : 00=1 cycle, 01=2 cycles, 10=3 cycles, 11=4 cycles */
RASPrechargeTime3  EQU  0                      ;(Trp)0=1cycle ~ 3=4clcyle
;/*[19:10]DRAM bank 3 base pointer */
initDRAMBasePtr3   EQU  0x280:SHL:10  
;/*[29:20] DRAM bank 3 Next pointer*/
initDRAMEndPtr3    EQU  0x2C0:SHL:20  
workDRAMBasePtr3   EQU  0x180:SHL:10  
workDRAMEndPtr3    EQU  0x1C0:SHL:20  

;/*[31:30] Number of column address bits in DRAM bank 3*/
NoColumnAddr3      EQU  2                      ;0=8bit,1=9bit,2=10bit,3=11bits
;-------------------------------------------------------------
Tcs3               EQU  CasStrobeTime3:SHL:1
Tcp3               EQU  CasPrechargeTime3:SHL:3
dumy3              EQU  DRAMCON3Reserved:SHL:4 ; dummy cycle
Trc3               EQU  RAS2CASDelay3:SHL:7
Trp3               EQU  RASPrechargeTime3:SHL:8
CAN3               EQU  NoColumnAddr3:SHL:30
;
initDRAMCON3   EQU  CAN3+initDRAMEndPtr3+initDRAMBasePtr3+Trp3+Trc3+Tcp3+Tcs3+dumy3+EDO_Mode3    
workDRAMCON3   EQU  CAN3+workDRAMEndPtr3+workDRAMBasePtr3+Trp3+Trc3+Tcp3+Tcs3+dumy3+EDO_Mode3    
;-------------------------------------------------------------
;/*[7] RAS to CAS delay */
SRAS2CASDelay3      EQU  1                      ;(Trc)0=1cycle,1=2cycle
;/*[9:8] RAS pre-charge time*/
SRASPrechargeTime3  EQU  1                      ;(Trp)0=1cycle ~ 3=4clcyle
;/*[31:30] Number of column address bits in DRAM bank 3*/
SNoColumnAddr3      EQU  0                      ;0=8bit,1=9bit,2=10bit,3=11bits

SCAN3               EQU  SNoColumnAddr3:SHL:30
STrc3               EQU  SRAS2CASDelay3:SHL:7
STrp3               EQU  SRASPrechargeTime3:SHL:8
;
initSDRAMCON3	    EQU	 SCAN3+initDRAMEndPtr3+initDRAMBasePtr3+STrp3+STrc3
workSDRAMCON3	    EQU	 SCAN3+workDRAMEndPtr3+workDRAMBasePtr3+STrp3+STrc3
;-------------------------------------------------------------------------

;/***********************************************************************/
;/* ->REFEXTCON:External I/O & Memory Refresh cycle Control Register 	*/
;/* 		Offset = 0x303C 					*/
;/***********************************************************************/
;/***********************************************************************/
;/*[9-0] 	External I/O bank 0 base pointer (base address)		*/
;/*[15] 	Validity of special register field (VSF)		*/
;/*		0 = No accessible to memory bank			*/
;/*		1 = Accessible to memory bank				*/
;/*[16] 	Refresh enable (REN)					*/
;/*		0 = Disable DRAM refresh				*/
;/*		1 = Enable DRAM refresh					*/
;/*[19:17] 	CAS hold time (tCHR)					*/
;/*		ROW Cycle Time (tRC) (note 1)				*/
;/*		000=1 cycle	001=2 cycles				*/
;/*		010=3 cycles	011=4 cycles				*/
;/*		100=5 cycles	101=Not Used (6 cycles)			*/
;/*		110=Not used	111=Not Used 				*/
;/*									*/
;/*		NOTE 1: In EDO/normal DRAM mode, CAS hold time		*/
;/*		can bee programmed upto 5 cycles.			*/
;/*		But in SDRAM mode, this bit fields 			*/
;/*		function are defined as ROW Cycle			*/
;/*		Time (tRC) and can be programmed up			*/
;/*		to 6 cycles.						*/
;/*[20] 	CAS setup time (tCSR) (note 2)				*/
;/*		0=1 cycle						*/
;/*		1=2 cycles						*/
;/*     								*/
;/*      	NOTE 2: In SDRAM mode, this bit field is 		*/
;/*      		reserved.					*/
;/*[31:21] 	Refresh count value (duration) 				*/
;/*		The refresh period is calculated as 			*/
;/* 		(2**11 - Value + 1) fMCLK				*/
;/***********************************************************************/
;

RefCycle        EQU   16   ;Unit [us], 1k refresh 16ms
CASSetupTime    EQU   0    ;0=1cycle, 1=2cycle
CASHoldTime     EQU   0    ;0=1cycle, 1=2cycle, 2=3cycle,
                           ;3=4cycle, 4=5cycle,

RefCycleValue   EQU   ((2048+1-(RefCycle*fMCLK)):SHL:21)
Tcsr            EQU   (CASSetupTime:SHL:20)   		; 1 cycle
Tcs             EQU   (CASHoldTime:SHL:17)    		; 1 cycle
ExtIOBase       EQU   0x18360      ; Refresh enable, VSF=1

;    1    8    3    6    0
; 0001 1000 0011 0110 0000
;    6 5432 1098 7654 3210
; External Base 	= 0x360 => 0x360 0000 
; [15] VSF 		= 1
; [16] Refresh enable 	= 1
rREFEXTCON      EQU   RefCycleValue+Tcsr+Tcs+ExtIOBase
;-------------------------------------------------------------
SRefCycle       EQU  16   ;Unit [us], 4k refresh 64ms
;/* ROW Cycle time */
ROWcycleTime    EQU   4    ;0=1cycle, 1=2cycle, 2=3cycle,
                           ;3=4cycle, 4=5cycle,
;
SRefCycleValue  EQU   ((2048+1-(SRefCycle*fMCLK)):SHL:21)
STrc            EQU   (ROWcycleTime:SHL:17) 
;   
rSREFEXTCON     EQU   SRefCycleValue+STrc+ExtIOBase
;-------------------------------------------------------------

;/*************************************************************************/
;/* KS32C50100 SPECIAL REGISTERS                                          */
;/*************************************************************************/

ASIC_BASE	EQU	0x3ff0000

;/* I/O Port Interface */
IOPMOD	  	EQU	ASIC_BASE+0x5000	;/* I/O port mode register 	*/
;/*Reset value=0x00000000 (All I/O port pins - inputs)				*/
;/*[ 0] I/O port mode bit for port 0						*/
;/*[17] I/O port mode bit for port 0						*/
;/*	0=Input									*/
;/*	1=Output								*/
IOPCON  	EQU	ASIC_BASE+0x5004	;/* I/O port control register 	*/
IOPDATA 	EQU	ASIC_BASE+0x5008	;/* I/O port data register 	*/

;/*  UART SPECIAL REGISTERS 0,1  */
UARTLCON0  	EQU	ASIC_BASE+0xD000	;/* UART0 Line Control register */
UARTCONT0  	EQU 	ASIC_BASE+0xD004	;/* UART0 Control register */
UARTSTAT0	EQU	ASIC_BASE+0xD008	;/* UART0 status register */
UARTTXH0	EQU	ASIC_BASE+0xD00C	;/* UART0 transmit buffer register */
UARTRXB0	EQU	ASIC_BASE+0xD010	;/* UART0 receive buffer register */
UARTBRD0	EQU 	ASIC_BASE+0xD014	;/* UART0 baud rate divisor register */

UARTLCON1	EQU 	ASIC_BASE+0xE000	;/* UART 1 Line Control register */
UARTCONT1  	EQU 	ASIC_BASE+0xE004	;/* UART 1 Control register */
UARTSTAT1	EQU	ASIC_BASE+0xE008	;/* UART 1 Status register */
UARTTXH1	EQU	ASIC_BASE+0xE00C	;/* UART 1 transmit buffer register */
UARTRXB1	EQU	ASIC_BASE+0xE010	;/* UART 1 receiver buffer register */
UARTBRD1	EQU 	ASIC_BASE+0xE014	;/* UART 1 baud rate divisor */

UCON0  		EQU	ASIC_BASE+0xD000	;/* UART0 control register s3C4530 */
USTAT0		EQU	ASIC_BASE+0xD004	;/* UART0 status register s3C4530 */
UCON1  		EQU	ASIC_BASE+0xE000	;/* UART1 control register s3C4530  */
USTAT1		EQU	ASIC_BASE+0xE004	;/* UART1 status register s3C4530 */


;/***************************************************************/
       END