evm50100.a

本source code 為s3c4510的bootloader

                                    ; 0x2=3Cycle, 0x3=4Cycle 
;/* Programmable access cycle */
rTacc1          EQU  (0x6:SHL:4)    ; 0x0=Disable, 0x1=2Cycle	; 7 Cycles
                                    ; 0x2=3Cycle, 0x3=4Cycle
                                    ; 0x4=5Cycle, 0x5=6Cycle
                                    ; 0x6=7Cycle, 0x7=Reserved

initROMCON1     EQU initROMEndPtr1+initROMBasePtr1+rTacc1+rTpa1+PMC1
workROMCON1     EQU workROMEndPtr1+workROMBasePtr1+rTacc1+rTpa1+PMC1
;-------------------------------------------------------------------------

;/***********************************************************************/
;/* -> ROMCON2 :ROM Bank2 Control register 				*/
;/*		Offset Address = 0x301C Reset Value    = 0x00000060) 	*/
;/***********************************************************************/
;-------------------------------------------------------------------------
initROMBasePtr2 EQU  0x040:SHL:10   ;=0x0400000 ;  4 
initROMEndPtr2  EQU  0x060:SHL:20   ;=0x0600000 ;  6
workROMBasePtr2 EQU  0x240:SHL:10   ;=0x2400000 ; 36 
workROMEndPtr2  EQU  0x260:SHL:20   ;=0x2600000 ; 38
;/* Page Mode Configuration */
PMC2            EQU  0x0            ; 0x0=Normal ROM, 0x1=4Word Page 	; Normal
                                    ; 0x2=8Word Page, 0x3=16Word Page
;/* Page Access Time */
rTpa2           EQU  (0x0:SHL:2)    ; 0x0=5Cycle, 0x1=2Cycle	; 5 Cycles
                                    ; 0x2=3Cycle, 0x3=4Cycle 
;/* Programmable access cycle */
rTacc2          EQU  (0x6:SHL:4)    ; 0x0=Disable, 0x1=2Cycle	 
                                    ; 0x2=3Cycle, 0x3=4Cycle	; 7 Cycles
                                    ; 0x4=5Cycle, 0x5=6Cycle
                                    ; 0x6=7Cycle, 0x7=Reserved

initROMCON2     EQU  initROMEndPtr2+initROMBasePtr2+rTacc2+rTpa2+PMC2
workROMCON2     EQU  workROMEndPtr2+workROMBasePtr2+rTacc2+rTpa2+PMC2
;-------------------------------------------------------------------------

;/***********************************************************************/
;/* -> ROMCON3 :ROM Bank3 Control register				*/
;/* 		Offset Address = 0x3020	Reset Value    = 0x00000060)	*/
;/***********************************************************************/
;-------------------------------------------------------------------------
initROMBasePtr3 EQU  0x060:SHL:10   ;=0x0600000 ;  6
initROMEndPtr3  EQU  0x080:SHL:20   ;=0x0800000 ;  8
workROMBasePtr3 EQU  0x260:SHL:10   ;=0x2600000 ; 38
workROMEndPtr3  EQU  0x280:SHL:20   ;=0x2800000 ; 40
;/* Page Mode Configuration */
PMC3            EQU  0x0            ; 0x0=Normal ROM, 0x1=4Word Page 
                                    ; 0x2=8Word Page, 0x3=16Word Page
;/* Page Access Time */
rTpa3           EQU  (0x0:SHL:2)    ; 0x0=5Cycle, 0x1=2Cycle
                                    ; 0x2=3Cycle, 0x3=4Cycle 
;/* Programmable access cycle */
rTacc3          EQU  (0x0:SHL:4)    ; 0x0=Disable, 0x1=2Cycle	; Disable
                                    ; 0x2=3Cycle, 0x3=4Cycle
                                    ; 0x4=5Cycle, 0x5=6Cycle
                                    ; 0x6=7Cycle, 0x7=Reserved

initROMCON3     EQU initROMEndPtr3+initROMBasePtr3+rTacc3+rTpa3+PMC3
workROMCON3     EQU workROMEndPtr3+workROMBasePtr3+rTacc3+rTpa3+PMC3
;-------------------------------------------------------------------------

;/***********************************************************************/
;/* -> ROMCON4 :ROM Bank4 Control register				*/
;/*		Offset Address = 0x3024 Reset  Value   = 0x00000060  	*/
;/***********************************************************************/
;-------------------------------------------------------------------------
initROMBasePtr4 EQU  0x080:SHL:10   ;=0x0800000 ;  8 		; Disable
initROMEndPtr4  EQU  0x0A0:SHL:20   ;=0x0A00000 ; 10 	
workROMBasePtr4 EQU  0x280:SHL:10   ;=0x2800000 ; 40
workROMEndPtr4  EQU  0x2A0:SHL:20   ;=0x2A00000 ; 42 	
;/* Page Mode Configuration */ 
PMC4            EQU  0x0            ; 0x0=Normal ROM, 0x1=4Word Page 
                                    ; 0x2=8Word Page, 0x3=16Word Page
;/* Page Access Time */
rTpa4           EQU  (0x0:SHL:2)    ; 0x0=5Cycle, 0x1=2Cycle
                                    ; 0x2=3Cycle, 0x3=4Cycle 
;/* Programmable access cycle */
rTacc4          EQU  (0x0:SHL:4)    ; 0x0=Disable, 0x1=2Cycle	; Disable
                                    ; 0x2=3Cycle, 0x3=4Cycle
                                    ; 0x4=5Cycle, 0x5=6Cycle
                                    ; 0x6=7Cycle, 0x7=Reserved

initROMCON4     EQU initROMEndPtr4+initROMBasePtr4+rTacc4+rTpa4+PMC4
workROMCON4     EQU workROMEndPtr4+workROMBasePtr4+rTacc4+rTpa4+PMC4
;-------------------------------------------------------------------------

;/***********************************************************************/
;/* -> ROMCON5 :ROM Bank5 Control register 				*/
;/*		Offset Address = 0x3028	Reset Value = 0x00000060 	*/
;/***********************************************************************/
initROMBasePtr5 EQU  0x0A0:SHL:10   ;=0x0A00000 ; 10  		; Disable
initROMEndPtr5  EQU  0x0C0:SHL:20   ;=0x0C00000 ; 12 
workROMBasePtr5 EQU  0x2A0:SHL:10   ;=0x2A00000 ; 42
workROMEndPtr5  EQU  0x2C0:SHL:20   ;=0x2C00000 ; 44 
;/* Page Mode Configuration */
PMC5            EQU  0x0            ; 0x0=Normal ROM, 0x1=4Word Page 
                                    ; 0x2=8Word Page, 0x3=16Word Page
;/* Page Access Time */
rTpa5           EQU  (0x0:SHL:2)    ; 0x0=5Cycle, 0x1=2Cycle
                                    ; 0x2=3Cycle, 0x3=4Cycle 
;/* Programmable access cycle */
rTacc5          EQU  (0x0:SHL:4)    ; 0x0=Disable, 0x1=2Cycle	; Disable
                                    ; 0x2=3Cycle, 0x3=4Cycle
                                    ; 0x4=5Cycle, 0x5=6Cycle
                                    ; 0x6=7Cycle, 0x7=Reserved

initROMCON5     EQU initROMEndPtr5+initROMBasePtr5+rTacc5+rTpa5+PMC5
workROMCON5     EQU workROMEndPtr5+workROMBasePtr5+rTacc5+rTpa5+PMC5
;-------------------------------------------------------------------------

;/***********************************************************************/
;/* -> DRAMCON0 :RAM Bank0 control register     			*/
;/* 		Offset      = 0x302C Reset Value = 0x0000 0000		*/
;/*									*/
;/*[0]		EDO mode 						*/
;/*		0 = Normal DRAM (Fast page mode DRAM)			*/
;/*		1 = EDO DRAM						*/
;/*									*/
;/*[2:1]	CAS strobe time	(tCS)					*/
;/*		00 = 1 cycle	01 = 2 cycles				*/
;/*		10 = 3 cycles	11 = 4 cycles				*/
;/*									*/
;/*[3:3]	CAS pre-charge time (tCP)				*/
;/*		0 = 1 cycle	1 = 2 cycles				*/
;/*									*/
;/*[6:4]	Reserved						*/
;/*									*/
;/*[7]		RAS to CAS delay (tRC)					*/
;/*		0 = 1 cycle	1 = 2 cycle 				*/
;/*									*/
;/*[9:8]	RAS pre-charge time (tRP)				*/
;/*		00 = 1 cycle	01 = 2 cycles				*/
;/*		10 = 3 cycles	11 = 4 cycles				*/
;/*									*/
;/*[19:10]	DRAM bank base pointer 					*/
;/*[29:20]	DRAM bank next pointer 					*/
;/*									*/
;/*[31:30]	Number of column address bits in DRAM bank 		*/
;/*		00 = 8 bits	01 = 9 bits				*/
;/*		10 = 10 bits	11 = 11 bits				*/
;/***********************************************************************/
;-------------------------------------------------------------------------
;/* EDO Mode [0] (note: in SDRAM mode, this bit affect SDRAM cycle)*/
EDO_Mode0          EQU  1                    	;(EDO)0=Normal (Fast page mode DRAM), 1=EDO DRAM
;/* CAS strobe time */
CasStrobeTime0     EQU  1                   	;(Tcs)0=1cycle,1=2cycles,2=3cycles,3=4cycle
;/* CAR pre-charge time (note: in SDRAM mode, this bit affect SDRAM cycle)*/
CasPrechargeTime0  EQU  0                  	;(Tcp)0=1cycle,1=2cycle
;/* Reserved */
DRAMCON0Reserved   EQU  1                   	; Must be set to 1
;/* RAS to CAS delay */
RAS2CASDelay0      EQU  0                  	;(Trc)0=1cycle,1=2cycle
;/* RAS pre-charge time */
RASPrechargeTime0  EQU  2                    	;(Trp)0=1cycle ~ 3=4clcyle
;/* DRAM bank base pointer */
initDRAMBasePtr0   EQU  0x100:SHL:10         	;=0x1000000 ; 16
;/* DRAM bank Next pointer */
initDRAMEndPtr0    EQU  0x200:SHL:20         	;=0x2000000 ; 32
workDRAMBasePtr0   EQU  0x000:SHL:10         	;=0x0000000 ;  0 
workDRAMEndPtr0    EQU  0x100:SHL:20         	;=0x1000000 ; 16

NoColumnAddr0      EQU  2                    	;0=8bit,1=9bit,2=10bit,3=11bits
;/* NOTE : in SDRAM mode, this bit affect SDRAM cycle. */
;/*        tCS value[1]: 0 = 1 cycle, 1=2 cycle */
;-------------------------------------------------------------
Tcs0               EQU  CasStrobeTime0:SHL:1	;/* CAS strobe time */		
Tcp0               EQU  CasPrechargeTime0:SHL:3	;/* CAS pre-charge time */
dumy0              EQU  DRAMCON0Reserved:SHL:4 	; dummy cycle
Trc0               EQU  RAS2CASDelay0:SHL:7	;/* RAS to CAS delay */
Trp0               EQU  RASPrechargeTime0:SHL:8	;/* RAS pre-charge time */
CAN0               EQU  NoColumnAddr0:SHL:30	;/* Number of cilumn address bits */
;
initDRAMCON0   EQU  CAN0+initDRAMEndPtr0+initDRAMBasePtr0+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0
workDRAMCON0   EQU  CAN0+workDRAMEndPtr0+workDRAMBasePtr0+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0
;----------------------------------------------------------------------------------
;/* SDRAM Bank 0 settings */
;/* [7] Ras to CAS Delay */
SRAS2CASDelay0      EQU  0   		;(Trc)0=1cycle,1=2cycle
;/* [9:8] RAS pre-charge time 00=1 cycle, 01=2 cycles, 10=3 cycles, 11=4 cycles*/
SRASPrechargeTime0  EQU  1           	;(Trp)0=1cycle ~ 3=4clcyle
;/* [31:30] Number of column address bits in DRAM bank 0*/
SNoColumnAddr0      EQU  0              ;0=8bit,1=9bit,2=10bit,3=11bits
;/* HY57V651620B */
;/* - Row Address: RA0-RA11, Column Address: CA0-CA7 */		;  
;/* - Programmable Burst Length and Burst Type*/		;
;/* 	- 1,2,4,8 or Full page for Sequential Burst */		;
;/* 	- 1,2,3,4 for Interleave Burst */			;
;/* - Programmable CAS Latensy : 2,3 Clocks */			;

STrc0               EQU  SRAS2CASDelay0:SHL:7			; RAS to CAS Delay 
STrp0               EQU  SRASPrechargeTime0:SHL:8		; RAS pre-charge time
SCAN0               EQU  SNoColumnAddr0:SHL:30			; Number of column address bits 
;
initSDRAMCON0	    EQU	 SCAN0+initDRAMEndPtr0+initDRAMBasePtr0+STrp0+STrc0+dumy0
workSDRAMCON0	    EQU	 SCAN0+workDRAMEndPtr0+workDRAMBasePtr0+STrp0+STrc0+dumy0
;-------------------------------------------------------------------------

;/***********************************************************************/
;/* -> DRAMCON1:RAM Bank1 control register 				*/
;/* 		Offset      = 0x3030 Reset Value = 0x00000000		*/
;/***********************************************************************/
;-------------------------------------------------------------------------
;/* [0] EDO mode: 0=Normal EDO (Fast page mode DRAM), 1=EDO DRAM */
EDO_Mode1          EQU  1                      	;(EDO)0=Normal, 1=EDO DRAM
;/* [2:1] CAS strobe time: 00=1 cycle, 01=2 cycles, 10=3 cycles, 11=4 cycles */
CasStrobeTime1     EQU  1                      	;(Tcs)0=1cycle ~ 3=4cycle
;/* [3:3] CAS pre-charge time: 0=1 cycle, 1=2 cycles*/
CasPrechargeTime1  EQU  0                   	;(Tcp)0=1cycle,1=2cycle
;/* [6:4] This bits default value is 000. But, you must set to 001 */
DRAMCON1Reserved   EQU  1                    	; Must be set to 1
;/* [7]   RAS to CAS delay : 0=1cycle. 1=2 cycles */
RAS2CASDelay1      EQU  0                    	;(Trc)0=1cycle,1=2cycle
;/* [9:8] RAS pre-charge time : 00=1 cycle, 01=2 cycles, 10=3 cycles, 11=4 cycles*/
RASPrechargeTime1  EQU  0                    	;(Trp)0=1cycle ~ 3=4clcyle
;/* [19:10] DRAM bank 1 base pointer */
initDRAMBasePtr1   EQU  0x200:SHL:10 
;/* [29:20] DRAM bank 1 Next pointer */
initDRAMEndPtr1    EQU  0x240:SHL:20 
workDRAMBasePtr1   EQU  0x100:SHL:10 
workDRAMEndPtr1    EQU  0x140:SHL:20 
;/* [31:30] Number of column address bits in DRAM bank 1 */
NoColumnAddr1      EQU  2                     	;0=8bit,1=9bit,2=10bit,3=11bits
;-------------------------------------------------------------
Tcs1               EQU  CasStrobeTime1:SHL:1	; CAS strobe time
Tcp1               EQU  CasPrechargeTime1:SHL:3	; CAS pre-charge time
dumy1              EQU  DRAMCON1Reserved:SHL:4 	; dummy cycle
Trc1               EQU  RAS2CASDelay1:SHL:7	; RAS to CAS delay 
Trp1               EQU  RASPrechargeTime1:SHL:8	; RAS pre-charge time 
CAN1               EQU  NoColumnAddr1:SHL:30	; Number of column address bits in DRAM bank 1