📄 evm50100.a
字号:
;/*************************************************************************/;/* */;/* FILE NAME VERSION */;/* */;/* snds.a SNDS100 Board version 1.0 */;/* */;/* COMPONENT */;/* */;/* DESCRIPTION */;/* */;/* SNDS100 for KS32C5000, KS32C50100 ASSEBLER SYSTEM HEADER FILE */;/* */;/* AUTHOR */;/* */;/* Young Sun KIM, Samsung Electronics, Inc. */;/* */;/* DATA STRUCTURES */;/* */;/* */;/* FUNCTIONS */;/* */;/* DEPENDENCIES */;/* */;/* */;/* HISTORY */;/* */;/* NAME DATE REMARKS */;/* */;/* Young Sun KIM 09-25-1998 Created initial version 1.0 */;/*************************************************************************/;/* */;/* Modified by */;/* Dmitriy Cherkashin */;/* dch@ucrouter.ru */;/* 2002 */;/*/ */;/*************************************************************************/;/* Format of the Program Status Register */;/*************************************************************************/;/* */;/* 31 30 29 28 7 6 5 4 3 2 1 0 */;/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+ */;/*| N | Z | C | V | | I | F | T | M4 ~ M0 | */;/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+ */;/* */ ;/* 7:0 (C)onftrol bits */ ;/* 15:8 e(X)tension bits */;/* 23:16 (S)tatus bits */;/* 31:24 (F)lag bits */ ;/* */;/*************************************************************************/;/*************************************************************************/;/* Processor Mode and Mask */;/*************************************************************************/;FBit EQU &40 ; FIQ &=0xIBit EQU &80 ; IRQLOCK_MASK EQU &C0 ; Interrupt lockout mask valueMODE_MASK EQU &1F ; Processor Mode MaskUDF_MODE EQU &1B ; Undefine Mode(UDF)ABT_MODE EQU &17 ; Abort Mode(ABT)SUP_MODE EQU &13 ; Supervisor Mode (SVC)IRQ_MODE EQU &12 ; Interrupt Mode (IRQ)FIQ_MODE EQU &11 ; Fast Interrupt Mode (FIQ)USR_MODE EQU &10 ; User Mode(USR);/*************************************************************************/;/* SYSTEM STACK MEMORY : 8K bytes system stacks are defined at memory.a;/*************************************************************************/ IF :DEF: LED_ONLYDRAM_BASE EQU 0x3FE0000 ; /* Internal SRAM */DRAM_LIMIT EQU 0x3FE2000 ; /* */USR_STACK_SIZE EQU 256 ; /* User stack size */ UDF_STACK_SIZE EQU 128 ; /* Undefined mode stack size */ABT_STACK_SIZE EQU 128 ; /* Abort mode stack size */IRQ_STACK_SIZE EQU 128 ; /* IRQ mode stack size */FIQ_STACK_SIZE EQU 128 ; /* FIQ mode stack size */SUP_STACK_SIZE EQU 128 ; /* Supervisor mode stack size */ ELSE DRAM_BASE EQU 0x1000000 ; /* Address of DRAM start byte */DRAM_LIMIT EQU 0x2000000 ; /* 16 Mbytes, next byte after DRAM */USR_STACK_SIZE EQU 2048 ; /* User stack size */ UDF_STACK_SIZE EQU 512 ; /* Undefined mode stack size */ABT_STACK_SIZE EQU 512 ; /* Abort mode stack size */IRQ_STACK_SIZE EQU 2048 ; /* IRQ mode stack size */FIQ_STACK_SIZE EQU 2048 ; /* FIQ mode stack size */SUP_STACK_SIZE EQU 2048 ; /* Supervisor mode stack size */ ENDIF;/*************************************************************************/;/* SYSTEM CLOCK */;/*************************************************************************/ IF :DEF: KS32C50100fMCLK EQU 50 ; System Clock MHz ELSE fMCLK EQU 50 ; System Clock MHz ENDIF;/***********************************************************************/;/* SYSTEM MEMORY CONTROL REGISTER EQU TABLES */;/***********************************************************************/; ;/***********************************************************************/;/* -> EXTDBWTH:Memory Bus Width register */;/* Offset = 0x3010, Reset Value = 0x0000000 */;/* */;/* [ 1: 0] DSR0 - Data bus width for ROM/SRAM/FLASH bank 0 */;/* */;/* DSR0 is read-only data at the B0SIZE[1:0] pins. DSR0 is read-only */;/* because ROM/SRAM/FLASH bank 0 is used to boot the ROM while the */;/* data bus width for ROM/SRAM/FLASH bank 0 is set using B0SIZE[1:0] */;/* */;/* [ 3: 2] DSR1 - Data bus width for ROM/SRAM/FLASH bank 1 */;/* [ 5: 4] DSR2 - Data bus width for ROM/SRAM/FLASH bank 2 */;/* [ 7: 6] DSR3 - Data bus width for ROM/SRAM/FLASH bank 3 */;/* [ 9: 8] DSR4 - Data bus width for ROM/SRAM/FLASH bank 4 */;/* [11:10] DSR5 - Data bus width for ROM/SRAM/FLASH bank 5 */;/* 00 = Disable */;/* 01 = Byte (8 bits) */;/* 10 = Half-word (16 bits) */;/* 11 = Word (32 bits) */;/* */;/* [13:12] DSD0 - Data bus width for DRAM bank 0 */;/* [15:14] DSD1 - Data bus width for DRAM bank 1 */;/* [17:16] DSD2 - Data bus width for DRAM bank 2 */;/* [19:18] DSD0 - Data bus width for DRAM bank 3 */;/* 00 = Disable */;/* 01 = Byte (8 bits) */;/* 10 = Half-word (16 bits) */;/* 11 = Word (32 bits) */;/* */;/* [21:20] DSX0 - Data bus width for external I/O bank 0 */;/* [23:22] DSX1 - Data bus width for external I/O bank 1 */;/* [25:24] DSX2 - Data bus width for external I/O bank 2 */;/* [27:26] DSX0 - Data bus width for external I/O bank 3 */;/* 00 = Disable */;/* 01 = Byte (8 bits) */;/* 10 = Half-word (16 bits) */;/* 11 = Word (32 bits) */;/***********************************************************************/;-------------------------------------------------------------;/* ROM/SRAM/FLASH */DSR0 EQU 1:SHL:0 ; ROM0, 0 : Disable ; 1 : Byte ; 2 : Half-Word ; 3 : WordDSR1 EQU 1:SHL:2 ; ROM1 ; (Byte)DSR2 EQU 1:SHL:4 ; ROM2 ; (Byte) DSR3 EQU 0:SHL:6 ; ROM3 ; (disable) DSR4 EQU 0:SHL:8 ; ROM4 ; (disable)DSR5 EQU 0:SHL:10 ; ROM5 ; (disable);/* Data bus width for DRAM bank 0,1,2,3 */DSD0 EQU 3:SHL:12 ; DRAM0 ; (Word) DSD1 EQU 0:SHL:14 ; DRAM1 ; (disable)DSD2 EQU 0:SHL:16 ; DRAM2 ; (disable)DSD3 EQU 0:SHL:18 ; DRAM3 ; (disable);/* Data bus width for external I/O banks 0,1,2,3 */DSX0 EQU 0:SHL:20 ; EXTIO0 ; (disable)DSX1 EQU 0:SHL:22 ; EXTIO1 ; (disable)DSX2 EQU 0:SHL:24 ; EXTIO2 ; (disable)DSX3 EQU 0:SHL:26 ; EXTIO3 ; (disable) rEXTDBWTH EQU DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3;/***********************************************************************/;/* -> ROMCON0 :ROM Bank0 Control register */;/* Offset Address=0x3014, Reset Value=0x20000060 */;/* */;/* [1:0] PCM Page mode configuration */;/* 00 = Normal Rom */;/* 01 = 4-word page */;/* 10 = 8-word page */;/* 11 = 16-word page */;/* [3:2] tPA Page address access time */;/* 00 = 5 cycles 01 = 2 cycles */;/* 10 = 3 cycles 11 = 4 cycles */;/* */;/* [6:4] tACC Programmable access cycle */;/* 000= Disable bank 001= 2 cycles */;/* 010= 3 cycles 011= 4 cycles */;/* 100= 5 cycles 101= 6 cycles */;/* 110= 7 cycles 111= Reserved */;/* */;/* [19:10] ROM/SRAM/Flash bank base pointer */;/* [29:20] ROM/SRAM/Flash bank next pointer */;/* */;/***********************************************************************/initROMBasePtr0 EQU 0x000:SHL:10 ;=0x0000000 ; 0 initROMEndPtr0 EQU 0x020:SHL:20 ;=0x0200000 ; 2workROMBasePtr0 EQU 0x200:SHL:10 ;=0x2000000 ; 32workROMEndPtr0 EQU 0x220:SHL:20 ;=0x2200000 ; 34;/* Page Mode Configuration (PCM)*/PMC0 EQU 0x0 ; 0x0=Normal ROM, 0x1=4Word Page ; 0x2=8Word Page, 0x3=16Word Page;/* Page address access time */rTpa0 EQU (0x0:SHL:2) ; 0x0=5Cycle, 0x1=2Cycle ; 5 Cycles ; 0x2=3Cycle, 0x3=4Cycle ;/* Programmable access cycle */;/*16:06:2002 EQU (0x6:SHL:4) */rTacc0 EQU (0x4:SHL:4) ; 0x0=Disable, 0x1=2Cycle ; ; 0x2=3Cycle, 0x3=4Cycle ; 0x4=5Cycle, 0x5=6Cycle ; 0x6=7Cycle, 0x7=ReservedinitROMCON0 EQU initROMEndPtr0+initROMBasePtr0+rTacc0+rTpa0+PMC0workROMCON0 EQU workROMEndPtr0+workROMBasePtr0+rTacc0+rTpa0+PMC0;-------------------------------------------------------------------------;/***********************************************************************/;/* -> ROMCON1 :ROM Bank1 Control register */;/* Offset Address = 0x3018 Reset Value = 0x00000060 */;/***********************************************************************/ initROMBasePtr1 EQU 0x020:SHL:10 ;=0x0200000 ; 2initROMEndPtr1 EQU 0x040:SHL:20 ;=0x0400000 ; 4 workROMBasePtr1 EQU 0x220:SHL:10 ;=0x2200000 ; 34workROMEndPtr1 EQU 0x240:SHL:20 ;=0x2400000 ; 36;/* Page Mode Configuration (PCM) */PMC1 EQU 0x0 ; 0x0=Normal ROM, 0x1=4Word Page ; Normal ; 0x2=8Word Page, 0x3=16Word Page;/* Page address access time */rTpa1 EQU (0x0:SHL:2) ; 0x0=5Cycle, 0x1=2Cycle ; 5 Cycles ⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -