ks32c50.h

本source code 為s3c4510的bootloader

/*              "11" = 3 invalid bytes 					*/
/* 									*/
/* [14] 	BDMA Rx enable (BRxEn) 					*/
/* 		When the Rx enable bit is set to "1", the BDMA Rx block */
/* 		is enabled. Even if this bit is disabled,the MAC will 	*/
/* 		receive Rx data until the MAC Rx FIFO overflows (as 	*/
/* 		long as the FIFO is not empty and the MAC Rx is 	*/
/* 		enabled). This bit is automatically disabled in the 	*/
/* 		following cases: 1) if the next frame pointer is Null,  */
/* 		or 2) if the owner bit is zero, and the			*/
/* 		BRxSTSKO bit is set. 					*/
/* 									*/
/* 		NOTE: The frame descriptor start address pointer must 	*/
/* 		be assigned before the BDMA Rx enable bit is set.	*/
/* 									*/
/*              0 = Disable the BDMA receiver. (If the MAC Rx FIFO is 	*/
/* 		    not empty, move data to the BDMA Rx buffer.)        */
/* 		1 = Enable the BDMA receiver. 				*/
/* 									*/
/* [15] 	BDMA Rx reset (BRxRS) Set this bit to "1" to reset the 	*/
/* 		BDMA Rx block. 						*/
/* 								        */
/* 		0 = No effect. 						*/
/*              1 = Reset the BDMA receiver. 				*/
/* 									*/
/* [16] 	BDMA Rx buffer empty interrupt  enable (BRxEmpty) 	*/
/*              Set this bit is "1" to enable the Rx buffer empty 	*/
/* 		interrupt.  						*/
/* 									*/
/* 		0 = Disable the Rx buffer empty interrupt. 		*/
/* 		1 = Enable the Rx buffer empty interrupt. 		*/
/* 									*/
/* [17] 	BDMA Rx early notify interrupt enable (BRxEarly) 	*/
/* 		Set this bit to "1" to enable the Rx early notify 	*/
/* 		interrupt.  						*/
/* 		The function of this interrupt is to note the length of */
/*		a data frame that is being received from its frame 	*/
/*              length field.						*/
/* 									*/
/* 		0 = Disable the Rx early notify interrupt 		*/
/*              1 = Enable the interrupt when BDMA captures the length  */
/*                  of the received frame type. 			*/
/* 									*/
/************************************************************************/

////////////////////////////////////////////////////////////////////////////////
// BDMARXCON Buffered DMA Receiver Control Register  ///////////////////////////
////////////////////////////////////////////////////////////////////////////////

#define	BDMARXCON_RxBRST	0x0001F	// BDMA Rx Burst Size
					// Burst data size = (BRxBRST + 1) word
#define	BDMARXCON_RxSTSKO	0x00020	// BDMA Rx Stop/Skip  Frame or Interrupt(=1) 
					// case of not OWNER the current Frame 
#define	BDMARXCON_RxMAINC	0x00040	// BDMA Rx Memory Address Inc/Dec 
#define	BDMARXCON_RxDIE		0x00080	// BDMA Rx Every Received Frame Interrupt Enable

#define	BDMARXCON_RxNLIE	0x00100	// BDMA Rx NULL List Interrupt Enable 
#define	BDMARXCON_RxNOIE	0x00200	// BDMA Rx Not Owner Interrupt Enable
#define	BDMARXCON_RxMSOIE	0x00400	// BDMA Rx Maximum Size over Interrupr Enable 
#define	BDMARXCON_RxLittle	0x00800	// BDMA Rx Big/Little Endian 
#define	BDMARXCON_RxBig 	0x00000	// BDMA Rx Big/Little Endian
#define	BDMARXCON_RxWA00        0x00000	// 00 	
#define BDMARXCON_RxWA01	0x01000	// BDMA Rx Word Alignment- one invalid byte 
#define BDMARXCON_RxWA10	0x02000	// BDMA Rx Word Alignment- two invalid byte
#define BDMARXCON_RxWA11	0x03000	// BDMA Rx Word Alignment- three invalid byte 
#define BDMARXCON_RxWA   	0x03000	// BDMA Rx Word Alignment mask
#define	BDMARXCON_RxEn		0x04000	// BDMA Rx Enable
#define	BDMARXCON_RxRS		0x08000	// BDMA Rx Reset
#define	BDMARXCON_RxEmpty	0x10000	// BDMA Rx Buffer empty interrupt 
#define	BDMARXCON_RxEarly	0x20000	// BDMA Rx Early notify Interrupt

#define BDMATXPTR (VPint(Base_Addr+0x9008)) /* Transmit frame descriptor start address */

/************************************************************************//*-*/
/* BDMATXPTR	Transmit Frame descriptor start address 		*/
/* 		Offset Adress = 0x9008, Reset Value = 0xFFFFFFFF  	*/
/* 									*/
/* [25:0] 	BDMA transmit frame descriptor start address		*/
/* 		The BDMA transmit frame descriptor start address 	*/
/* 		register contains the address of the frame descriptor 	*/
/* 		on the frame to be sent. During a BDMA operation, this  */
/* 		start address pointer is updated to the next frame 	*/
/* 		address. 		      				*/
/************************************************************************/

#define BDMARXPTR	(VPint(Base_Addr+0x900c)) /* Receive frame descriptor start address */ 

/************************************************************************//*-*/
/* BDMARXPTR 	Receive frame descriptor start adress 			*/
/* 		Offset Adress = 0x900C					*/
/* 		Reset Value   = 0xFFFFFFFF 				*/
/* 									*/
/* [25:0] 	BDMA receive frame descriptor start address 		*/
/* 		The BDMA receive frame descriptor start address 	*/
/* 		register contains the address of the frame descriptor 	*/
/* 		on the frame to be saved. During a BDMA operation, 	*/
/* 		this start address pointer is updated to the next 	*/
/* 		frame address. 		      				*/
/************************************************************************/

#define BDMARXLSZ	(VPint(Base_Addr+0x9010)) /* Receive frame maximum size */

/************************************************************************//*-*/
/* BDMARXLSZ 	Receive frame maximum size 				*/
/* 		Offset value =  0x9010, Reset Value = Undefined 	*/
/* 									*/
/* [15:0] 	BDMA receive frame maximum size (BRxLSZ) 		*/
/*              This register value controls how many bytes per frame 	*/
/* 		can be saved to memory. If the received frame size 	*/
/* 		exceeds the value stored in this location, an error 	*/
/* 		condition is reported.					*/
/* 									*/
/* [31:16] 	BDMA receive frame length (BRxFSZ), read-only 		*/
/* 		When an early notification (Early Notify) interrupt 	*/
/* 		occurs, the frame length/Ethernet type field contains 	*/
/* 		the Frame size of the frame that is currently being 	*/
/* 		received.						*/
/* 		To save space in the frame memory buffer, you can 	*/
/* 		determine the current frame length by 1) enabling the 	*/
/* 		early notification interrupt, and 2) reading the BRxFSZ */
/* 		field when the interrupt occurs. 			*/
/************************************************************************/

////////////////////////////////////////////////////////////////////////////////
// BDMARXLSZ Receive frame maximum size register ///////////////////////////////
////////////////////////////////////////////////////////////////////////////////

#define BDMARxLSZ 0x0000FFFF	// BDMA receive frame maximum size
#define BDMARxFSZ 0xFFFF0000	// BDMA receive frame length (read-only)

#define BDMASTAT	(VPint(Base_Addr+0x9014)) /* Buffered DMA status */

/************************************************************************/
/* BDMASTAT	Buffered DMA status 					*/
/* 		Offset Address = 0x9014					*/
/* 		Reset Value    = 0x00000000 	      			*/
/* 									*/
/* [0] 		BDMA Rx done every received frame (BRxRDF) 		*/
/* 		This bit is set each time the BDMA receiver moves one   */
/*              received data frame to memory. This bit must be cleared */
/* 		for the receiving next frame interrupt generation.      */
/* 									*/
/* 		0 = Normal operation. 					*/
/*              1 = One frame is received. 				*/
/* 									*/
/* [1] 		BDMA Rx null list (BRxNL) 				*/
/*		If this bit is set, the BDMARXPTR has a null address. 	*/
/* 		Even if BDMA Rx is disabled, data is transferred from	*/
/* 		the MAC Rx FIFO to the BDMA Rx buffer until the BDMA Rx */
/* 		buffer overflows.					*/
/* 									*/
/* 		0 = Normal operation. 					*/
/*              1 = Current frame descriptor has null address 		*/
/* 		    (0x00000000).   					*/
/* 									*/
/* [2] 		BDMA Rx not owner (BRxNO) 				*/
/*              If this bit is set, BDMA is not the owner of the 	*/
/* 		current data frame. The BRxSTSKO bit is set and BDMA 	*/
/* 		Rx is stopped.        					*/
/* 									*/
/* 		0 = BDMA is owner of the current frame. 		*/
/* 		1 = The owner of the current frame is not BDMA. In this */
/* 		    case, BDMA Rx is stopped if the BSTSKO bit is set. 	*/
/* 									*/
/* [3] 		BDMA Rx maximum size over (BRxMSO) 			*/
/*              If this bit is set, the received frame size is larger 	*/
/* 		than the value in the Rx frame maximum size register, 	*/
/* 		BDMARXLSZ.       					*/
/* 									*/
/* 		0 = Normal operation. 					*/
/* 		0 = Received frame exceeds the user defined 		*/
/* 		BDMARXLSZ[15:0] value. 					*/
/* 									*/
/* [4] 		BDMA Rx buffer empty (BRxEmpty) 			*/
/* 		If this bit is set, the BDMA Rx buffer is empty.        */
/* 									*/
/* 		0 = Not empty. 						*/
/* 		1 = BDMA Rx buffer empty. 				*/
/* 									*/
/* [5] 		Early notification (BRxSEarly) 				*/
/* 		This bit is set when the BDMA receiver has received the */
/* 		length/Ether-type field of the current frame. 		*/
/* 									*/
/* 		0 = Normal operation. 					*/
/* 		1 = Length of current frame can be accessed by reading 	*/
/* 		    the BDMA receive maximum frame size register, 	*/
/* 		    BDMARXLSZ [31:16]. 					*/
/* 									*/
/* [6] 		Reserved Not applicable. 				*/
/* 									*/
/* [7] 		One more frame data in BDMA receive buffer (BRxFRF) 	*/
/* 		This bit is set whenever an additional data frame is 	*/
/* 		received in the BDMA receive buffer.			*/
/* 									*/
/* 		0 = Only one frame data reside in BDMA receive buffer. 	*/
/* 		1 = One more frame data reside in the BDMA receive 	*/
/* 		    buffer.    						*/
/* 									*/	
/* [15:8] 	Number of frames in BDMA receive buffer (BRxNFR) 	*/
/* 		This value indicates the total number of data frames    */
/* 		currently in the BDMA receive buffer. 			*/
/*  									*/
/* [16] 	BDMA Tx complete to send control packet (BTxCCP) 	*/
/*              Bit [16] is set each time the MAC sends a complete 	*/
/* 		control packet. 					*/
/* 									*/
/* 		0 = Normal operation. 					*/
/* 		1 = MAC send the control packet. 			*/
/* 									*/
/* [17] 	BDMA Tx null list (BTxNL)				*/
/*              If this bit is set, the BDMATXPTR value is a null 	*/
/* 		address. In this case, BDMA Tx is disabled but data 	*/
/* 		continues to be transferred from the BDMA Tx buffer to 	*/
/* 		the MAC Tx FIFO until the BDMA Tx buffer underflows. 	*/
/* 		This bit is read only. If you set BDMA Tx reset bit by  */
/* 		software, this bit is cleared automatically. To resume 	*/
/* 		data transfer, you must then set the new frame 		*/
/* 		descriptor pointer and enable BDMA Tx. 	      		*/
/* 									*/
/* [18] 	BDMA Tx not owner (BTxNO) 				*/
/*              If [18] is set, BDMA is not owner of the current frame. */
/*              In this case, the BSTSKO bit is set and BDMA Tx is 	*/
/* 		stopped.   						*/
/* 									*/
/* [19] 	Reserved Not applicable. 				*/
/* 									*/
/* [20] 	BDMA Tx buffer empty (BTxEmpty) 			*/
/* 		If this bit is set, the BDMA Tx buffer is empty.  	*/
/* 									*/
/* 		0 = Not empty 						*/
/* 		1 = BDMA Tx buffer empty. 				*/
/* 									*/
/* [31:21] 	Reserved Not applicable. 				*/
/* 									*/
/* NOTE: 	bit 0, 1, 2, 3, 4, 16, 17, 18, and 20 should be cleared */
/* 		for interrupt generation to the next frame. The method  */
/* 		is write a 1 to the corresponding bit location. 	*/
/* 									*/
/************************************************************************/ 

////////////////////////////////////////////////////////////////////////////////
// BDMASTAT BDMA Status Register ///////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

#define	BDMASTAT_BRxRDF	   0x00001 // 0 BDMA Rx Done Every Received Frame 
#define	BDMASTAT_BRxNL	   0x00002 // 1 BDMA Rx NULL List 
#define	BDMASTAT_BRxNO	   0x00004 // 2 BDMA Rx Not Owner 
#define	BDMASTAT_BRxMSO	   0x00008 // 3 BDMA Rx Maximum Size Over 
#define	BDMASTAT_BRxEmpty  0x00010 // 4 BDMA Rx Buffer Empty 
#define	BDMASTAT_BRxSEarly 0x00020 // 5 Early Notify 
#define	BDMASTAT_BRxFRF	   0x00080 // 7 One more frame data in BDMA receive buffer 
#define	BDMASTAT_BRxNFR    0x0FF00 // 15:8 Number of frames in BDMA receive buffer 
#define	BDMASTAT_BTxCCP	   0x10000 // 16 BDMA Tx Complete to send Control Packet 
#define	BDMASTAT_BTxNL	   0x20000 // 17 BDMA Tx Null List 
#define	BDMASTAT_BTxNO	   0x40000 // 18 BDMA Tx Not Owner
#define	BDMASTAT_BTxEmpty 0x100000 // 20 BDMA Tx Buffer Empty 

/************************************************************************/
/* CAM 		Content Address Memory (32 words)			*/
/* 		Offset Adress = 0x9100-0x917C				*/
/* 		Reset Value   = Undefined 				*/
/* 									*/
/* [31:0] 	CAM content (CAM) 					*/
/*   		The CPU uses the CAM content register as a data base 	*/
/* 		for destination addresss. To activate the CAM function, */
/* 		you must set the appropriate enable bits in CAM enable  */
/* 		register   						*/
/* 									*/
/* 	There are 21 CAM entries for the destination address and the 	*/
/* 	Pause control packet. For the destination address CAM value, 	*/
/* 	one destination address consists of 6 bytes. Using the 32-word 	*/
/* 	space (32