ks32c50.h

本source code 為s3c4510的bootloader

#define DRAMCON_TCS_2CLK   0x00000002	/* 01 = 2 cycles */
#define DRAMCON_TCS_3CLK   0x00000004	/* 10 = 3 cycles */
#define DRAMCON_TCS_4CLK   0x00000006	/* 11 = 4 cycles */

/* [3:3] CAS precharge time (tCP) */
#define DRAMCON_TCP        0x00000008	/* CAS precharge time mask */
#define DRAMCON_TCP_1CLK   0x00000000	/* 0 = 1 cycle */
#define DRAMCON_TCP_2CLK   0x00000008	/* 1 = 2 cycle */	

/* [7] RAS to CAS delay(tRC or tRCD) */
#define DRAMCON_TRC        0x00000080	/* RAS to CAS delay mask */
#define DRAMCON_TRC_1CLK   0x00000000	/* 0 = 1 cycle */
#define DRAMCON_TRC_2CLK   0x00000080	/* 1 = 2 cycles */

/* [9:8] RAS pre-charge time (tRP) */
#define DRAMCON_TRP        0x00000300	/* RAS precharge mask */
#define DRAMCON_TRP_1CLK   0x00000000	/* 00 = 1 cycle */
#define DRAMCON_TRP_2CLK   0x00000100	/* 01 = 2 cycles */
#define DRAMCON_TRP_3CLK   0x00000200	/* 10 = 3 cycles */
#define DRAMCON_TRP_4CLK   0x00000300	/* 11 = 4 cycles */

/* [31:30]  Number of column address bits in DRAM bank # (CAN) */
#define DRAMCON_CAN        0xC0000000	/* CAN mask */
#define DRAMCON_CAN_8BITS  0x00000000	/* 00 =  8 bits */
#define DRAMCON_CAN_9BITS  0x40000000	/* 01 =  9 bits */
#define DRAMCON_CAN_10BITS 0x80000000	/* 10 = 10 bits */
#define DRAMCON_CAN_11BITS 0xC0000000	/* 11 = 11 bits */


/************************************************************************/
/* REFEXTCON Refresh and external I/O control register 			*/
/*           Offset      = 0x303C 					*/
/*           Reset Value = 0x00000000 					*/
/* 									*/
/* [9:0]     External I/O bank 0 base pointer (base address)		*/
/*           This value is the start address of external I/O bank 0. 	*/
/*           Start address is defined as External I/O bank 0 base 	*/
/*           pointer << 16. The end address of external I/O bank 0 is 	*/
/*           defined as External I/O bank 0 base pointer >> 16 + 16 K   */
/* 	     bytes-1.						        */
/* 									*/
/* NOTE:     All external I/O banks are located in the continuous 	*/
/* 	     address space which begins at the start address of         */
/*           external I/O bank 0. The size of each external I/O bank    */
/*           is fixed at 16 K bytes. The start and end addresses of the */
/*           other three external I/O banks can be derived from the     */
/*           external I/O bank 0 base pointer value.  			*/ 
/* 									*/
/* [15]      Validity of special register field(VSF) 			*/
/*            0 = Not accessible to memory bank 			*/
/*            1 = Accessible to memory bank 				*/
/* 									*/
/* [16]      Refresh enable (REN) 					*/
/*            0 = Disable DRAM refresh 					*/
/*            1 = Enable DRAM refresh					*/
/* 									*/
/* [19:17]   CAS hold time(tCHR) 					*/
/*           ROW Cycle Time (tRC) (note1)				*/
/*            000 = 1 cycle 						*/
/*            001 = 2 cycles 						*/
/*            010 = 3 cycles 						*/
/*            011 = 4 cycles 						*/
/*            100 = 5 cycles 						*/
/*            101 = Not used (6 cycles)					*/
/*            110 = Not used 						*/
/*            111 = Not used 						*/
/* 									*/
/* NOTE :    In EDO/normal DRAM mode, CAS hold time can be programmed   */ 
/*           upto 5 cycles. But in SDRAM mode, this bit fields function */
/*           are defined as ROW Cycle Time (tRC) and can be programmed  */
/*           upto 6 cycles.						*/
/* 									*/
/* [20]      CAS setup time(t CSR) (note2) 				*/
/*            0 = 1 cycle 					        */
/*            1 = 2 cycles 						*/
/* 									*/
/* NOTE :    In SDRAM mode, this bit field is reserved. 		*/ 
/* 									*/
/* [31:21]   Refresh count value (duration) 				*/
/*           The refresh period is calculated as 			*/
/*           (2**11 - Value + 1) / fMCLK   				*/ 
/************************************************************************/

#define REFEXTCON	(VPint(Base_Addr+0x303c)) 

#define REFEXTCON_VSF      0x00008000   /* [15] Validity of special register field(VSF) */
#define REFEXTCON_REN      0x00010000   /* [16] Refresh enable (REN) */

/* [19:17] CAS hold time(tCHR) */
#define REFEXTCON_TCHR     0x000E0000   /* CAS hold time */
#define REFEXTCON_TRC      0x000E0000   /* ROW Cycle Time */

#define REFEXTCON_TRC_1CLK 0x00000000  	/* 000 = 1 cycle */
#define REFEXTCON_TRC_2CLK 0x00020000   /* 001 = 2 cycles */
#define REFEXTCON_TRC_3CLK 0x00040000   /* 010 = 3 cycles */
#define REFEXTCON_TRC_4CLK 0x00060000   /* 011 = 4 cycles */
#define REFEXTCON_TRC_5CLK 0x00080000   /* 100 = 5 cycles */
#define REFEXTCON_TRC_6CLK 0x000A0000   /* 101 = Not used (6 cycles) */

/* [20] CAS setup time(t CSR) (note2) */
#define REFEXTCON_TCSR      0x00100000	/* */
#define REFEXTCON_TCSR_1CLK 0x00000000	/* 0 = 1 cycle */
#define REFEXTCON_TCSR_2CLK 0x00100000	/* 1 = 2 cycles */


/************************************************************************/
/* Ethernet BDMA Register  						*/
/************************************************************************/

#define BDMATXCON	(VPint(Base_Addr+0x9000)) /* Buffered DMA transmit control register */

/************************************************************************/
/* BDMATXCON 	Buffered DMA transmit control register 			*/
/* 		Offset Address = 0x9000, Reset Value = 0x00000000	*/
/* 									*/
/* [4:0] 	BDMA Tx burst size (BTxBRST)				*/
/*              (Word size + 1) of data bursts requested in BDMA mode.  */
/*              If BTxBRST is zero, the burst size is one word. If	*/
/*		BtXBRST is 31, the burst size is 32 words. 		*/
/* 									*/
/* [5] 		BDMA Tx stop/skip frame by owner bit (BTxSTSKO) 	*/
/* 		0 = Skips the current frame and goes to the next frame 	*/
/* 		    descriptor (if BDMA is not the owner of the frame) 	*/
/* 		1 = BDMA transmitter generates an interrupt (if enabled)*/
/* 									*/
/* [6]          Reserved Not applicable. 				*/
/* 									*/
/* [7] 		BDMA Tx complete to send control packet interrupt enable*/
/*              (BTxCCPIE). 						*/
/* 		0 = Disable complete to send control packet interrupt.	*/
/*              1 = Enable complete to send control packet interrupt. 	*/
/*              (The interrupt is generated when the MAC completes 	*/
/* 		sending the control packet.) 				*/
/* 									*/
/* [8] 		BDMA Tx Null list interrupt enable (BTxNLIE)		*/	
/* 		0 = Disable transmit Null list interrupt. 		*/
/* 		1 = Enable Null list interrupt to indicate that 	*/
/* 		BDMATxPTR in the BDMA Tx unit has a Null address 	*/
/* 		(0x00000000). 	      					*/
/* 									*/
/* [9] 		BDMA Tx not owner interrupt enable (BTxNOIE) 		*/
/* 		0 = Disable BDMA Tx not owner interrupt for the current */
/* 		    frame.						*/
/* 	        1 = Enable BDMA Tx not owner interrupt for the current 	*/
/* 		    frame (and if the BTxSTSKO bit is set). 		*/
/* 									*/
/* [10] 	BDMA Tx buffer empty interrupt enable (BTxEmpty) 	*/
/* 		0 = Disable TX buffer empty interrupt.			*/
/*              1 = Enable TX buffer empty interrupt. 			*/
/* 									*/
/* [13:11]      BDMA transmit to MAC Tx start level (BTxMSL) 		*/
/* 		These bits determine when the new frame data in BDMA Tx */
/* 		buffer can be moved to the MAC Tx FIFO when a new frame */
/* 		arrives. 						*/
/*       	"000" - no wait 					*/
/*              "001" - wait to fill 1/8 of the BDMA Tx buffer		*/
/*              "111" - which means wait to fill 7/8 of the BDMA Tx 	*/
/*                      buffer.   					*/
/* 									*/
/* [14] 	BDMA Tx enable (BTxEn) 					*/
/*		0 = Disable the BDMA transmitter.			*/
/*              1 = Enable the BDMA transmitter. 			*/
/* 									*/
/* [15] 	BDMA Tx reset (BTxRS) 					*/
/*     		0 = No effect. 						*/
/* 		1 = Reset the BDMA Tx block. 				*/
/************************************************************************/

////////////////////////////////////////////////////////////////////////////////
// Buffered DMA	Trasmit	Control Register(BDMATXCON) ////////////////////////////
////////////////////////////////////////////////////////////////////////////////

#define	BDMATXCON_TxBRST	0x0001F	// BDMA Tx Burst Size Mask = 16 
#define	BDMATXCON_TxSTSKO	0x00020	// BDMA Tx Stop (1)/Skip (0) Frame or Interrupt in case
					// of not Owner the current frame 

#define	BDMATXCON_TxCPIE	0x00080	// BDMA Tx Complete to send control 
#define	BDMATXCON_TxCCPIE       0x00080	// packet interrupt Enable

#define BDMATXCON_TxNLIE        0x00100 // BDMA Tx Null list interrupt enable
#define	BDMATXCON_TxNOIE        0x00200	// BDMA Tx Buffer Not Owner
#define	BDMATXCON_TxEmpty	0x00400	// BDMA Tx Buffer Empty Interrupt 
// BDMA Tx buffer can be moved to the MAC Tx IO when the new frame comes in. 
// [13:11] BDMA transmit to MAC Tx start level (BTxMSL)
#define	BDMATXCON_TxMSL000	0x00000	// No wait to fill the BDMA 
#define	BDMATXCON_TxMSL001	0x00800	// wait to fill 1/8 of the BDMA 
#define	BDMATXCON_TxMSL010	0x01000	// wait to fill 2/8 of the BDMA
#define	BDMATXCON_TxMSL011	0x01800	// wait to fill 3/8 of the BDMA
#define	BDMATXCON_TxMSL100	0x02000	// wait to fill 4/8 of the BDMA
#define	BDMATXCON_TxMSL101	0x02800	// wait to fill 5/8 of the BDMA
#define	BDMATXCON_TxMSL110	0x03000	// wait to fill 6/8 of the BDMA
#define	BDMATXCON_TxMSL111	0x03800	// wait to fill 7/8 of the BDMA

#define	BDMATXCON_TxEn		0x04000	// BDMA Tx Enable 
#define	BDMATXCON_TxRS		0x08000	// BDMA Rx Reset 


#define BDMARXCON	(VPint(Base_Addr+0x9004)) /* Buffered DMA receive control register */

/************************************************************************/
/* BDMARXCON 	Buffered DMA receive control register 			*/
/* 		Offset Address = 0x9004					*/
/*              Reset value = 0x00000000 				*/
/* 									*/
/* [4:0] 	BDMA Rx burst size (BRxBRST) 				*/
/* 		Burst data size = (BRxBRST + 1) word 			*/
/* 									*/
/* [5] 		BDMA Rx stop/skip frame by owner bit (BRxSTSKO)		*/
/* 		This bit determines whether the BDMA Rx controller 	*/
/*              issues an interrupt, if enabled, or skips the current 	*/
/*              frame and goes to the next frame descriptor 		*/
/*              (assuming BDMA is not the owner).			*/
/* 		0 = Skips the current frame and goes to the next frame 	*/
/*                  descriptor. 					*/
/*              1 = BDMA receiver generates an interrupt (if enabled). 	*/
/* 									*/
/* [6] 		BDMA Rx memory address inc/dec (BRxMAINC) 		*/
/* 		0 = Decrement the frame memory address. 		*/
/* 		1 = Increment the frame memory address. 		*/
/* 									*/
/* [7] 		BDMA Rx every received frame interrupt enable (BRxDIE) 	*/
/*              This bit enables the BDMA Rx every received frame 	*/
/* 		interrupt which is generated by the BDMA controller 	*/
/*              each time is moves complete data frame into memory. 	*/
/* 									*/
/* 		0 = Disable frame receive done interrupt. 		*/
/*              1 = Enable frame receive done interrupt. 		*/
/* 									*/
/* [8] 		BDMA Rx Null list interrupt enable(BRxNLIE) 		*/
/* 		This bit enables the BDMA Rx Null list interrupt which 	*/
/*              indicates that the receive frame descriptor start 	*/
/*              address pointer, BDMARXPTR, in the BDMA Rx block has 	*/
/*  		a Null (0x00000000) address. 				*/
/* 									*/
/* 		0 = Disable Null address (0x00000000) receive interrupt.*/
/* 		1 = Enable Null address (0x00000000) receive interrupt. */
/* 									*/
/* [9] 		BDMA Rx not owner interrupt enable (BRxNOIE) 		*/
/* 		This bit enables the BDMA Rx not owner interrupt when 	*/
/* 		the ownership bit of the current frame does not belong 	*/
/*              to the BDMA controller, and if the BRxSTSKO bit is set.	*/
/* 									*/
/* 		0 = Disable interrupt for BDMA Rx not owner of the 	*/
/* 		    current frame. 					*/
/*              1 = Enable interrupt for BDMA Rx not owner of the 	*/
/*                  current frame. 					*/
/* 									*/
/* [10] 	BDMA Rx maximum size over interrupt enable (BRxMSOIE) 	*/
/* 		This bit enables the BDMA Rx maximum size over 		*/
/*              interrupt when the received frame size is larger than 	*/
/* 		the value in receive frame maximum size register. 	*/
/* 									*/
/* 		0 = Disable interrupt for received frame if larger than */
/*                  the maximum frame size. 				*/
/*              1 = Enable interrupt for received frame if larger than 	*/
/* 		    the maximum frame size. 				*/
/* 									*/
/* [11] 	BDMA Rx Big/Little Endian (BRxLittle) 			*/
/* 		This bit determines whether the data is stored in 	*/
/* 		Little- or Big-Endian format. If it is set to "1", 	*/
/* 		word swapping will take place between the receive 	*/
/* 		buffer and the system data bus.				*/
/* 									*/
/*   		0 = Big-Endian frame data format.			*/
/*              1 = Little-Endian. (Frame data in BDMA Rx buffer is 	*/
/* 		    word-swapped on the system bus.) 			*/
/* 									*/
/* [13:12] 	BDMA Rx word alignment (BRxWA) 				*/
/* 		The Rx word alignment bits determine how many bytes are */
/* 		invalid in the first word of each data frame. These 	*/
/* 		invalid bytes are inserted when the word is assembled 	*/
/* 		by the BDMA controller. 				*/
/*              "00" = No invalid bytes 				*/
/*              "01" = 1 invalid byte					*/
/* 		"10" = 2 invalid bytes					*/