ks32c50.h

本source code 為s3c4510的bootloader

/* 	   001 = 1 cycle 						*/ 
/* 	   010 = 2 cycle 						*/ 
/* 	   011 = 3 cycles 						*/ 
/* 	   100 = 4 cycles 						*/
/* 	   101 = 5 cycles 						*/
/* 	   110 = 6 cycles 						*/
/* 	   111 = 7 cycles 						*/
/************************************************************************/

/* Chip selection set-up time on nOE (tCOS0, tCOS1, tCOS2, tCOS3) */
#define EXTACON0_TCOS0_OFFSET  0 /* Bank 0 Chip selection set-up time on nOE */
#define EXTACON0_TCOS1_OFFSET 16 /* Bank 1 Chip selection set-up time on nOE */
#define EXTACON1_TCOS2_OFFSET  0 /* Bank 2 Chip selection set-up time on nOE */
#define EXTACON1_TCOS3_OFFSET 16 /* Bank 3 Chip selection set-up time on nOE */

/* Address set-up time before nECS (tACS0, tACS1, tACS2, tACS3)	*/ 
#define EXTACON0_TACS0_OFFSET  3 /* Bank 0 Address set-up time before nECS */
#define EXTACON0_TACS1_OFFSET 19 /* Bank 1 Address set-up time before nECS */
#define EXTACON1_TACS2_OFFSET  3 /* Bank 2 Address set-up time before nECS */
#define EXTACON1_TACS3_OFFSET 19 /* Bank 3 Address set-up time before nECS */

/* Chip selection hold time on nOE (tCOH0,tCOH1,tCOH2,tCOH3) */
#define EXTACON0_TCOH0_OFFSET  6 /* Bank 0 Chip selection hold time on nOE */
#define EXTACON0_TCOH1_OFFSET 22 /* Bank 1 Chip selection hold time on nOE */ 
#define EXTACON1_TCOH2_OFFSET  6 /* Bank 2 Chip selection hold time on nOE */
#define EXTACON1_TCOH3_OFFSET 22 /* Bank 3 Chip selection hold time on nOE */

/* Access cycles (nOE low time (tACC0,tACC1,tACC2,tACC3) */
#define EXTACON0_TACC0_OFFSET  9 /* Bank 0 Access cycles (nOE Low time) */
#define EXTACON0_TACC1_OFFSET 25 /* Bank 1 Access cycles (nOE Low time) */
#define EXTACON1_TACC2_OFFSET  9 /* Bank 2 Access cycles (nOE Low time) */
#define EXTACON1_TACC3_OFFSET 25 /* Bank 3 Access cycles (nOE Low time) */


#define EXTDBWTH	(VPint(Base_Addr+0x3010))

/************************************************************************/
/* EXTDBWTH Data bus width resgister. 					*/
/* 	  Offset      = 0x3010 						*/
/*        Reset value = 0x00000000      				*/ 
/* 									*/
/*[1 : 0] Data bus width for ROM/SRAM/FLASH bank0 (DSR0) 		*/
/* 	  DSR0 is read-only data at the B0SIZE[1:0] pins. DSR0 is 	*/
/* 	  read-only because ROM/SRAM/FLASH bank is used to boot the 	*/  
/* 	  while the data bus width for ROM/SRAM/FLASH bank0 is set 	*/
/* 	  used B0SIZE[1:0] 						*/  
/* 	  								*/
/* 	  00 = Not permitted 						*/
/* 	  01 = Byte (8 bits) 						*/
/*        10 = Half-word (16 bits)					*/ 
/*        11 = Word (32 bits)						*/ 
/* 									*/
/*[ 3: 2] Data bus width for ROM/SRAM/FLASH bank 1 (DSR1)		*/   
/*[ 5: 4] Data bus width for ROM/SRAM/FLASH bank 2 (DSR2)		*/   
/*[ 7: 6] Data bus width for ROM/SRAM/FLASH bank 3 (DSR3)		*/
/*[ 9: 8] Data bus width for ROM/SRAM/FLASH bank 4 (DSR4)		*/   
/*[11:10] Data bus width for ROM/SRAM/FLASH bank 5 (DSR5)		*/   
/* 									*/
/* 	  00 = Disabled 						*/
/* 	  01 = Byte (8 bits) 						*/
/*        10 = Half-word (16 bits)					*/ 
/*        11 = Word (32 bits)						*/ 
/* 									*/
/*[13:12] Data bus width for DRAM bank 0 (DSD0)				*/  
/*[15:14] Data bus width for DRAM bank 1 (DSD1)				*/  
/*[17:16] Data bus width for DRAM bank 2 (DSD2)				*/  
/*[19:18] Data bus width for DRAM bank 3 (DSD3)				*/  
/* 									*/
/* 	  00 = Disabled 						*/
/* 	  01 = Byte (8 bits) 						*/
/*        10 = Half-word (16 bits)					*/ 
/*        11 = Word (32 bits)						*/ 
/* 									*/
/*[21:20] Data bus width for external I/O bank 0 (DSX0)			*/
/*[23:22] Data bus width for external I/O bank 1 (DSX1)			*/
/*[25:24] Data bus width for external I/O bank 2 (DSX2)			*/
/*[27:26] Data bus width for external I/O bank 3 (DSX3)			*/  
/* 									*/
/* 	  00 = Disabled 						*/
/* 	  01 = Byte (8 bits) 						*/
/*        10 = Half-word (16 bits)					*/ 
/*        11 = Word (32 bits)						*/ 
/* 									*/
/************************************************************************/

#define EXTDBWTH_DSR0     0x00000003 /* Data bus width for ROM/SRAM/FLASH bank 0 */
#define EXTDBWTH_DSR1     0x0000000C /* Data bus width for ROM/SRAM/FLASH bank 1 */
#define EXTDBWTH_DSR2     0x00000030 /* Data bus width for ROM/SRAM/FLASH bank 2 */
#define EXTDBWTH_DSR3     0x000000C0 /* Data bus width for ROM/SRAM/FLASH bank 3 */
#define EXTDBWTH_DSR4     0x00000300 /* Data bus width for ROM/SRAM/FLASH bank 4 */
#define EXTDBWTH_DSR5     0x00000C00 /* Data bus width for ROM/SRAM/FLASH bank 5 */

#define EXTDBWTH_DSD0     0x00003000 /* Data bus width for DRAM bank 0 */
#define EXTDBWTH_DSD1     0x0000C000 /* Data bus width for DRAM bank 1 */
#define EXTDBWTH_DSD2     0x00030000 /* Data bus width for DRAM bank 2 */
#define EXTDBWTH_DSD3     0x000C0000 /* Data bus width for DRAM bank 3 */


#define EXTDBWTH_DSX0     0x00300000 /* Data bus width for external I/O bank 0 */
#define EXTDBWTH_DSX1     0x00C00000 /* Data bus width for external I/O bank 1 */
#define EXTDBWTH_DSX2     0x03000000 /* Data bus width for external I/O bank 2 */
#define EXTDBWTH_DSX3     0x0C000000 /* Data bus width for external I/O bank 3 */

#define EXTDBWTH_DSR0_OFF          0 /* */
#define EXTDBWTH_DSR1_OFF          2 /* */
#define EXTDBWTH_DSR2_OFF          4 /* */
#define EXTDBWTH_DSR3_OFF          6 /* */
#define EXTDBWTH_DSR4_OFF          8 /* */
#define EXTDBWTH_DSR5_OFF         10 /* */

#define EXTDBWTH_DSD0_OFF         12 /* */
#define EXTDBWTH_DSD1_OFF         14 /* */
#define EXTDBWTH_DSD2_OFF         16 /* */
#define EXTDBWTH_DSD3_OFF         18 /* */

#define EXTDBWTH_DSX0_OFF         20 /* */
#define EXTDBWTH_DSX1_OFF         22 /* */
#define EXTDBWTH_DSX2_OFF         24 /* */
#define EXTDBWTH_DSX3_OFF         26 /* */

//
/************************************************************************/
/* ROMCON0,ROMCON1,ROMCON2,ROMCON3,ROMCON4,ROMCON5			*/   
/* 									*/	
/* [1:0]   Page mode configuration (PMC) 				*/
/* 	    00 = Normal ROM 						*/
/*          01 = 4-word page 						*/
/*          10 = 8-word page 						*/
/*          11 = 16-word page 						*/
/* 									*/	
/* [3:2]   Page address access time (tPA) 			        */
/*          00 = 5 cycles 						*/
/*          01 = 2 cycles 						*/
/*          10 = 3 cycles 						*/
/*          11 = 4 cycles 						*/
/* 									*/	
/* [6:4]   Programmable access cycle (tACC)  				*/
/*          000 = Disable bank 						*/
/*          001 = 2 cycles 						*/
/*          010 = 3 cycles 						*/
/*          011 = 4 cycles 						*/
/*          100 = 5 cycles 						*/
/*          101 = 6 cycles 						*/
/*          110 = 7 cycles 						*/
/*          111 = Reserved 						*/
/* 									*/	
/* [19:10]  ROM/SRAM/Flash bank # base pointer				*/
/*	    This value is the start address of the ROM/SRAM/Flash bank. */
/*          The start address is calculated as ROM/SRAM/FLASH bank base */
/*          pointer << 16 						*/
/* 									*/	
/* [29:20]  ROM/SRAM/FLASH bank # next pointer 			        */
/*          This value is the current bank end address << 16 + 1 	*/
/* 									*/	
/************************************************************************/

#define ROMCON0		(VPint(Base_Addr+0x3014)) /* ROM/SRAM/Flash bank 0 control register */
#define ROMCON1		(VPint(Base_Addr+0x3018)) /* ROM/SRAM/Flash bank 1 control register */
#define ROMCON2		(VPint(Base_Addr+0x301c)) /* ROM/SRAM/Flash bank 2 control register */
#define ROMCON3		(VPint(Base_Addr+0x3020)) /* ROM/SRAM/Flash bank 3 control register */
#define ROMCON4		(VPint(Base_Addr+0x3024)) /* ROM/SRAM/Flash bank 4 control register */
#define ROMCON5		(VPint(Base_Addr+0x3028)) /* ROM/SRAM/Flash bank 5 control register */


/* Page mode configuration (PMC) */

#define ROMCON_PMC          0x00000003	/* Page mode mask */
#define ROMCON_PMC_NORMAL   0x00000000	/* 00 = Normal ROM */
#define ROMCON_PMC_4WPAGE   0x00000001	/* 01 = 4-word page */
#define ROMCON_PMC_8WPAGE   0x00000002	/* 10 = 8-word page */
#define ROMCON_PMC_16WPAGE  0x00000003	/* 11 = 16-word page */

/* [3:2] Page address access time (tPA) */

#define ROMCON_TPA          0x0000000C	/* page address access time mask */
#define ROMCON_TPA_5CLK     0x00000000	/* 00 = 5 cycles */
#define ROMCON_TPA_2CLK     0x00000004	/* 01 = 2 cycles */
#define ROMCON_TPA_3CLK     0x00000008	/* 10 = 3 cycles */
#define ROMCON_TPA_4CLK     0x0000000C	/* 11 = 4 cycles */

/* [6:4]   Programmable access cycle (tACC) */

#define ROMCON_TACC         0x00000070	/* access cycle mask */

#define ROMCON_TACC_DISABLE 0x00000000	/* 000 = Disable bank */
#define ROMCON_TACC_2CLK    0x00000010	/* 001 = 2 cycles */
#define ROMCON_TACC_3CLK    0x00000020	/* 010 = 3 cycles */
#define ROMCON_TACC_4CLK    0x00000030	/* 011 = 4 cycles */	
#define ROMCON_TACC_5CLK    0x00000040	/* 100 = 5 cycles */
#define ROMCON_TACC_6CLK    0x00000050	/* 101 = 6 cycles */
#define ROMCON_TACC_7CLK    0x00000060	/* 110 = 7 cycles */
#define ROMCON_TACC_UNUSED  0x00000070	/* 111 = Reserved */


#define ROMCON_BASE_MASK    0x000FFC00  /* 19:10  base pointer mask */
#define ROMCON_BASE_OFFSET          10  /* base pointer offset */

#define ROMCON_NEXT_MASK    0x3FF00000  /* 29:20  base pointer mask */
#define ROMCON_NEXT_OFFSET          20  /* base pointer offset */

//

/************************************************************************/
/* DRAMCON0 DRAM bank 0 control register 				*/
/*          Offset      = 0x302C 					*/
/*          Reset Value = 0x00000000 					*/
/* 									*/
/* DRAMCON1 DRAM bank 1 control register 	 			*/
/*          Offset      = 0x3030 					*/
/*          Reset Value = 0x00000000					*/
/* 									*/
/* DRAMCON2 DRAM bank 2 control register 				*/
/*          Offset      = 0x3034 					*/
/*          Reset Value = 0x00000000 					*/
/* 									*/
/* DRAMCON3 DRAM bank 3 control register				*/
/*          Reset Value = 0x00000000 					*/
/* 									*/
/* [0]      EDO mode(EDO) (note)					*/
/*          0 = Normal DRAM (Fast page mode DRAM) 			*/
/*          1 = EDO DRAM						*/
/* 									*/
/* [2:1]    CAS strobe time (tCS) 					*/
/*          00 = 1 cycle 						*/
/*          01 = 2 cycles 						*/
/*          10 = 3 cycles 						*/
/*          11 = 4 cycles 						*/
/* 									*/
/* [3:3]    CAS pre-charge time (tCP ) (note) 				*/
/*          0 = 1 cycle 						*/
/*          1 = 2 cycles 						*/
/* 									*/
/* NOTE     In SDRAM mode, this bit affect SDRAM cycle. 		*/
/*          tCS value [1] : 0 = 1 cycle, 1 = 2 cycle 			*/
/* 									*/
/* [6:4]    Reserved 							*/
/*          These bits default value is 000. But, you must set to 001.  */
/* 									*/
/* [7]      RAS to CAS delay(tRC or tRCD)  				*/
/*           0 = 1 cycle 						*/
/*           1 = 2 cycles 						*/
/* 									*/
/* [9:8]    RAS pre-charge time (tRP)  					*/
/*           00 = 1 cycle 						*/
/*           01 = 2 cycles 						*/
/*           10 = 3 cycles 						*/
/*           11 = 4 cycles						*/
/* 									*/
/* [19:10]  DRAM bank # base pointer 					*/
/*          This value indicates the start address of DRAM bank #. 	*/
/*          The start address is calculated as RAM bank # 		*/
/*          base pointer << 16  					*/
/* 									*/
/* [29:20]  DRAM bank # Next pointer 					*/
/*          This value isthe current bank end address << 16 + 1         */
/* 									*/
/* [31:30]  Number of column address bits in DRAM bank # (CAN)          */
/*           00 =  8 bits 						*/
/*           01 =  9 bits 					        */
/*           10 = 10 bits 						*/
/*           11 = 11 bits 						*/
/************************************************************************/

#define DRAMCON0 (VPint(Base_Addr+0x302c)) /* DRAM bank 0 control register */
#define DRAMCON1 (VPint(Base_Addr+0x3030)) /* DRAM bank 1 control register */
#define DRAMCON2 (VPint(Base_Addr+0x3034)) /* DRAM bank 2 control register */
#define DRAMCON3 (VPint(Base_Addr+0x3038)) /* DRAM bank 3 control register */


#define DRAMCON_NORMAL     0x00000000	/* Normal DRAM */
#define DRAMCON_EDO        0x00000001	/* 1 = EDO DRAM	*/

/* [2:1] CAS strobe time (tCS) */
#define DRAMCON_TCS        0x00000006	/* CAS strobe time mask */
#define DRAMCON_TCS_1CLK   0x00000000	/* 00 = 1 cycle */