ks32c50.h

本source code 為s3c4510的bootloader

/*************************************************************************/
/*                                                                       */
/* FILE NAME                                      VERSION                */
/*                                                                       */
/*      snds.h                     KS32C5000, KS32C50100   : version 1.0 */
/*                                                                       */
/* COMPONENT                                                             */
/*                                                                       */
/*                                                                       */
/* DESCRIPTION                                                           */
/*                                                                       */
/*      Board Specific Routines for NetMCU-I series.                     */
/*                                                                       */
/* AUTHOR                                                                */
/*                                                                       */
/*                                                                       */
/* DATA STRUCTURES                                                       */
/*                                                                       */
/*                                                                       */
/* FUNCTIONS                                                             */
/*                                                                       */
/*                                                                       */
/* DEPENDENCIES                                                          */
/*                                                                       */
/*                                                                       */
/* HISTORY                                                               */
/*                                                                       */
/*         NAME            DATE                    REMARKS               */
/*                                                                       */
/*      hbahn           09-15-1998      Created initial version 1.0      */
/*      in4maker        05-10-1999      Added CAM_Reg(x)                 */
/*                                                                       */
/*************************************************************************/

/* 			*/
/* Modifyed by 		*/
/* Dmitriy Cherkashin 	*/
/* [e-mail]	*/
/* 2002, 2003		*/
/*			*/

#ifndef _SNDS_H
#define _SNDS_H

#ifdef  _S3C4530_	
#define _KS32C50100_
#else
#ifndef _KS32C50100_ 
#define _KS32C50100_ 
#endif
#endif 								// _S3C4530_


/*------------------------------------------------------------------------
 *	  ASIC Address Definition
 *----------------------------------------------------------------------*/

#define VPint    *(volatile unsigned int   *)		
#define VPshort  *(volatile unsigned short *)		
#define VPchar   *(volatile unsigned char  *)		

#define  	Base_Addr	0x3ff0000		
								
/************************************************************************/
/* System Configuration Register 					*/
/************************************************************************/

#define SYSCFG		(VPint(Base_Addr+0x0000))	

/************************************************************************/
/* System Configuration Register (SYSCFG). 				*/
/*									*/
/* 	 Offset      = 0x0000						*/
/*       Reset Value = 0x07FFFF91 KS32C50100				*/
/* 		       0x4FFFFF91 S3c4530A				*/
/* 									*/
/*[0] 	 Stal enable (SE). Must be set to zero 				*/
/*[1] 	 Cache enable (CE). Then set to "1", cache operation are enabled*/
/*[2]    Write buffer enable (WE). Then set to '1", write buffer 	*/
/* 	 operation  are enabled 					*/
/*[3]    Fixed Priority (FP)						*/
/* 	  0 = Round-robin 						*/
/* 	  1 = Fixed priority within Group 				*/
/* 	 NOTE: S3C4530A 						*/
/*[5:4]  Cache mode (CM). This 2-bit value determines how the internal 	*/
/* 	 memory is to be divided into cache and SRAM 			*/
/* 	 00 = 4-Kbyte SRAM, 4-Kbyte cache 				*/
/* 	 01 = 0-Kbyte SRAM, 8-Kbyte cache 				*/
/* 	 10 = 8-Kbyte SRAM, 0-Kbyte cache 				*/
/* 									*/
/* NOTE: When you write 10, to this field, the cache enable bit is 	*/
/* 	 is cleared automatically. 					*/
/* 									*/
/*[15:6] Internal SRAM base pointer. This 10-bit address becoms the 	*/
/* 	 the upper address of SRAM. A25 through A16, the remaining 	*/
/*       SRAM adresses, and A15 through A0, are filled with zeros. 	*/    
/* 									*/
/*[25:16]Special register bank base pointer. The resolution of this 	*/
/*       value is 64K.							*/
/* 									*/
/*[29:26]Product Identifier (PD_ID)  					*/
/*       0000=KS32C5000							*/
/*       0001=KS32C50100						*/
/* 									*/
/* 									*/
/*[30:26]Product Identifier (PD_ID) 					*/
/* 	 00001 = S3C4510X (KS32C50100) 					*/
/* 	 11001 = S3C4510B 						*/
/* 	 00011 = S3C4530X (KS32C50300) 					*/
/* 	 10011 = S3C4530A 						*/
/*[31]   Sync. DRAM mode 						*/	 
/* 	 0 = Noemal/EDO DRAM interface for 4 DRAM banks 		*/
/*       1 = Sync. DRAM interface for 4 DRAM banks 			*/
/************************************************************************/

#define SYSCFG_STALL         	0x00000001 	/* (SE) Stall enable bit */
#define SYSCFG_CACHE         	0x00000002	/* (CE) Cache enable bit */
#define SYSCFG_WRITE_BUFF    	0x00000004	/* (WE) Write enable bit */

/*[3] Fixed Priority (FP) */
#ifdef _S3C4530_
#define SYSCFG_FP         	0x00000008	/* (FP) Fixed Priority */
#endif							/* _S3C4530_ 	*/

#define SYSCFG_CACHE_MODE    	0x00000030	/* (CM) Cache mode */
#define SYSCFG_CACHE_MODE_00 	0x00000000	/* 4Kb SRAM, 4Kb cache */
#define SYSCFG_CACHE_MODE_01 	0x00000010	/* 0Kb SRAM, 8Kb cache */
#define SYSCFG_CACHE_MODE_10 	0x00000020	/* 8Kb SRAM, 0Kb cache */	
#define SYSCFG_CACHE_MODE_11 	0x00000030	/* unused */
#define SYSCFG_CACHE_MASK       0x0000003f	/* Cache configuration mask */

/* alternative names for cache mode */

#define SYSCFG_CACHE_MODE_4KB_CACHE	SYSCFG_CACHE_MODE_00
#define SYSCFG_CACHE_MODE_8KB_CACHE	SYSCFG_CACHE_MODE_01
#define SYSCFG_CACHE_MODE_8KB_SRAM	SYSCFG_CACHE_MODE_10

#ifdef _S3C4530_ 
/*[30:26]Product Identifier (PD_ID) */
#define SYSCFG_PD_KS32C50100 0x04000000 /* 00001 = S3C4510X (KS32C50100) */
#define SYSCFG_PD_S3C4510B   0x64000000 /* 11001 = S3C4510B */
#define SYSCFG_PD_S3C4530X   0x0C000000 /* 00011 = S3C4530X (KS32C50300) */
#define SYSCFG_PD_S3C4530A   0x4C000000 /* 10011 = S3C4530A */
#define SYSCFG_PD_ID         0x7C000000 /* 11111 = PD_ID mask */
#else
#ifdef _KS32C50100_
/*[29:26]Product Identifier (PD_ID) */
#define SYSCFG_PD_KS32C50000 0x00000000 /* 0000 = (KS32C5000) */
#define SYSCFG_PD_KS32C50100 0x04000000 /* 0001 = (KS32C50100) */
#define SYSCFG_PD_ID         0x3C000000 /* 1111 = PD_ID mask */
#endif
#endif							/* _S3C4530_ */

#define CLKCON          (VPint(Base_Addr+0x3000))	

/************************************************************************/
/* CLKCON Clock control register. 					*/
/* 									*/
/* 	 Offset 	= 0x3000					*/
/* 	 Reset Value 	= 0x00000000 					*/
/* 									*/
/*[15:0] Clock Divided Value 						*/
/* 	 If all bits are 0, a non-divided clock is used. Only one bit 	*/ 
/*	 can be set in CLKCON[15:0]. That is, the clock dividing 	*/
/* 	 values is defined as 1,2,4,8,16 ... 				*/ 
/* 	 Internal system clock, fMCLK = fICLK / (CLKCON + 1) 		*/ 
/* 									*/
/*[16]	 ROM bank 5 wait enable 					*/
/* 	 0 = Disable ROM bank 5 wait 					*/
/* 	 1 = Enable  ROM bank 5 wait 					*/
/* 									*/
/*[17]	 ROM bank 5 address/data bus Mux enable 			*/
/* 	 0 = Normal operation 						*/
/* 	 1 = Enable bus multiplexing 					*/
/* 									*/
/*[19:18]Mux bus Address Cycle (tAC) 					*/
/* 	 00 = 1 MCLK 							*/
/*       01 = 2 MCLK 							*/
/* 	 10 = 3 MCLK 							*/
/* 									*/
/*[20]   ROM bank 5 wait 1 cycle delay (S3C4530) 			*/
/*       Wait cycle will check the second cycle after a chip selection  */
/*       signal is activated. 						*/
/* 									*/
/*[21,23,25,27,29] ROM bank 4,3,2,1,0 wait enable (S3C4530) 		*/
/*       Wait cycle will check the next cycle after the each chip 	*/
/*       selection signal is activated. 				*/
/*        [21] = ROM bank 4						*/
/*        [23] = ROM bank 3						*/
/*        [25] = ROM bank 2 						*/
/*        [27] = ROM bank 1 						*/
/*        [29] = ROM bank 0 					        */
/* 									*/
/* [22,24,26,28,30] ROM bank 4,3,2,1,0 wait 1 cycle delay (S3C4530) 	*/
/*       Wait cycle will check the second cycle after the each chip     */
/*       selection signal is activated. 				*/
/*        [22] = ROM bank 4						*/
/*        [24] = ROM bank 3						*/
/*        [26] = ROM bank 2 						*/
/*        [28] = ROM bank 1						*/
/*        [30] = ROM bank 0 						*/
/* 									*/
/*[31]   Test bit 							*/
/* 	 This bit should be always 0.					*/
/* 									*/
/************************************************************************/

#define CLKCON_DIV_MASK        0x0000FFFF /* Clock Divided Value */
#define CLKCON_ROM5_WAIT_EN    0x00010000 /* ROM bank 5 wait enable */
#define CLKCON_ROM5_MUX_EN     0x00020000 /* ROM bank 5 address/data bus Mux enable */
// 
#define CLKCON_ROM5_MUX_TAC    0x000C0000 /* Mux bus Address Cycle (tAC) */
#define CLKCON_ROM5_MUX_TAC_1  0x00000000 /* 00 = 1 MCLK */	
#define CLKCON_ROM5_MUX_TAC_2  0x00040000 /* 01 = 2 MCLK */	
#define CLKCON_ROM5_MUX_TAC_3  0x00080000 /* 10 = 3 MCLK */	
#define CLKCON_ROM5_MUX_TAC_UN 0x000C0000 /* 11 = unused */

#ifdef _S3C4530_
#define CLKCON_ROM5_WAIT_DELAY 0x00100000 /*[20] ROM bank 5 wait 1 cycle delay (S3C4530)*/

#define CLKCON_ROM4_WAIT_EN    0x00200000 /*[21] ROM bank 4 wait enable*/
#define CLKCON_ROM4_WAIT_DELAY 0x00400000 /*[22] ROM bank 4 wait cycle delay */

#define CLKCON_ROM3_WAIT_EN    0x00800000 /*[23] ROM bank 3 wait enable*/
#define CLKCON_ROM3_WAIT_DELAY 0x01000000 /*[24] ROM bank 3 wait cycle delay */

#define CLKCON_ROM2_WAIT_EN    0x02000000 /*[25] ROM bank 2 wait enable*/
#define CLKCON_ROM2_WAIT_DELAY 0x04000000 /*[26] ROM bank 2 wait cycle delay */

#define CLKCON_ROM1_WAIT_EN    0x08000000 /*[27] ROM bank 1 wait enable*/
#define CLKCON_ROM1_WAIT_DELAY 0x10000000 /*[28] ROM bank 1 wait cycle delay */

#define CLKCON_ROM0_WAIT_EN    0x20000000 /*[29] ROM bank 0 wait enable*/
#define CLKCON_ROM0_WAIT_DELAY 0x40000000 /*[30] ROM bank 0 wait cycle delay */
#endif								/* _S3C4530_ */

// 
#define CLKCON_TEST_BIT        0x80000000 /* Test bit */


/* External I/O Access Control Registers */  

#define EXTACON0 	(VPint(Base_Addr+0x3008))	/* External I/O timing register 1 */
#define EXTACON1 	(VPint(Base_Addr+0x300c))	/* External I/O timing register 2 */

/************************************************************************/
/* Chip selection set-up time on nOE (tCOS0, tCOS1, tCOS2, tCOS3)	*/
/* 									*/
/* [0:2]   EXTACON0 tCOS0 						*/
/* [0:2]   EXTACON1 tCOS2 						*/
/* [18:16] EXTACON0 tCOS1 						*/
/* [18:16] EXTACON1 tCOS3 						*/
/* 									*/
/* Address set-up time before nECS (tACS0, tACS1, tACS2, tACS3)		*/ 
/* 									*/
/* [5:3]   EXTACON0 tACS0 						*/
/* [5:3]   EXTACON1 tACS2 						*/
/* [21:19] EXTACON0 tACS1 						*/
/* [21:19] EXTACON1 tACS3 						*/
/* 									*/
/* Chip selection hold time on nOE (tCOH0,tCOH1,tCOH2,tCOH3)		*/
/* 									*/
/* [8:6]   EXTACON0 tCOH0 						*/
/* [8:6]   EXTACON1 tCOH2 						*/
/* [24:22] EXTACON0 tCOH1 						*/
/* [24:22] EXTACON1 tCOH2 						*/
/* 									*/
/* Access cycles (nOE low time (tACC0,tACC1,tACC2,tACC3) 		*/
/* 									*/
/* [11:9]  EXTACON0 tACC0 						*/
/* [11:9]  EXTACON1 tACC2 						*/
/* [27:25] EXTACON0 tACC1 						*/
/* [27:25] EXTACON1 tACC2 						*/
/* 									*/
/* 	   000 = 0 cycle 						*/