dma.c

本source code 為s3c4510的bootloader

/* 
 * Modified by 
 * Dmitriy Cherkashin 
 * [e-mail]
 * 2002
 */

/*************************************************************************/
/*                                                                       */
/* FILE NAME                                      VERSION                */
/*                                                                       */
/*     DMA.c                       KS32C5000, KS32C50100   : version 1.0 */
/*                                                                       */
/* COMPONENT                                                             */
/*                                                                       */
/*                                                                       */
/*                                                                       */
/* DESCRIPTION                                                           */
/*                                                                       */
/*                                                                       */
/* AUTHOR                                                                */
/*                                                                       */
/*      Young Sun KIM, Samsung Electronics, Inc.                         */
/*                                                                       */
/* DATA STRUCTURES                                                       */
/*                                                                       */
/*                                                                       */
/* FUNCTIONS                                                             */
/*                                                                       */
/*      Evalution code for DMA control block                             */
/*                                                                       */
/* DEPENDENCIES                                                          */
/*                                                                       */
/*                                                                       */
/* HISTORY                                                               */
/*                                                                       */
/*         NAME            DATE                    REMARKS               */
/*                                                                       */
/*         in4maker     12-18-1998      timer function updated           */
/*************************************************************************/
#include "ks32c50.h"
#include "evm50100.h"

#define GDMA_DEBUG   0           	/* DEBUG mode */

#define GDMATestSize       0x1000 	/* Default Test Size 4KB */   
U8      GDMATestSrc[GDMATestSize];	/* Default source buffer */
U8      GDMATestDst[GDMATestSize];	/* Default destination buffer */

/* global variable */
volatile U32 Gdma0DoneFlag = 0;   // GDMA Channel 0 Transfer done interrupt flag
volatile U32 Gdma1DoneFlag = 0;   // GDMA Channel 1 Transfer done interrupt flag


//////////////////////////////////////////////////////////////////////////////// 
// GDMA0, GDMA1 Interrupt Service Routines /////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

void  GDMA0isr(void)
{
#if GDMA_DEBUG
 Print("\nTRANSFER MODE IS ");
 switch( (GDMACON0&GDMACON_MODE) ) 
  {
   case GDMACON_MODE_MEMMEM  : Print("\nSOFTWARE."); break;
   case GDMACON_MODE_EXTDREQ : Print("\nEXTDREQ."); break;
   case GDMACON_MODE_U0      : Print("\nUART0."); break;
   case GDMACON_MODE_U1      : Print("\nUART1.");
  }
 GdmaReset(0);
#endif
 Gdma0DoneFlag = 1; 
}

void  GDMA1isr(void)
{
#if GDMA_DEBUG
 Print("\nTRANSFER MODE IS ");
 switch( (GDMACON1&GDMACON_MODE) ) 
  {
   case GDMACON_MODE_MEMMEM  : Print("\nSOFTWARE."); break;
   case GDMACON_MODE_EXTDREQ : Print("\nEXTDREQ."); break;
   case GDMACON_MODE_U0      : Print("\nUART0."); break;
   case GDMACON_MODE_U1      : Print("\nUART1.");
  }
 GdmaReset(1);
#endif
 Gdma1DoneFlag = 1; 
}


//////////////////////////////////////////////////////////////////////////////// 
// GDMA Configuration viewer /////////////////////////////////////////////////// 
//////////////////////////////////////////////////////////////////////////////// 

static void GDMAConfigView(int cn)
{
 U32 gdmacon;			// GDMA channel cn control register
 U32 gdmasrc;			// GDMA channel cn source address register 
 U32 gdmadst;			// GDMA channel cn destination address register 
 U32 gdmacnt;			// GDMA channel cn count register 

 if(cn == 1) 
  { 
// GDMA Channel 1 //////////////////////////////////////////////////////////////
   gdmacon = GDMACON1;			// GDMA 1 Control register
   gdmasrc = GDMASRC1;			// GDMA 1 Source address register 
   gdmadst = GDMADST1;			// GDMA 1 Destination address register 
   gdmacnt = GDMACNT1;			// GDMA 1 Count Register 
  }
 else 
 if(cn == 0)
  {
// GDMA Channel 0 ////////////////////////////////////////////////////////////// 
   gdmacon = GDMACON0;			// GDMA 0 Control Register 
   gdmasrc = GDMASRC0;			// GDMA 0 Source Address Register 
   gdmadst = GDMADST0;			// GDMA 0 Destination Address Register 
   gdmacnt = GDMACNT0;			// GDMA 0 Count Register 
  }
 else
  { 
   return;
  } 

//////////////////////////////////////////////////////////////////////////////// 
// GDMACON ///////////////////////////////////////////////////////////////////// 
//////////////////////////////////////////////////////////////////////////////// 

 Print("\nGDMA%d Control Register...................0x%08x", cn, gdmacon);

// GDMA_RE // [0] Run enable/disable (RE) ////////////////////////////////////// 

 Print("\n[0]     GDMA%d Run enable/disable (RE)....%s", cn,
  ((gdmacon & GDMACON_RE) !=0)  ?
   "1(Enable)"	:
   "0(Disable)"
  );

//////////////////////////////////////////////////////////////////////////////// 
// GDMA_BS // [1] Busy status (BS) /////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

 Print("\n[1]     GDMA%d Busy status (BS)...........%s", cn,
  ((gdmacon & GDMACON_BS) != 0)	? 
   "1(DMA is active)"		:
   "0(DMA is idle)"
  );

//////////////////////////////////////////////////////////////////////////////// 
// [3:2] GDMA mode selection (MODE) ////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

 Print("\n[3:2]   GDMA%d mode selection (MODE)......",cn);
 switch(gdmacon & GDMACON_MODE)
 {
  case GDMACON_MODE_EXTDREQ: Print("01(External DMA Request mode)"); break;
  case GDMACON_MODE_U0     : Print("10(UART0 Mode)"); break;
  case GDMACON_MODE_U1     : Print("11(UART1 Mode)"); break;
  case GDMACON_MODE_MEMMEM : 
  default 		   : 
   Print("00(Memory to Memory)"); 
   break;
 }

//////////////////////////////////////////////////////////////////////////////// 
// [4] Destination address direction (GDMA_DST_DEC) ////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

 Print("\n[4]     GDMA%d Dest. address direction....%s", cn,  
  ((gdmacon & GDMACON_DST_DEC) != 0) ?
   "1(Decrement)"	:
   "0(Increment)"
 ); 


//////////////////////////////////////////////////////////////////////////////// 
// [5] Source address direction (GDMA_SRC_DEC) /////////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

 Print("\n[5]     GDMA%d Source address direction...%s", cn,
  ((gdmacon & GDMACON_SRC_DEC) != 0)	? 
   "1(decrement)"	:
   "0(Increment)"
 );
  
//////////////////////////////////////////////////////////////////////////////// 
// [6] Destination address fix (GDMA_DST_FIX) //////////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

 Print("\n[6]     GDMA%d Destination address fix....%s", cn,
  ((gdmacon & GDMACON_DST_FIX) != 0)	? 
   "1(Not change address)" :
   "0(Increase/Decrease address)"
 );


//////////////////////////////////////////////////////////////////////////////// 
// [7] Source address fix (GDMA_SRC_FIX) ///////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

 Print("\n[7]     GDMA%d Source address fix.........%s", cn,
  ((gdmacon & GDMACON_SRC_FIX) != 0)	? 
   "1(Not change address)" :	
   "0(Increase/Decrease)"
 );

//////////////////////////////////////////////////////////////////////////////// 
// [8] Stop interrupt enable (GDMA_SI) /////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

 Print("\n[8]     GDMA%d Stop interrupt enable(SI)..%s", cn,
  ((gdmacon & GDMACON_SI) != 0)		? 
   "1(Generate stop interrupt)" :
   "0(do not generate stop int)"
 );
  

//////////////////////////////////////////////////////////////////////////////// 
// [9] Four-data burst enable (GDMA_FB) ////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

 Print("\n[9]     GDMA%d Four-data burst enable(FB).%s", cn,
  ((gdmacon & GDMACON_FB) != 0)		?	 
   "1(Enable)"	:
   "0(Disable)"
  );

//////////////////////////////////////////////////////////////////////////////// 
// [10] Transfer direction (for UART0/UART1 only) (GDMA_TD) ////////////////////
//////////////////////////////////////////////////////////////////////////////// 

 Print("\n[10]    GDMA%d Transfer direction.........%s", cn,
  ((gdmacon & GDMACON_TD) == GDMACON_TD_MEMTOU)	?
   "1(Memory to UART0/UART1)"	:
   "0(UART0/UART1 to memory)"
 );

//////////////////////////////////////////////////////////////////////////////// 
// [11] Single/Block mode (GDMA_SB) ////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

 Print("\n[11]    GDMA%d Single/Block mode (SB).....%s", cn,
  ((gdmacon & GDMACON_SB_BLOCK) != 0) 	?
   "1(Block mode)"	:
   "0(Single Mode)"
 );

//////////////////////////////////////////////////////////////////////////////// 
// [13:12] Transfer width (TW) /////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

 Print("\n[13:12] GDMA%d Transfer width (TW)........",cn);
 switch( (gdmacon & GDMACON_TW) )	// Transfer Width 
  {
   case GDMACON_TW_BYTE     : Print("00(byte)");     break;
   case GDMACON_TW_HALFWORD : Print("01(halfword)"); break;
   case GDMACON_TW_WORD     : Print("10(word)");     break;
   default                  : Print("11(unused)");   break;
  }


//////////////////////////////////////////////////////////////////////////////// 
// [14] Continuous mode (GDMA_CM) //////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

 Print("\n[14]    GDMA%d Continuous mode (CM).......%s", cn, 
  ((gdmacon & GDMACON_CM) != 0)	? 	// Continuos Mode  
   "1(Continuous mode)"	:
   "0(Normal operation)"
 );

//////////////////////////////////////////////////////////////////////////////// 
// [15] Demand mode (GDMA_DM) //////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

 Print("\n[15]    GDMA%d Demand mode (DM)...........%s", cn,
  ((gdmacon & GDMACON_DM) != 0)	? 	// Demand Mode 
   "1(Demand mode)"	:
   "0(Normal operation)"
 );

//
 Print("\nGDMASRC%d Source Address Register.........0x%08x", cn, gdmasrc);
 Print("\nGDMADST%d Dest. Address Register..........0x%08x", cn, gdmadst);
 Print("\nGDMACNT%d Transfer Count Register.........0x%08x", cn, gdmacnt);
 Print("\n");
}


//////////////////////////////////////////////////////////////////////////////// 
// Initialize GDMA control register ////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

void GdmaReset(unsigned gdma_channel)
{
 if(gdma_channel == 1) 
  {
// GDMA Channel 1 reset ////////////////////////////////////////////////////////   
   GDMASRC1 = 0;			// GDMA 1 source address 
   GDMADST1 = 0;			// GDMA 1 destination address 
   GDMACNT1 = 0;			// GDMA 1 transfer count register 
   GDMACON1 = 0;			// GDMA 1 control register 
  }
 else 
 if(gdma_channel == 0)
  {
// GDMA Channel 0 reset ////////////////////////////////////////////////////////   
   GDMASRC0 = 0;			// GDMA 0 source address 
   GDMADST0 = 0;			// GDMA 0 destination address 
   GDMACNT0 = 0;			// GDMA 0 transfer count register 
   GDMACON0 = 0;			// GDMA 0 control register 
  }
}


//////////////////////////////////////////////////////////////////////////////// 
// GDMA Registers Read & write test ////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

// print GDMA source address register ////////////////////////////////////////// 
#define PrintGDMASRC(cn)	 			\
 Print("\nGDMASRC%d           [0x%08x] = 0x%08x", 	\
  cn				,			\
 (cn ? &GDMASRC1 : &GDMASRC0)	,			\
 (cn ?  GDMASRC1  : GDMASRC0)  				\
); 

// print GDMA destination address register ///////////////////////////////////// 
#define PrintGDMADST(cn) 				\
 Print("\nGDMADST%d           [0x%08x] = 0x%08x", 	\
  cn				,			\
 (cn ? &GDMADST1 : &GDMADST0)	, 			\
 (cn ?  GDMADST1 :  GDMADST0) 				\
); 

// print GDMA transfer count register ////////////////////////////////////////// 
#define PrintGDMACNT(cn) 				\
 Print("\nGDMACNT%d           [0x%08x] = 0x%08x",	\
  cn				,			\
 (cn ? &GDMACNT1 : &GDMACNT0)	, 			\
 (cn ?  GDMACNT1 :  GDMACNT0)				\
); 

// print GDMA control register ///////////////////////////////////////////////// 
#define PrintGDMACON(cn) 				\
 Print("\nGDMACON%d           [0x%08x] = 0x%08x",  	\
  cn				,			\
 (cn ? &GDMACON1 : &GDMACON0) 	, 			\
 (cn ?  GDMACON1 :  GDMACON0)				\
); 

//////////////////////////////////////////////////////////////////////////////// 
// GDMA Interrupt enable & disable and clear transfer done flag ////////////////
//////////////////////////////////////////////////////////////////////////////// 

void GdmaIntEnable(unsigned gdma_channel)
{
 if(gdma_channel == 1) 
  {
// GDMA channel 1 interrupt enable /////////////////////////////////////////////  
   Gdma1DoneFlag = 0; 			// clear GDMA1 done flag	
   Enable_Int(nGDMA1_INT);		// enable GDMA1 INT  
  }
 else 
 if(gdma_channel == 0)
  {
// GDMA channel 0 interrupt enable /////////////////////////////////////////////
   Gdma0DoneFlag = 0;			// clear GDMA1 done flag   
   Enable_Int(nGDMA0_INT);		// enable GDMA0 INT 
  } 
// 
 Enable_Int(nGLOBAL_INT);		// global interrupt enable 
}


void GdmaIntDisable(unsigned gdma_channel)
{
 if(gdma_channel == 1) 
  {
// disable GDMA channel 1 interrupt ////////////////////////////////////////////   
   Disable_Int(nGDMA1_INT);		// disable GDMA1_INT
   Gdma1DoneFlag = 0;			// clear GDMA1 done flag 
  }
 else 
 if(gdma_channel == 0)
  {
// disable GDMA channel 0 interrupt ////////////////////////////////////////////
   Disable_Int(nGDMA0_INT);		// disable GDMA0_INT 	
   Gdma0DoneFlag = 0; 			// clear GDMA0 done flag 
  }
}

//////////////////////////////////////////////////////////////////////////////// 
// Initialize GDMA Memory with ASCII pattern for test //////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

//
// src   = source size 
// tsize = size in bytes 
// 

static void GdmaMemInit(void *src, void * dst, int tsize)
{
 U8 * srcptr;
 U8 * dstptr;
 int ascii = 48;
 int cnt;

 srcptr = (U8 *) src;
 dstptr = (U8 *) dst;
 cnt = tsize;

 while(cnt--) 
  {
   if(ascii > 123) 
    {
     ascii = 48;
    }

   *srcptr++ = ascii++;
   *dstptr++ = 0;
  }
}

//
// src   = source address 
// dst   = destination address
// tsize = size in bytes
// 

static int GdmaMemComp(void *src, void *dst, int tsize)
{
 U8 * SrcAddr; 
 U8 * DstAddr;
 int  cnt;

 SrcAddr = (U8 *)src;				/* byte pointer to source */
 DstAddr = (U8 *)dst;				/* byte pointer to destination */
 cnt	 = tsize;				/* byte count */

 while(cnt--)
  {
   if ( *DstAddr != *SrcAddr )
    {
     Print("\nMemory Byte Test Error") ;