hdlcmain.c

本source code 為s3c4510的bootloader

 PrintSBIT(ch, "20  DMA Rx memory overflow (RxMOV)", reg, HSTAT_RxMOV,
    "1(overflow Rx buf desc,next ptr == null)",
    "0(Normal operation)"
 );

 Print("\nPress any key to continue"); 
 get_byte(); 

// [22] DMA Tx abort (DTxABT) //////////////////////////////////////////////////
 PrintSBIT(ch, "22  DMA Tx abort (DTxABT)", reg, HSTAT_DTxABT, 
    "1", "0(Normal operation)"
 );

// [23] Rx internal error (RxIERR) /////////////////////////////////////////////
 PrintUBIT(ch, "23  Rx internal error (RxIERR)", reg, HSTAT_RxIERR);

// [24] DMA Rx frame done every received frame (DRxFD) /////////////////////////
 PrintUBIT(ch, "24  DMA Rx frame done every frame", reg, HSTAT_DRxFD);

// [25] DMA Rx null list (DRxNL) ///////////////////////////////////////////////
 PrintUBIT(ch, "25  DMA Rx null list (DRxNL)", reg, HSTAT_DRxNL);

// [26] DMA Rx not owner (DRxNO) ///////////////////////////////////////////////
 PrintSBIT(ch, "26  DMA Rx not owner (DRxNO)", reg, HSTAT_DRxNO,
    "1(CPU has the ownership)", "0(DMA has the ownership)"
 );

// [27] DMA Tx frame done (DTxFD) //////////////////////////////////////////////
 PrintUBIT(ch, "27  DMA Tx frame done (DTxFD)", reg, HSTAT_DTxFD);

// [28] DMA Tx null list (DTxNL) ///////////////////////////////////////////////
 PrintUBIT(ch, "28  DMA Tx null list (DTxNL)", reg, HSTAT_DTxNL);

// [29] DMA Tx not owner (DTxNO) ///////////////////////////////////////////////
 PrintSBIT(ch, "29  DMA Tx not owner (DTxNO)", reg, HSTAT_DTxNO, 
    "1(CPU has the ownership)", "0(DMA has the ownership)"
 );

// [30] DPLL one clock missing (DPLLOM) ////////////////////////////////////////
 PrintUBIT(ch, "30  DPLL one clock missing (DPLLOM)", reg, HSTAT_DPLLOM);
// [31] DPLL two clock missing (DPLLTM) ////////////////////////////////////////
 PrintUBIT(ch, "31  DPLL two clock missing (DPLLTM)", reg, HSTAT_DPLLTM);
}

////////////////////////////////////////////////////////////////////////////////
// HDLC Interrupt Enable Register (HINTEN) /////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

static void PrintHINTB(char * str, U32 val, U32 mask)
{
 Print("\n%s%s", 
   str ,
   ((val & mask) != 0) ?
    "1(enabled)" :
    "0(disabled)"
  );
}

static void PrintHINTEN(int cn)
{
 U32 hi;				// 
 U8 ch;					// channel letter 
 if(cn == 0)
  {
   ch = 'A';				// channel A 
   hi = HINTENA;			// 
  } 
 else
 if(cn == 1)
  {
   ch = 'B';				// channel B 
   hi = HINTENB;
  }

 Print("\nHINTEN%c HDLC%c Int enable register.", ch, ch);

// [4] Tx frame complete interrupt enable //////////////////////////////////////
 PrintHINTB("4  Tx frame complete Int (TxFCIE).........",hi,HINTEN_TxFCIE);
// [5] Tx FIFO available to write interrupt enable /////////////////////////////
 PrintHINTB("5  Tx FIFO available to write Int(TxFAIE).",hi,HINTEN_TxFAIE);
// [7] CTS transition has occurred interrupt enable ////////////////////////////
 PrintHINTB("7  CTS transition Int (TxSCTSIE)..........",hi,HINTEN_TxSCTSIE);
// [8] Tx underrun has occurred interrupt enable ///////////////////////////////
 PrintHINTB("8  Tx underrun Int (TxUIE)................",hi,HINTEN_TxUIE);
// [9] Rx FIFO available to read interrupt enable //////////////////////////////
 PrintHINTB("9  Rx FIFO available to read Int (RxFAIE).",hi,HINTEN_RxFAIE);

#ifdef _S3C4530_ 
 PrintHINTB("10 Tx Fframe good Int (TxFGIE)............",hi,HINTEN_TxFGIE);
#endif 								/* _S3C4530_ */ 

// [11]Rx flag detected interrupt enable ///////////////////////////////////////
 PrintHINTB("11 Rx flag detected Int (RxFDIE)..........",hi,HINTEN_RxFDIE);
// [13]DCD transition interrupt enable /////////////////////////////////////////
 PrintHINTB("13 DCD transition Int (RxSDCDIE)..........",hi,HINTEN_RxSDCDIE);
// [14]Rx frame valid interrupt enable /////////////////////////////////////////
 PrintHINTB("14 Rx frame valid Int (RxFVIE)............",hi,HINTEN_RxFVIE);
// [15]Idle detected interrupt enable //////////////////////////////////////////
 PrintHINTB("15 Idle detected Int (RxIDLEIE)...........",hi,HINTEN_RxIDLEIE);
// [16]Abort detected interrupt enable /////////////////////////////////////////
 PrintHINTB("16 Abort detected Int (RxABTIE)...........",hi,HINTEN_RxABTIE);
// [17]CRC error frame interrupt enable ////////////////////////////////////////
 PrintHINTB("17 CRC error frame Int (RxCRCEIE).........",hi,HINTEN_RxCRCEIE); 
// [18]Non-octet aligned frame interrupt enable ////////////////////////////////
 PrintHINTB("18 Non-octet aligned frame Int (RxNOIE)...",hi,HINTEN_RxNOIE);
// [19]Rx overrun interrupt enable /////////////////////////////////////////////
 PrintHINTB("19 Rx overrun Int (RxOVIE)................",hi,HINTEN_RxOVIE);
// [20]Rx memory overflow interrupt enable /////////////////////////////////////
 PrintHINTB("20 Rx memory overflow Int (RxMOVIE).......",hi,HINTEN_RxMOVIE);

 Print("\nPress any key to continue"); 
 get_byte(); 


// [22]DMA Tx abort interrupt enable ///////////////////////////////////////////
 PrintHINTB("22 DMA Tx abort Int (DTxABTIE)............",hi,HINTEN_DTxABTIE);
// [23]Rx internal error interrupt enable //////////////////////////////////////
 PrintHINTB("23 Rx internal error Int (RxIERRIE).......",hi,HINTEN_RxIERRIE);
// [24]DMA Rx frame done interrupt enable //////////////////////////////////////
 PrintHINTB("24 DMA Rx frame done Int (DRxFDIE)........",hi,HINTEN_DRxFDIE);
// [25]DMA Rx null list interrupt enable ///////////////////////////////////////
 PrintHINTB("25 DMA Rx null list Int (DRxNLIE).........",hi,HINTEN_DRxNLIE);
// [26]DMA Rx not owner interrupt enable ///////////////////////////////////////
 PrintHINTB("26 DMA Rx not owner Int (DRxNOIE).........",hi,HINTEN_DRxNOIE);
// [27]DMA Tx frame done every transmitted frame interrupt enable //////////////
 PrintHINTB("27 DMA Tx frame done every frame(DTxFDIE).",hi,HINTEN_DTxFDIE);
// [28]DMA Tx null list interrupt enable ///////////////////////////////////////
 PrintHINTB("28 DMA Tx null list Int (DTxNLIE).........",hi,HINTEN_DTxNLIE);
// [29]DMA Tx not owner interrupt enable ///////////////////////////////////////
 PrintHINTB("29 DMA Tx not owner Int (DTxNOIE).........",hi,HINTEN_DTxNOIE);
// [30]DPLL one clock missing interrupt enable /////////////////////////////////
 PrintHINTB("30 DPLL one clock missing Int( DPLLOMIE)..",hi,HINTEN_DPLLOMIE);
// [31]DPLL two clocks missing interrupt enable ////////////////////////////////
 PrintHINTB("31 DPLL two clocks missing Int (DPLLTMIE).",hi,HINTEN_DPLLTMIE);
}


static void PrintHBRGTC(int cn)
{
 U32 hmode;
 U32 hbrgtc;				// 
 U32 cnt2;
 U32 cnt1;
 U32 cnt0;
 U8 ch;					// channel letter 
 if(cn == 0)
  {
   ch = 'A';				// channel A 
   hmode  = HMODEA;			// HDLC A Mode register   
   hbrgtc = HBRGTCA;			// HDLC A BRG register 
  } 
 else
 if(cn == 1)
  {
   ch = 'B';				// channel B 
   hmode  = HMODEB;			// HDLC N Mode register 
   hbrgtc = HBRGTCB;			// HDLC B BRG register 
  }

// 
 Print("\nHBRGTC%c HDLC%c.", ch, ch);

// 
 cnt2 = (hbrgtc & 0x3); 
 Print("\n1:0  Time constant value for CNT2....");
 switch( cnt2 )
  {
   case 0 : Print("00(divide by 1)");  cnt2 =  1; break;	// 
   case 1 : Print("01(divide by 16)"); cnt2 = 16; break;	// 
   case 2 : Print("10(divide by 32)"); cnt2 = 32; break;	// 
   default:
    break; 
  }

 Print("\n3:2  Time constant value for CNT1....");
 cnt1 = (hbrgtc >> 2) & 0x3;
 switch(cnt1)
  {
   case 0 : Print("00(divide by 1)");  cnt1 =  1; break;
   case 1 : Print("01(divide by 16)"); cnt1 = 16; break;
   default:
    break; 
  }

 cnt0 = ((hbrgtc >> 4) & 0xFFF);
 Print("\n15:4 Time constant value for CNT0....%d", cnt0 );

 if( (hmode & HMODE_BRGCLK_MCLK2) != 0 )
  {
   Print("\nBRGOUT1=MCLK2/(CNT0+1)/(16**CNT1)....%d", MCLK2/(cnt0+1)/cnt1);
   Print("\nBRGOUT2=BRGOUT1/CNT2.................%d", MCLK2/(cnt0+1)/cnt1/cnt2);
  }
}

static void PrintHSAR(char * nam, U32 val)
{
 Print("\n%s = 0x%08x", nam, val);
 Print("\n31:24 First address byte.......0x%02x", (val >> 24) & 0xFF);
 Print("\n23:16 Second address byte......0x%02x", (val >> 16) & 0xFF);
 Print("\n15:8  Third address byte.......0x%02x", (val >>  8) & 0xFF);
 Print("\n7:0   Fourth address byte......0x%02x", (val)       & 0xFF);
}


#ifdef _S3C4530_
// Transparent Contgrol Regs
static void PrintTCON(int ch)
{
 int cn, cnt;				// channel number, count
 U32 reg[2];				// reg content 
 reg[0] = TCONA;			// Channel A transparent control register 
 reg[1] = TCONB;			// Chan B Transparent Control Reg
  
 Print("\nTransparent Contgrol Regs TCON");
 if(ch >= 0) 
  {
   cnt = ch + 1;  
   Print(" 0x%08x", reg[ch] );
  }  
 else 
  {
   cnt = -ch;
   for(cn = 0; cn < cnt; ++cn) 
    {
     Print(" 0x%08x", reg[cn] );
    }
  }

 { 
  ABIT ds_bt[] = {
    {"00(D4)", TCON_DS_D4},
    {"01(D3)", TCON_DS_D3},
    {"10(D2)", TCON_DS_D2},
    {"11(D1)", TCON_DS_D1},
    {0, 0}
  };
  
  PrintABIT(ch, "1:0 Data Sampling (DS)", reg, TCON_DS, ds_bt); 
 }

  PrintSBIT(ch, "4   RTS Pin Low", reg, TCON_RTS, "1(Low)", "0(High)");
}
#endif								/* _S3C4530_ */

////////////////////////////////////////////////////////////////////////////////
// view HDLC registers /////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////


void HdlcRegView(void)
{
 while(1)
  {
   U8 it;
   Print("\n\nHDLC Registers");
   Print("\n                                              A       B");
   Print("\n[M] HMODE     (Mode register)              %08x %08x",HMODEA    , HMODEB);
   Print("\n[C] HCON      (Control register)           %08x %08x",HCONA     , HCONB);
   Print("\n[S] HSTAT     (Status Register)            %08x %08x",HSTATA    , HSTATB); 
   Print("\n[I] HINTEN    (Interrupt Enable)           %08x %08x",HINTENA   , HINTENB); 
   Print("\n[B] HBRGTC    (BRG Time Constant Register) %08x %08x",HBRGTCA   , HBRGTCB);
   Print("\n[0] HSAR0     (HDLC station address 0)     %08x %08x",HSAR0A    , HSAR0B);
   Print("\n[1] HSAR1     (HDLC station address 1)     %08x %08x",HSAR1A    , HSAR1B);
   Print("\n[2] HSAR2     (HDLC station address 2)     %08x %08x",HSAR2A    , HSAR2B);
   Print("\n[3] HSAR3     (HDLC station address 3)     %08x %08x",HSAR3A    , HSAR3B);
   Print("\n[A] HMASK     (address mask register)      %08x %08x",HMASKA    , HMASKB);
   Print("\n    HDMATXPTR (Tx Buffer Descr. Pointer)   %08x %08x",HDMATXPTRA, HDMATXPTRB); 
   Print("\n    HDMARXPTR (Rx Buffer Descr. Pointer)   %08x %08x",HDMARXPTRA, HDMARXPTRB); 
   Print("\n    HMFLR     (Maximum Frame Length)       %08x %08x",HMFLRA    , HMFLRB);
   Print("\n    HRBSR     (DMA Receive Buffer Size)    %08x %08x",HRBSRA    , HRBSRB);
   Print("\n    HPRMB     (DMA Preamble Register)      %08x %08x",HPRMBA    , HPRMBB);

#ifdef _S3C4530_
   if(is_s3c4530(syscfg_pd_id)) 
   { 
     Print("\n    HSYNC     (HDLC Sync Regster)          %08x %08x",HSYNCA    , HSYNCB);
     Print("\n[T] TCON      (Transparent Control reg)    %08x %08x",TCONA     , TCONB);
     Print("\n    TSACFG    (TSA Configuration reg)      %08x"     ,TSACFG);
     Print("\n    TSASLOT   (TSA A&B Time Slot reg)      %08x %08x",TSAACFG   , TSABCFG);
   }
#endif								/* _S3C4530_ */

   Print("\n[Q] Quit");
   Print("\nSelect Test Item : "); 
   it = get_upper();   

   switch(it)
    {
     case 'M' : 
// HDLC Mode registers /////////////////////////////////////////////////////////
      PrintHMODE(0);			// Print HMODEA register 
      PrintHMODE(1);			// Print HMODEB register 
      break;

     case 'C' : 
// HDLC Control registers //////////////////////////////////////////////////////
      PrintHCON(0);			// HCONA   
      Print("\nPress any key to continue"); 
      get_byte(); 
      PrintHCON(1);			// HCONB
      break;

     case 'S' : 
// HDLC Status registers /////////////////////////////////////////////////////// 
      PrintHSTAT(0);			// HSTATA   
      Print("\nPress any key to continue"); 
      get_byte(); 
      PrintHSTAT(1);			// HSTATB
      break;

     case 'I' : 
// 
      PrintHINTEN(0); 			// HINTENA
      Print("\nPress any key to continue"); 
      get_byte(); 
      PrintHINTEN(1); 			// HINTENB
      break;

     case 'B' : 
      PrintHBRGTC(0); 			// HBRGTCA 
      PrintHBRGTC(1); 			// HBRGTCB
      break;

     case '0' : 
// HDLC station address 0 //////////////////////////////////////////////////////
      PrintHSAR("HSAR0A", HSAR0A);	
      PrintHSAR("HSAR0B", HSAR0B);
      break;

     case '1' : 
// HDLC station address 1 //////////////////////////////////////////////////////
      PrintHSAR("HSAR1A", HSAR1A);	
      PrintHSAR("HSAR1B", HSAR1B);
      break;

     case '2' :
// HDLC station address 2 //////////////////////////////////////////////////////
      PrintHSAR("HSAR2A", HSAR2A);	
      PrintHSAR("HSAR2B", HSAR2B);
      break;

     case '3' :
// HDLC station address 3 //////////////////////////////////////////////////////
      PrintHSAR("HSAR3A", HSAR3A);	
      PrintHSAR("HSAR3B", HSAR3B);
      break;

     case 'A' :
// HDLC address mask register //////////////////////////////////////////////////
      PrintHSAR("HMASKA", HMASKA);	
      PrintHSAR("HMASKB", HMASKB);
      break; 
#ifdef _S3C4530_
     case 'T' : 
// Transparent Contgrol Regs
       if(is_s3c4530(syscfg_pd_id)) { 
         PrintTCON(-2); 
       }
       break;	
#endif								/* _S3C4530_ */ 
     case 'Q' : return;
     default  : 
      break;
    }

   Print("\nPress any key to continue"); 
   it = get_byte();
   if(it == 'Q')
    {
     return;
    } 
  }
} 

////////////////////////////////////////////////////////////////////////////////
// HDLC Reset Test /////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

void HdlcResetTest (void)
{
 U8 cn; 
 U8 clet; 
 U8 csel;
 U8 it;
 U8 warn;

 cn = 0;
 clet = 'A';
 csel = 'B';
 do 
  {
   Print("\nHDLC Reset");
   Print("\n[%c] HDLC %c Select"     , csel, csel);// Select HDLC Channel 
   Print("\n[T] HDLC %c Tx Reset"    , clet );	 
   Print("\n[R] HDLC %c Rx Reset"    , clet );
   Print("\n[D] HDLC %c DMA Tx Reset", clet );
   Print("\n[E] HDLC %c DMA Rx Reset", clet );
   Print("\n[I] HDLC Initialize");
   Print("\n[Q] Quit HDLC Reset Test");
   Print("\nSelect Test Item : "); 
   it = get_upper();
	
   warn = 1;
   switch(it)
    {
     case 'A' :
// select HDLC channel A /////////////////////////////////////////////////////// 
      Print("\nHDLC Channel A selected."); 
      cn   =  0;
      clet = 'A';
      csel = 'B';
      warn = 0;				// no warning 
      break;

     case 'B' :
// Select HDLC Chennel B /////////////////////////////////////////////////////// 
      Print("\nHDLC Channel B selected."); 
      cn =  1;
      clet = 'B';
      csel = 'A';
      break;
     
     case 'T' : 
// Reset Tx for selected HDLC channel ////////////////////////////////////////// 
      Print("\nHDLC Channel %c Tx reseted.",clet); 
      HCON(cn) |= HCON_TxRS;
      break;

     case 'R' : 
// Reset Rx for selected HDLC channel ////////////////////////////////////////// 
      Print("\nHDLC Channel %c Rx reseted.",clet); 
      HCON(cn) |= HCON_RxRS;
      break;

     case 'D' : 
// Reset DMA Tx for selected channel /////////////////////////////////////////// 
      Print("\nHDLC Channel %c DMA Tx reseted.",clet); 
      HCON(cn) |= HCON_DTxRS;
      break;	

     case 'E' : 
// Reset DMA Rx for selected channel /////////////////////////////////////////// 
      Print("\nHDLC Channel %c DMA Rx reseted.",clet); 
      HCON(cn) |= HCON_DRxRS;
      break;

     case 'I' : 
      HDLC_Init();
      warn = 0;				// no warning message
      break;

     case 'Q' : 
      return;

     default  : 
      Print("\nInvalid Test Item Selected"); 
      warn = 0;				// no warning message
      break;
    }

// 
   if(warn == 1)
    {
     Print("\nAfter Reset Command HDLC registers are changed."); 
     Print("\nSelect HDLC Initialize to set correct values of HDLC registers"); 
    }

   Print("\nPress any key to Continue HDLC Test") ; 
   it = get_byte();
  } 
 while(it != 'Q' && it != 'q');
}

////////////////////////////////////////////////////////////////////////////////
// HDLC Loopback Function //////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////