hdlcmain.c

本source code 為s3c4510的bootloader

/***********************************************************************/
/*                                                                     */
/*   MODULE:  BDTest/hdlc.c                                            */
/*   DATE:    98/12/10                                                 */
/*   PURPOSE: hdlc(high level data link control) function define.      */
/*                                                                     */
/*---------------------------------------------------------------------*/
/*      Copyright (C) 1998 Samsung Electronics.                        */
/*                                                                     */
/*      programmed by jwCHOI & such                                    */
/*                                                                     */
/***********************************************************************/

/* 			*/
/* Modified by 		*/
/* Dmitriy Cherkashin 	*/
/* [e-mail]	*/
/* 2002			*/
/*			*/

#include "ks32c50.h"
#include "evm50100.h"

//#define HDLC_RESET			

U32 gHdlcBaudRate = 1000000;

////////////////////////////////////////////////////////////////////////////////
// set HDLC baud rate //////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

static void HdlcSetBrg(void)
{
 U32 val;
 Disable_Int(nGLOBAL_INT); 			// enable global interrupt
 Print("\nInput Baud Rate (%d)",gHdlcBaudRate);	// print current baud rate
 val = get_number(10, 16);			// read length from console 
 if(val > 0) { gHdlcBaudRate = val; }
 Print("\nHDLC Baud Rate   %d", gHdlcBaudRate);	// print HDLC baud rate
 HDLC_Init();					// init HDLC controller	
 Enable_Int(nGLOBAL_INT); 			// enable global interrupt
}

////////////////////////////////////////////////////////////////////////////////
// Print HDLC Mode Register (HMODE) ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

static void PrintHMODE(int ch)
{
 U32 reg[2];				
 reg[0] = HMODEA;			// HDLCA mode register
 reg[1] = HMODEB;			// HDLCB mode register

 if(ch >= 0)
  {
   Print("\nHMODE%c HDLC%c Mode register 0x%08x", 'A'+ch, 'A'+ch, reg[ch]);
  }
 else 
  {
   Print("\nHMODE A=0x%08x B=0x%08x", reg[0], reg[1] );
  }

// [0] 	   Multi-Frame in HTxFIFO //////////////////////////////////////////////
 PrintSBIT(ch, "0     Multi-Frame in HTxFIFO", reg, HMODE_MFinFIFO, 
  "1(Multiple frame in FIFO)", "0(Single frame in FIFO)"
 );

#ifdef _S3C4530_
 if(is_s3c4530(syscfg_pd_id)) 
  {
   PrintUBIT(ch, "2     Rx clock inversion(RXCINV)", reg, HMODE_RXCINV);
   PrintUBIT(ch, "3     Tx clock inversion(TXCINV)", reg, HMODE_TXCINV);
  }
#endif 								/* _S3C4530_ */

// [4] Rx Little-Endian mode (RxLittle) ////////////////////////////////////////
 PrintSBIT(ch, "4     Rx Little-Endian mode (RxLittle)", reg, HMODE_RxLittle,
   "1(Little)", "0(Big-endian)"
 );

// [5] Tx Little-Endian mode (TxLittle) ////////////////////////////////////////
 PrintSBIT(ch, "5     Tx Little-Endian mode (TxLittle)",    reg, HMODE_TxLittle, 
   "1(Little)", "0(Big-endian)"
 );

#ifdef _S3C4530_ 
 if(is_s3c4530(syscfg_pd_id))
  {
   PrintUBIT(ch, "6     Rx Transparent mode (RxTRANS)", reg, HMODE_RxTRANS);
   PrintUBIT(ch, "7     Tx Transparent mode (TxTRANS)", reg, HMODE_TxTRANS);
  }
#endif 								/* _S3C4530_ */

 {
// [10:8]  Tx preamble length (TxPL) ///////////////////////////////////////////
  ABIT tpl_bt[] = {
    {"000(1 byte)" , HMODE_TxPL1},	//
    {"001(2 bytes)", HMODE_TxPL2},	//
    {"010(3 bytes)", HMODE_TxPL3},	//
    {"011(4 bytes)", HMODE_TxPL4},	//
    {"100(5 bytes)", HMODE_TxPL5},	//
    {"101(6 bytes)", HMODE_TxPL6},	//
    {"110(7 bytes)", HMODE_TxPL7},	//
    {"111(8 bytes)", HMODE_TxPL8},	//
    {0, 0}
  };  
  PrintABIT(ch, "10:8  Tx preamble length (TxPL)", reg, HMODE_TxPL8, tpl_bt);
 }

 {
// [14:12] Data formats (DF) ///////////////////////////////////////////////////
  ABIT df_bt[] = {
    {"000(NRZ)"       , HMODE_DF_NRZ	  },  
    {"001(NRZI)"      , HMODE_DF_NRZI	  },  
    {"010(FM0)"       , HMODE_DF_FM0	  },  
    {"011(FM1)"       , HMODE_DF_FM1	  },  
    {"100(Manchester)", HMODE_DF_Manchester}, 
    { 0, 0} 
  };

  PrintABIT(ch, "14:12 Data formats (DF)", reg, HMODE_DF, df_bt);
 }

// [18:16] DPLL clock select (DPLLCLK) /////////////////////////////////////////
 {
   ABIT dpll_bt[] = {
     {"000(TXC)"    , HMODE_DPLLCLK_TXC    },
     {"001(RXC)"    , HMODE_DPLLCLK_RXC    },
     {"010(MCLK)"   , HMODE_DPLLCLK_MCLK   },
     {"011(BRGOUT1)", HMODE_DPLLCLK_BRGOUT1},
     {"100(BRGOUT2)", HMODE_DPLLCLK_BRGOUT2},
     { 0, 0}
   };  
  PrintABIT(ch, "18:16 DPLL clock select (DPLLCLK)", reg, HMODE_DPLLCLK, dpll_bt );
 }

// [19]    BRG clock select (BRGCLK) ///////////////////////////////////////////
 PrintSBIT(ch, "19    BRG clock select (BRGCLK)", reg, HMODE_BRGCLK_MCLK2, 
   "1(MCLK2)", "0(RXC)"
 );
  
 {
// [22:20] Tx clock select (TxCLK) /////////////////////////////////////////////
   ABIT txcs_bt[] = {
     {"000(TXC)"    , HMODE_TxCLK_TXC}, 
     {"001(RXC)"    , HMODE_TxCLK_RXC},
     {"010(DPLLOUTT)",HMODE_TxCLK_DPLLOUTT},
     {"011(BRGOUT1)", HMODE_TxCLK_BRGOUT1},
     {"100(BRGOUT2)", HMODE_TxCLK_BRGOUT2},
     {0, 0}
   };  
  PrintABIT(ch, "22:20 Tx clock select (TxCLK)", reg,HMODE_TxCLK, txcs_bt );
 }

// [26:24] Rx clock select (RxCLK) /////////////////////////////////////////////
 {
   ABIT rxcs_bt[] = {
     {"000(TXC)"    , HMODE_RxCLK_TXC},
     {"001(RXC)"    , HMODE_RxCLK_RXC},
     {"010(DPLLOUTR)",HMODE_RxCLK_DPLLOUTR},
     {"011(BRGOUT1)", HMODE_RxCLK_BRGOUT1},
     {"100(BRGOUT2)", HMODE_RxCLK_BRGOUT2},
     { 0, 0}
   };  
   PrintABIT(ch, "26:24 Rx clock select (RxCLK)", reg, HMODE_RxCLK, rxcs_bt);
 }

// [30:28] TXC output pin select (TXCOPS) //////////////////////////////////////
 {
  ABIT txco_bt[] =  {
    {"000(TxCLK)"   , HMODE_TXCOPS_TxCLK   },
    {"001(RxCLK)"   , HMODE_TXCOPS_RxCLK   },
    {"010(BRGOUT1)" , HMODE_TXCOPS_BRGOUT1 },
    {"011(BRGOUT2)" , HMODE_TXCOPS_BRGOUT2 },
    {"100(DPLLOUTT)", HMODE_TXCOPS_DPLLOUTT},
    {"101(DPLLOUTR)", HMODE_TXCOPS_DPLLOUTR},
    { 0, 0}
  };
  PrintABIT(ch, "30:28 TXC output pin select (TXCOPS)", reg, HMODE_TXCOPS, txco_bt);
 }
}

////////////////////////////////////////////////////////////////////////////////
// Print HDLC control register /////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

static void PrintHCON(int ch)
{
 U32 reg[2];				// HCONA or HCONB
 reg[0] = HCONA;			// HCONA 
 reg[1] = HCONB;			// HCONB 

 if(ch >= 0) 
  {
   Print("\nHCON%c HDLC%c Control register.", 'A'+ch, 'A'+ch);
  }
 else
  {
   Print("\nHCON A&B HDLC Control regs A=0x%08x B=0x%08x", reg[0], reg[1]);
  }  

////////////////////////////////////////////////////////////////////////////////	
// HDLC control register (HCON) ////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////	

// [0] Tx reset (TxRS) /////////////////////////////////////////////////////////
 PrintSBIT(ch, "0     Tx reset (TxRS)",	reg, HCON_TxRS, 
   "1(TxFIFO & Tx block reset)", "0(Normal operation)"
 );

// [1] Rx reset (RxRS) /////////////////////////////////////////////////////////
 PrintSBIT(ch, "1     Rx reset (RxRS)",	reg, HCON_RxRS, 
   "1(RxFIFO and Rx block reset)", "0(Normal operation)"
 );

// [2] DMA Tx reset (DTxRS) ////////////////////////////////////////////////////
 PrintSBIT(ch, "2     DMA Tx reset (DTxRS)", reg, HCON_DTxRS, 
   "1(DMA Tx reset)", "0(Normal operation)"
 );

// [3] DMA Rx reset (DRxRS) ////////////////////////////////////////////////////
 PrintSBIT(ch, "3     DMA Rx reset (DRxRS)", reg, HCON_DRxRS, 
   "1(DMA Rx block is reset)", "0(Normal operation)"
 );

// [4] Tx enable (TxEN) ////////////////////////////////////////////////////////
 PrintSBIT(ch, "4     Tx enable (TxEN)", reg, HCON_TxEN, 
   "1(Tx enabled)", "0(Tx disabled)"
 );

// [5] Rx enable (RxEN) ////////////////////////////////////////////////////////
 PrintSBIT(ch, "5     Rx enable (RxEN)", reg, HCON_RxEN, 
   "1(Rx enabled)", "0(Rx disabled)"
 );

// [6] DMA Tx enable (DTxEN) ///////////////////////////////////////////////////
 PrintSBIT(ch, "6     DMA Tx enable (DTxEN)", reg, HCON_DTxEN, 
   "1(DMA Tx enabled)", "0(DMA Tx disabled"
 );

// [7] DMA Rx enable (DRxEN) ///////////////////////////////////////////////////
 PrintSBIT(ch, "7     DMA Rx enable (DRxEN)", reg, HCON_DRxEN, 
   "1(DMA Rx enabled)", "0(DMA Rx disabled)"
 );

// [8] DPLL enable (DPLLEN) ////////////////////////////////////////////////////
 PrintSBIT(ch, "8     DPLL enable (DPLLEN)", reg, HCON_DPLLEN,
   "1(Enable)", "0(Disable)"
 );

// [9] BRG enable (BRGEN) //////////////////////////////////////////////////////

 PrintSBIT(ch, "9     BRG enable (BRGEN)", reg, HCON_BRGEN,
   "1(BRG counter is enabled)", "0(BRG counter is inhibited)"
 );

// [10]    Tx 4 word mode (Tx4WD) //////////////////////////////////////////////
 PrintSBIT(ch, "10    Tx 4 word mode (Tx4WD)", reg, HCON_Tx4WD,
   "1(4-word mode selected)", "0(1-word mode selected)"
 );

// [11]    Rx 4 word mode (Rx4WD) //////////////////////////////////////////////
 PrintSBIT(ch, "11    Rx 4 word mode (Rx4WD)", reg, HCON_Rx4WD, 
   "1(4-word mode selected)", "0(1-word mode selected)"
 );

// [13:12] Rx widget alignment (RxWA) //////////////////////////////////////////
 {
   ABIT wa_bt[] = {
     {"00(No Invalid bytes)", HCON_RxWA0},
     {"01(1 invalid byte)"  , HCON_RxWA1},
     {"10(2 invalid bytes)" , HCON_RxWA2},
     {"11(3 invalid bytes)" , HCON_RxWA3},
     { 0, 0} 
   };
  PrintABIT(ch, "13:12 Rx widget alignment (RxWA)", reg, HCON_WIDGETMASK, wa_bt);
 }

// [14] DMA Tx stop or skip (DTxSTSK) //////////////////////////////////////////
 PrintSBIT(ch, "14    DMA Tx stop or skip (DTxSTSK)", reg, HCON_DTxSTSK,
   "1(DMA Tx stops)", "0(DMA Tx skips)"
 );

// [15] DMA Rx stop or skip (DRxSTSK) //////////////////////////////////////////
 PrintSBIT(ch, "15    DMA Rx stop or skip (DRxSTSK)", reg, HCON_DRxSTSK,
   "1(DMA Rx stops)", "0(DMA Rx skips)"
 );

// [16] DMA Rx memory address decrement (DRxMADEC) /////////////////////////////
 PrintSBIT(ch, "16    DMA Rx memory address decrement",reg,HCON_DRxMADEC,
   "1(Address is decremented)", "0(Address is incremented)"
 );

// [17] Tx flag idle (TxFLAG) //////////////////////////////////////////////////
 PrintSBIT(ch, "17    Tx flag idle (TxFLAG)", reg, HCON_TxFLAG, 
   "1(time fill mode)", "0(mark idle mode)"
 );

// [18] Tx single flag (TxSFLAG) ///////////////////////////////////////////////
 PrintSBIT(ch, "18    Tx single flag (TxSFLAG)", reg, HCON_TxSFLAG, 
   "1(Single flag mode)", "0(Double flag mode)"
 );

// [19] Tx loop-back mode (TxLOOP) /////////////////////////////////////////////
 PrintSBIT(ch, "19    Tx loop-back mode (TxLOOP)", reg, HCON_TxLOOP, 
   "1(loop-back)", "0(Normal operation)"
 );

// [20] Rx echo mode (RxECHO) //////////////////////////////////////////////////
 PrintSBIT(ch, "20    Rx echo mode (RxECHO)", reg, HCON_RxECHO, 
   "1(enabled)", "0(disabled)"
 );

 Print("\nPress any key to continue"); 
 get_byte(); 

// [21] Tx abort extension (TxABTEXT) //////////////////////////////////////////

 PrintSBIT(ch, "21    Tx abort extension (TxABTEXT)",  reg, HCON_TxABTEXT,
   "1(At least 16 consecutive 1s are Tx)",
   "0(At least consecutive eight 1s are Tx"
 );

// [22] Tx abort (TxABT) ///////////////////////////////////////////////////////
 PrintSBIT(ch, "22    Tx abort (TxABT)", reg, HCON_TxABT,
   "1(Tx abort)", "0(Normal)"
 );

// [23] Tx preamble (TxPRMB) ///////////////////////////////////////////////////
 PrintSBIT(ch, "23    Tx preamble (TxPRMB)", reg, HCON_TxPRMB,
   "1(Tx the content of HPRMB)", "0(mark idle or time fill pattern"
 );

// [24] Tx data terminal ready (TxDTR) /////////////////////////////////////////
 PrintSBIT(ch, "24    Tx data terminal ready (TxDTR)", reg, HCON_TxDTR,
   "1(nDTR goes low level)", "0(nDTR goes high level)"
 );

// [25] Rx frame discontinue (RxDISCON) ////////////////////////////////////////
 PrintSBIT(ch, "25    Rx frame discontinue (RxDISCON)", reg, HCON_RxDISCON, 
   "1(Ignore currently Rx frame)", "0(Normal)"
 ); 

// [26] Tx no CRC (TxNOCRC) ////////////////////////////////////////////////////
 PrintSBIT(ch, "26    Tx no CRC (TxNOCRC)", reg, HCON_TxNOCRC,
   "1(CRC is not appended by hardware)", "0(Disable)"
 );

// [27] Rx no CRC (RxNOCRC) ////////////////////////////////////////////////////
 PrintSBIT(ch, "27    Rx no CRC (RxNOCRC)", reg, HCON_RxNoCRC, 
   "1(Receiver does not check CRC)", "0(Disable)"
 );

// [28] Auto enable (AutoEN) ///////////////////////////////////////////////////
 PrintSBIT(ch, "28    Auto enable (AutoEN)", reg, HCON_AutoEN, 
   "1(enabled)", "0(disabled)"
 );

#ifdef _S3C4530_
 if(is_s3c4530(syscfg_pd_id))
  { 
   PrintUBIT(ch, "29    Transparent Rx stop",      reg, HCON_TRxSTOP);
   PrintUBIT(ch, "30    Transmit reverse (TxREV)", reg, HCON_TxREV);
   PrintUBIT(ch, "31    Receive reverse (RxREV)",  reg, HCON_RxREV);
  }
#endif							/* _S3C4530_ */
}


////////////////////////////////////////////////////////////////////////////////
// HDLC Status Register (HSTAT) ////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

static void PrintHSTAT(int ch)
{
 int cn, cnt;				// chan number, channels count
 U32 reg[2];				// HSTATA or HSTATB
 reg[0] = HSTATA;			// HSTATA 
 reg[1] = HSTATB;			// HSTATB 

 if(ch >= 0) 
  { 
   cnt = ch + 1;
   Print("HSTAT%c HDLC%c Status register 0x%08x", 'A'+ch, 'A'+ch, reg[ch]);
  }
 else 
  {
   cnt = -ch;
   Print("HSTAT Status regs A=0x%08x B=0x%08x", reg[0], reg[1]);
  } 

 {
// [3:0]   Rx remaining bytes (RxRB) ///////////////////////////////////////////
  PrintMBIT("3:0 Rx remaining bytes (RxRB)");
  for(cn = 0; cn < cnt; ++cn)  
   {
    if(cn == ch || ch < 0) 
     {
      Print("%-15d", (reg[cn] & HSTAT_RxRB));
     } 
   }
 }

// [4] Tx frame complete (TxFC) ////////////////////////////////////////////////
 PrintUBIT(ch, "4   Tx frame complete (TxFC)", reg, HSTAT_TxFC);
// [5] Tx FIFO available ///////////////////////////////////////////////////////
 PrintUBIT(ch, "5   Tx FIFO available  (TxFA)",reg, HSTAT_TxFA);
// [6] Tx clear-to-send (TxCTS) ////////////////////////////////////////////////
 PrintSBIT(ch, "6   Tx clear-to-send (TxCTS)", reg, HSTAT_TxCTS, 
  "1(nCTS input pin is Low)", "0(nCTS input pin is High)"
 );

// [7] Tx stored clear-to-send (TxSCTS) ////////////////////////////////////////
 PrintSBIT(ch, "7   Tx stored clear-to-send(TxSCTS)", reg, HSTAT_TxSCTS,
   "1(transition occurred at the nCTS input)",
   "0(Normal operation)"
 );

// [8] Tx underrun (TxU) ///////////////////////////////////////////////////////
 PrintUBIT(ch, "8   Tx underrun (TxU)", reg, HSTAT_TxU);
// [9] Rx FIFO available (RxFA) ////////////////////////////////////////////////
 PrintSBIT(ch, "9   Rx FIFO available (RxFA)", reg, HSTAT_RxFA, 
   "1(Data is available in the RxFIFO)", "0(Normal operation)"
 );

#ifdef _S3C4530_ 
//  [10] Tx Frame Good (TxFG) //////////////////////////////////////////////////
 if(is_s3c4530(syscfg_pd_id))
  {
   PrintUBIT(ch, "10  Tx Frame Good (TxFG)", reg, HSTAT_TxFG);
  }
#endif 								/* _S3C4530_ */

// [11] Rx flag detected (RxFD) ////////////////////////////////////////////////
 PrintUBIT(ch, "11  Rx flag detected (RxFD)", reg, HSTAT_RxFD);

// [12] Rx data carrier detected (RxDCD) ///////////////////////////////////////
 PrintSBIT(ch, "12  Rx data carrier detected(RxDCD)", reg, HSTAT_RxDCD, 
   "1(nDCD input pin is Low)", "0(nDCD input pin is High)"
 );

// [13] Rx stored data carrier detected (RxSDCD) ///////////////////////////////
 PrintSBIT(ch, "13  Rx stored data carrier detected", reg, HSTAT_RxSDCD, 
   "1(transition of the nDCD input)", "0(Normal operation)"
 );

// [14] Rx frame valid (RxFV) //////////////////////////////////////////////////
 PrintSBIT(ch, "14  Rx frame valid (RxFV)", reg, HSTAT_RxFV, 
   "1(last data byte of a frame recived)",
   "0(Normal operation)"
 );

// [15] Rx idle (RxIDLE) ///////////////////////////////////////////////////////
 PrintSBIT(ch, "15  Rx idle (RxIDLE)", reg, HSTAT_RxIDLE, 
   "1(Rx 15 consecutive 1s)", "0(Normal operation)"
 );

// [16] Rx abort (RxABT) ///////////////////////////////////////////////////////
 PrintSBIT(ch, "16  Rx abort (RxABT)", reg, HSTAT_RxABT, 
   "1(Rx consecutive 1s)", "0(Normal operation)"
 );

// [17] Rx CRC error (RxCRCE) //////////////////////////////////////////////////
 PrintSBIT(ch, "17  Rx CRC error (RxCRCE)", reg, HSTAT_RxCRCE,
    "1(CRC error)", "0(Normal operation)"
 );

// [18] Rx non-octet align (RxNO) //////////////////////////////////////////////
 PrintSBIT(ch, "18  Rx non-octet align (RxNO)", reg, HSTAT_RxNO,
  "1(Received frame is not octet)", "0(Received frame is octet)"
 );

// [19] Rx overrun (RxOV) //////////////////////////////////////////////////////
 PrintUBIT(ch, "19  Rx overrun (RxOV)", reg, HSTAT_RxOV);

// [20] DMA Rx memory overflow (RxMOV) /////////////////////////////////////////