evm50100.h

本source code 為s3c4510的bootloader

//#define HEAPEND               0x1FF0000		/* from RW$$Limit to DRAM0 Limit - 64Kb */	
//#define AllocNonCacheAreaBase 0x5FF0000		/* from DRAM0 Limit - 64K  		*/ 
//#define AllocNonCacheAreaEnd  0x6000000		/* to   DRAM0 Limit  			*/

/************************************************************************/ 
/* NON-CACHEABLE AREA CONTROL BIT (from KS32C50100 manual) 		*/
/* 									*/
/* Allthow the cache affects the entire system memory, it is sometimes 	*/
/* necessary to define  non-cacheable areas when the consistency of 	*/
/* data stored in memory and the cache must be ensured. To support 	*/
/* this, the KS32C50100 provides a non-cacheable control bit in the 	*/
/* address field, ADDR[26] (0x400_0000). 				*/		
/* 									*/
/* If ADDR[26] in the ROM/SRAM, flash memory, DRAM, or external I/O 	*/
/* bank's access address is 0, then accessed data is cacheable. If the	*/
/* ADDR[26] value is 1,  the accessed data is non-cacheable 		*/    
/************************************************************************/ 

extern void MemoryTest(void);		/* Memory Test Select Function */			

//                                     
/*
 *  Function for byte copy from srcp to dstp with count times
 *  (bcopy: Byte copy, scopy: Halfword, wcopy: word)
 *
 *  Where dstp is destination address,
 *        srcp is soruce address
 *        words is memory test size (words)
 */

extern int bcopy(void * /*srcp*/, void * /*dstp*/, int /*words*/, int);
extern int scopy(void * /*srcp*/, void * /*dstp*/, int /*words*/, int);	
extern int wcopy(void * /*srcp*/, void * /*dstp*/, int /*words*/, int);	

/*
 * Memory data compare test functions
 * srcp  = source address  
 * dstp  = destination address
 * words = memory test size (words)
 */

extern int bcomp(void * /*srcp*/, void * /*dstp*/, int /*words*/, int);	
extern int scomp(void * /*srcp*/, void * /*dstp*/, int /*words*/, int);	
extern int wcomp(void * /*srcp*/, void * /*dstp*/, int /*words*/, int);	


extern int  PatternGen(unsigned int /*seed*/);	/* Generate random fill pattern */		
extern void PrintRotSlash(int);			/* print memory test progress*/		

/*
 * Memory word, halfword, byte copy & compare test program
 * source address is src, destination address is dest, test memory size (words), 
 * size test repeat times is repeat.
 */

extern int MemTest(U32 * /*src*/,U32 * /*dest*/,int /*size*/,int /*repeat*/, int);

/* 
 *  DRAM Memory dump test program.
 *  Memory dump initial address is 0x1000000 (requested) 
 *                  end address is 0x1000100 (requested)	
 */

extern void MemoryDump(void);					
extern void MemDump(U32 * /*start address*/,U32 * /*End address*/);

////////////////////////////////////////////////////////////////////////////////
// pollio.c ////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

extern unsigned long Print(char * /*format */, ...);
// Read a number from the console
extern unsigned long get_number(int , int /* digits */);  

////////////////////////////////////////////////////////////////////////////////
// system.c ////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////


/* Cache memory direct access address */
#define Set0CacheRAM    0x10000000  	/* Set 0 Cache ram address */
#define Set1CacheRAM    0x10800000  	/* Set 1 Cache ram address */
#define TagRAM          0x11000000  	/* Tag ram address */
#define NonCacheArea    0x04000000  	/* ADDR[26] NonCacheable control bit */


void PrintCacheConfig(void);		/* Print Cache Configuration */
extern void CacheTest(void);		/* Cache  test top module */
extern void CacheFlush(void);		/* Cache flush (clear tag RAM) */


// Main 10N March Algorithm ////////////////////////////////////////////////////
// addr       = memory region start address
// word count = memory region size (words)
// patter     = pattern 
// prog       = 1 print progress indicator
// 
// return   1 = success
//          0 = failure  

extern int March10N32(unsigned int */*addr*/,int /*word count*/,unsigned int /*pattern*/, int prog);

/*
 *  All 10N March Test
 *  March-10N Test for Tag-RAM, 4K-SRAM, 8K-SRAM, Set0, Set1
 */

extern int March10NAllTest(void);
extern int TagMarch10(void);        	// test tag ram (256 words)
extern int SramMarch10_4k(void);   	// test SRAM in 4k mode
extern int SramMarch10_8k(void);  	// test SRAM in 8k mode	
extern int Set0March10(void);        	// test cache set 0 in SRAM disable mode
extern int Set1March10(void);      	// test cache set 1 in SRAM disable mode

/* init cache, where cmd : */
extern void CacheInit(int /*cmd*/);

#define CACHEINIT_4K	0		/* 0 = 4Kb - SRAM, 4Kb - cache */
#define CACHEINIT_8K    1 		/* 1 = 0Kb - SRAM, 8Kb - cache */
#define CACHEINIT_0K    2 		/* 2 = 8Kb - SRAM, 0Kb - cache */ 
#define CACHEINIT_OFF   2		/* 2 = Off */ 


////////////////////////////////////////////////////////////////////////////////
// timer.c /////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////


#define tmDATA(t)           (t*fMCLK_MHz * 1000 - 1)    // t is time tick,unit[ms]
#define t_data_ms(t)        (t*fMCLK_MHz * 1000 - 1)    // t is time tick,unit[ms]
#define t_data_us(t)        (t*fMCLK_MHz - 1)  		// t is time tick,unit[us]

typedef struct 
{
 volatile unsigned int tm_ms;		/* millisecond */
 volatile unsigned int tm_sec;		/* sec */
 volatile unsigned int tm_min;		/* min */
 volatile unsigned int tm_hour; 	/* hour */
 volatile unsigned int tm_mday;		/* month day */
 volatile unsigned int tm_mon;		/* month */	
 volatile unsigned int tm_year;		/* year */
}TIME; 


extern void TimerStart(int t);		/* start timer 0,1 */
extern void TimerStop(int t);		/* stop timer 0,1 */

/* init timer, set interval mode, set timer ISR, enable timer interrupt source */
extern void TimerInit(int /*timer dev*/,int /*timer data ms*/);	 
extern void TimerReset(int /* timer device number */);	/* reset timer */		
extern int  TimerEnabled(int /* timer */);
extern int  TimerWaitMs(int /*num*/ , U32 /* mswait */ );
extern void GetSysTime(int /* timer */,TIME * );	/* get system time */			
extern void tm0isr(void);    		/* timer0 interrupt service */	
extern void tm1isr(void);    		/* timer1 interrupt service */		

extern void TimerTest(void);		/* timers test main function */	


////////////////////////////////////////////////////////////////////////////////
// iic.c ///////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

extern void IICTest(void);		// main test function  
extern void IICSetup(void);		// reset IIC, set prescaler  
extern int  IICWriteReadTest(int lcnt);	// write & read test 
extern void IICReadTest(void);		// read test  
extern void IICWriteTest(void);		// write test 
extern void IICWriteByteTest(void);	// read addr, byte from console and write to EEPROM
extern void IICReadByteTest(void);	// read addr from console and read byte from EEPROM
extern int  IICByteTest(void);		// byte write & read test 

// write & read buffer in interrupt mode ///////////////////////////////////////

extern int  IICWrite(U8 /*devaddr*/,U32 /*addr*/,U8 */*data*/,U32 /*len*/);
extern void IICRead(U8 /*devaddr*/,U32 /*addr*/,U8 */*data*/,U32 /*len*/);

// write & read byte in pooling mode ///////////////////////////////////////////

extern int  IICWriteByte(U32 /*addr*/, U8 /*ch*/);	// write byte in pooling mode 
extern int  IICReadByte(U32 /*addr*/, U8 * /*ch*/);	// read byte in pooling mode 

extern int  MacAddrReadIIC(U8 * data);
extern int  MacAddrWriteIIC(U8 * data);

////////////////////////////////////////////////////////////////////////////////
// dma.c ///////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////


extern void GdmaTest(void);		// GDMA0/GDMA1 Test Top Module
extern void GDMAStartUpDialog(void);	// GDMA Configure Dialog 
extern void GdmaMemMemTest(void);	// GDMA Memory to Memory test Module
extern void UartToMemoryTest(int un, int gdma);	// UART to memoty Test  
extern void MemoryToUartTest(int un, int gdma);	// Memory to UART test 
extern void GdmaReset(unsigned cn);	 // Reset GDMA	
extern void GdmaIntEnable(unsigned cn);	 // Enable GDMA Channel Interrupt & Global interrupt  
extern void GdmaIntDisable(unsigned cn); // Disable GDMA Channle Interrupt
extern void GDMA0isr(void);		 // GDMA 0 ISR 
extern void GDMA1isr(void);		 // GDMA 1 ISR 

// copy function using GDMA 0/1 (global interrupt must be enabled) /////////////
extern void gdma0copy(U32 dmadst, U32 dmasrc,int Size, int Width);
extern void gdma1copy(U32 dmadst, U32 dmasrc,int Size, int Width);

// gdma0copy = copy using GDMA 0 
// gdma1copy = copy using GDMA 1
// dmasrc    = source address 
// dmadst    = destination address 
// Size      = transfer count
// Width     = 0 - byte (8 bit)
//             1 - half word (16 bit)
//             2 - word (32 bit) 

extern int DmaAutoTest(U32 src,U32 dst,int tsize,int lsize) ;	

////////////////////////////////////////////////////////////////////////////////
// hdlcinit.c & hdlcmain.c /////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

extern void HdlcTest(void);		// HDLC Test Main Function
extern void HDLC_Init(void);		// HDLC Channals A,B initialize
// Init Tx Buffer Descriptors ////////////////////////////////////////////////// 
// cn = channel number 
//      0 = HDLCA
//      1 = HDLCB
// np = Null List Position 
//      0 = circular buffer descriptor list   
//      1 - (HDLC_MAX_TX_DES-1) = BD[np-1]->Next = 0; 
extern void TxBD_init(int cn, int np); 
extern void RxBD_init(int cn);		// Init Rx Buffer Descriptors

extern int  HDLCSend(int cn, U8 * data, int size);
extern int  HDLCRecv(int cn, U32 * status, U8 * data, int * size);
extern int  HDLCRx_reset(int cn);	// reset Rx 
extern int  HDLCTx_reset(int cn);	// reset Tx 
extern int  HDLCTxBD_count(int cn);	// count Tx BD with owner DMA

// 
extern void HDLCRxA_isr(void);		//
extern void HDLCTxA_isr(void);		//
extern void HDLCRxB_isr(void);		//
extern void HDLCTxB_isr(void);		//

// HDLC Internal Loopback Function, cn - channel number (-1 all channels), 
// pcnt = tx frames count, (quiet == 1) => don't print error messages  
extern int HdlcInternalLoopback(int cn,int pcnt,int quiet); 
extern void HdlcRegView(void);		// Register View
extern void HdlcErrorRpt(void);		// HDLC Statistic

extern void HdlcResetTest(void);	// Reset Tests
extern void HdlcSingleTransfer(int);	//
extern void HdlcMultipleTransfer(int);	//
extern void HdlcClrErrReport(void);	// Clear Statistics 
extern void HdlcVarView(void);		// View Global Variables 

// HDLC Statistics /////////////////////////////////////////////////////////////
extern volatile U32   gHDLCRxDone;	// used in ISR CPU Mode
extern U32            gHdlcBaudRate;	// 

////////////////////////////////////////////////////////////////////////////////
// iop.c ///////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

extern void IopTest(void);			/* I/O Function Test Main module */	
extern void IoPortRw(void);			/* Read/Write port */
extern void SetupIoport(void);			/* Setup I/O port registers */

/* External interrupt service routine */

extern void ext0isr(void);			/* External interrupt 0 ISR */
extern void ext1isr(void);			/* External interrupt 1 ISR */
extern void ext2isr(void);			/* External interrupt 2 ISR */
extern void ext3isr(void);			/* External interrupt 3 ISR */

extern void ExtIntReq(int /*channel*/);		/* test external interrupt request */
extern void ExtIntAllEnable(void);		/* Enable External Interrupt 0,1,2,3 */
extern void ExtIntAllDisable(void);		/* Disable External Interrupt 0,1,2,3 */

////////////////////////////////////////////////////////////////////////////////
// zmport.c ////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

extern int ZmTest(void);

#endif 							// _EVM50100_H_