📄 mac.c
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else if( it == 'Y' || it == 'N' ) { if(it == 'Y') { Print("\nDTE is 100BASE-TX capable."); phy_ana_reg |= PHYANA_DR100_TX_HALF; } else { Print("\nDTE is not 100BASE-TX capable."); phy_ana_reg &=~PHYANA_DR100_TX_HALF; } MiiStationWrite // register write ( PHY_ANA_REG , // register address PHYHWADDR , // PHY address phy_ana_reg // register value ); } } break; case 'D' : // 10BASE-T full-duplex {////////////////////////////////////////////////////////////////////////////////// [D] 10BASE-T full-duplex //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// Print("\nEnable 10Base-T full-duplex [Y/N/Q]"); it = get_upper(); if(it == 'Q') { return; } else if( it == 'Y' || it == 'N' ) { if(it == 'Y') {// enable 10Base-T full-duplex ///////////////////////////////////////////////// Print("\nDTE is 10BASE-T full-duplex capable."); phy_ana_reg |= PHYANA_DR10_TX_FULL; } else {// disable 10Base-T full-duplex //////////////////////////////////////////////// Print("\nDTE is not 10BASE-T full-duplex capable."); phy_ana_reg &=~PHYANA_DR10_TX_FULL; } MiiStationWrite // register write ( PHY_ANA_REG , // register address PHYHWADDR , // PHY address phy_ana_reg // register value ); } } break; case 'E' : // 10BASE-T {////////////////////////////////////////////////////////////////////////////////// [E] 10Base-T //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// Print("\nEnable 10Base-T [Y/N/Q]"); it = get_upper(); if(it == 'Q') { return; } else if( it == 'Y' || it == 'N' ) { if(it == 'Y') {// enable 10Base-T half duplex ///////////////////////////////////////////////// Print("\nDTE is 10BASE-T capable."); phy_ana_reg |= PHYANA_DR10_TX_HALF; } else {// disable 10Base-T half duplex //////////////////////////////////////////////// Print("\nDTE is not 10BASE-T capable."); phy_ana_reg &=~PHYANA_DR10_TX_HALF; } MiiStationWrite // register write ( PHY_ANA_REG , // register address PHYHWADDR , // PHY address phy_ana_reg // register value ); } } break; case 'S' : // Selector Filed {////////////////////////////////////////////////////////////////////////////////// [S] Selector Filed ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// while(1) { Print("\n\nSelector Filed."); Print("\n[1] <00001> = IEEE 802.3."); Print("\n[2] <00010> = IEEE 802.9 ISLAN-16T."); Print("\n[0] <00000> = Reserved for future Auto-Negotiation development."); Print("\n[R] <11111> = Reserved for future Auto-Negotiation development."); Print("\n[Q] Quit"); // Quit from station management Print("\nSelect Test Item : "); it = get_upper(); if(it == 'Q') { return; } else if(it == '1') {// <00001> = IEEE 802.3 //////////////////////////////////////////////////////// Print("\nSelector Field = <00001>(IEEE 802.3)."); phy_ana_reg &= ~0x1F; // clear selector field bits phy_ana_reg |= 0x01; } else if(it == '2') {// <00010> = IEEE 802.9 ISLAN-16T ////////////////////////////////////////////// Print("\nSelector Field = <00010>(IEEE 802.9 ISLAN-16T)."); phy_ana_reg &= ~0x1F; // clear selector field bits phy_ana_reg |= 0x02; } else if(it == '0') {// <00000> = Reserved for future Auto-Negotiation development ////////////////// Print("\nSelector Field = <00000>."); phy_ana_reg &= ~0x1F; // clear selector field bits phy_ana_reg |= 0x00; } else if(it == 'R') {// <11111> = Reserved for future Auto-Negotiation development ////////////////// Print("\nSelector Field = <11111>."); phy_ana_reg &= ~0x1F; // clear selector field bits phy_ana_reg |= 0x1F; } else { Print("\nInvalid Test Item Selected"); continue; } MiiStationWrite // register write ( PHY_ANA_REG , // register address PHYHWADDR , // PHY address phy_ana_reg // register value ); { break; } } } break; case 'Q' : return; default : Print("\nInvalid Test Item Selected") ; break; } Print("\nPress any key to continue"); it = get_upper(); if(it == 'Q') { break; } }} ////////////////////////////////////////////////////////////////////////////////// PHY_ANLPAR_REG // Auto Negotiation Link Partner Ability Register(Address 5)//////////////////////////////////////////////////////////////////////////////////static void PhyStationAnlPar(void){ U32 phy_anlpar_reg; // Auto Negotiation Link Partner Ability Register phy_anlpar_reg = MiiStationRead // read PHY register ( PHY_ANLPAR_REG , // register address PHYHWADDR // PHY address ); Print("\n5.Auto Negotiation Link Partner Ability : 0x%04x ",phy_anlpar_reg);// Next Page(PHYANLPAR_NEXTP) ////////////////////////////////////////////////// Print("\n5.15 Next Page (RO)............%s", ((phy_anlpar_reg & PHYANLPAR_NEXTP) != 0) ? "1(LP has ability to send multiple pages)" : "0(LP has no ability to send multiple pages)" ); // Acknowledge(PHYANLPAR_ACK) ////////////////////////////////////////////////// Print("\n5.14 Acknowledge (RO)..........%s", ((phy_anlpar_reg & PHYANLPAR_ACK) != 0) ? "1(LP has received Link Code Word)" : "0(LP has not received Link Code Word)" );// Remote Fault(PHYANLPAR_REMFAULT) //////////////////////////////////////////// Print("\n5.13 Remote Fault (RO).........%s", ((phy_anlpar_reg & PHYANLPAR_REMFAULT) != 0) ? "1(Remote fault)" : "0(No remote fault)" ); // 5.12:11 Reserved Ignore on read. RO N/A// Pause(PHYANLPAR_PAUSE) ////////////////////////////////////////////////////// Print("\n5.10 Pause (RO)................%s", ((phy_anlpar_reg & PHYANLPAR_PAUSE) != 0) ? "1(Pause operation is enabled for LP)" : "0(Pause operation is disabled for LP)" ); // 100BASE-T4(PHYANLPAR_100BASET4) ///////////////////////////////////////////// Print("\n5.9 100BASE-T4 (RO)...........%s", ((phy_anlpar_reg & PHYANLPAR_100BASET4) != 0) ? "1(LP is 100BASE-T4 capable)" : "0(LP is not 100BASE-T4 capable)" ); // 100BASE-TX full-duplex(PHYANLPAR_100BASETX_FD) ////////////////////////////// Print("\n5.8 100BaseTX full-duplex(RO).%s", ((phy_anlpar_reg & PHYANLPAR_100BASETX_FD) != 0) ? "1(LP is 100BASE-TX full-duplex capable)" : "0(LP is not 100BASE-TX full-duplex capable)" ); // 100BASE-TX(PHYANLPAR_100BASETX_HD) ////////////////////////////////////////// Print("\n5.7 100BASE-TX (RO)...........%s", ((phy_anlpar_reg & PHYANLPAR_100BASETX_HD) != 0) ? "1(LP is 100BASE-TX capable)" : "0(LP is not 100BASE-TX capable)" ); // 10BASE-T full-duplex(PHYANLPAR_10BASET_FD) ////////////////////////////////// Print("\n5.6 10BASE-T full-duplex(RO)..%s", ((phy_anlpar_reg & PHYANLPAR_10BASET_FD) != 0) ? "1(LP is 10BASE-T full-duplex capable)" : "0(LP is not 10BASE-T full-duplex capable)" ); // 10BASE-T(PHYANLPAR_10BASET_HD) ////////////////////////////////////////////// Print("\n5.5 10BASE-T (RO).............%s", ((phy_anlpar_reg & PHYANLPAR_10BASET_HD) != 0) ? "1(LP is 10BASE-T capable)" : "0(LP is not 10BASE-T capable)" ); // Selector Field S[4:0](PHYANLPAR_SEL_FIELD) ////////////////////////////////// Print("\n5.4:0 Selector Field (RO)......"); switch((phy_anlpar_reg & PHYANLPAR_SEL_FIELD) != 0) { case 0x01 : Print("<00001>(IEEE 802.3)"); break; case 0x02 : Print("<00010>(IEEE 802.9 ISLAN-16T)"); break; case 0x00 : Print("<00000>(Reserved for future Auto-Negotiation development)"); break; case 0x1F : Print("<11111>(Reserved ved for future Aut o-Negotiation development)"); break; } Print("\n LP = Link Partner");}////////////////////////////////////////////////////////////////////////////////// PHY_ANE_REG // Auto Negotiation Expansion (Address 6) ///////////////////////////////////////////////////////////////////////////////////////////////////////static void PhyStationAne(void){ U32 phy_ane_reg; // Auto Negotiation Expansion register phy_ane_reg = MiiStationRead ( PHY_ANE_REG , PHYHWADDR ); Print("\n6. Auto Negotiation Expansion Register : 0x%04x ",phy_ane_reg);// Parallel Detection Fault(PHYANE_PAR_DET_FAULT) ////////////////////////////// Print("\n6.4 Parallel Detect.Fault (RO/LH).%s", ((phy_ane_reg & PHYANE_PAR_DET_FAULT) != 0) ? "1(Parallel detection fault has occurred)" : "0(Parallel detection fault has not occurred)" );// Link Partner Next Page Able(PHYANE_LP_NEXT_PAGE) //////////////////////////// Print("\n6.3 LP Next Page Able (RO)........%s", ((phy_ane_reg & PHYANE_LP_NEXT_PAGE) != 0) ? "1(Link partner is next page able)" : "0(Link partner is not next page able)" );// Next Page Able(PHYANE_NEXT_PAGE) //////////////////////////////////////////// Print("\n6.2 Next Page Able (RO)...........%s", ((phy_ane_reg & PHYANE_NEXT_PAGE) != 0) ? "1(Supported)" : "0(Not Supported)" );// Page Received(PHYANE_PAGE_REC) ////////////////////////////////////////////// Print("\n6.1 Page Received (RO/LH).........%s", ((phy_ane_reg & PHYANE_PAGE_REC) != 0) ? "1(3 identical and consecutive link code words received)" : "0(3 identical and consecutive link code words not received)" );// Link Partner Auto Neg Abl(PHYANE_LP_AUTONEG) //////////////////////////////// Print("\n6.0 LP Auto Neg Able (RO).........%s", ((phy_ane_reg & PHYANE_LP_AUTONEG) != 0) ? "1(LP is auto-negotiation able)" : "0(LP is not auto-negotiation able)" ); // Print("\n LP = Link Partner"); Print("\n RO = Read Only"); Print("\n LH = Latching High");}////////////////////////////////////////////////////////////////////////////////// PHY_ECNTL_REG1 // Mirror Register (Address 16, Hex 10) //////////////////////////////////////////////////////////////////////////////////////////////////////static void PhyStationEcntl(void){ U32 phy_ecntl_reg1; // Mirror Register TIME tm; int err = 0; // error flag U8 ch;// Print("\n\nPHY.16. Read/Write test"); phy_ecntl_reg1 = MiiStationRead ( PHY_ECNTL_REG1 , // PHYHWADDR // ); Print("\n16. Mirror Register : 0x%04x ", phy_ecntl_reg1); Print("\nThis register is intended for use in checking the"); Print("\nMII serial port and has no affect on chip operation."); Print("\nPress any key to run read & write test"); ch = get_upper();// PHY_ECNTL_REG1 Read Write Test ////////////////////////////////////////////// TimerReset(1); TimerInit(1,(ONE_SECOND/TICKS_PER_SECOND)); TimerStart(1); Print("\nPress any key to break read & write test"); for(phy_ecntl_reg1 = 0; phy_ecntl_reg1 < 0xFFFF; ++phy_ecntl_reg1) { if(kbd_hit()) { ch = get_upper(); break; } // if((phy_ecntl_reg1 & 0x1F) == 0) { PrintRotSlash((phy_ecntl_reg1 >> 5) & 0x3); } // PHY_ECNTL_REG1 Write //////////////////////////////////////////////////////// MiiStationWrite (
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