init.s

本source code 為s3c4510的bootloader

; [31]    Sync DRAM interface for 4 DRAM banks

SYNC_DRAM_CONFIGURATION
     IF :DEF: ROM_AT_ADDRESS_ZERO
;ROM and RAM Configuration(Multiple Load and Store)
;/* ROM sturtup tests & monitor */
   	LDR     r0, =SystemInitDataSDRAM
	LDMIA   r0, {r1-r12}
	LDR	r0, =0x3FF0000 + 0x3010 ; EXTDBWTH Offset : 0x3010
	STMIA   r0, {r1-r12}
    ENDIF

	LDR	r0, =0x3FF0000		 
	LDR	r1, =0x83FFFFA0   	; SetValue = 0x83FFFFA1
	STR	r1, [r0]	  	; Cache,WB disable
                           		; Start_addr = 0x3FF00000
INITIALIZE_C
;=====================================
; Initialise memory required by C code
;=====================================
    	IMPORT  |Image$$RO$$Limit|  ; End of ROM code (=start of ROM data)
    	IMPORT  |Image$$RW$$Base|   ; Base of RAM to initialise
    	IMPORT  |Image$$ZI$$Base|   ; Base and limit of area
        IMPORT  |Image$$RW$$Limit|  ;
    	IMPORT  |Image$$ZI$$Limit|  ; to zero initialise

    IF :DEF: ROM_AT_ADDRESS_ZERO
;/* ROM_AT_ADDRESS_ZERO defined in ROM startup tests and in Monitor */
    IF :DEF: LED_ONLY
;/* Monitor */
;/* RO area - ROM bank 0; RW, ZI in internal SDRAM */
;/* => copy RW area to internal SDRAM */
;/* Image$$RW$$Base must be set to 0x3FE0000 in linker command line */
    	LDR     r0, =|Image$$RO$$Limit|;
    	LDR     r1, =|Image$$RW$$Base|;
        LDR     r3, =|Image$$RW$$Limit|;
1       CMP     r1, r3 			; while(r1 < r3)
    	LDRLO   r2, [r0], #4	     	; [r0 += 4]
    	STRLO   r2, [r1], #4	     	; [r1 += 4]
    	BLO     %1
    ELSE
;/* ROM Startup, copy  RO/RW areas to external DRAM */
;/* ! Image$$RO$$Limit must be equal Image$$RW$$Base ! */
        MOV     r0, #0 
        MOV     r1, #0x1000000
    	LDR     r3, =|Image$$ZI$$Base|;

0   	CMP     r0, r3               ; while(r0 < r3)
    	LDRLO   r2, [r0], #4	     ; [r0 += 4]
    	STRLO   r2, [r1], #4	     ; [r1 += 4]
    	BLO     %0
    ENDIF 
    ENDIF 
	
;/* Init ZI area */
    	MOV     r2, #0
    	LDR     r1, =|Image$$ZI$$Base|;
    	LDR     r3, =|Image$$ZI$$Limit|;
    IF :DEF: ROM_AT_ADDRESS_ZERO
    IF :DEF: LED_ONLY
    ELSE
        ORR     r1, r1, #0x1000000
        ORR     r3, r3, #0x1000000
    ENDIF
    ENDIF 
2  	CMP     r1, r3               
    	STRLO   r2, [r1], #4
    	BLO     %2

;/***********************************************************************/
;/*---+------------+							*/
;/*   |            |							*/
;/*   |            |        +------------+ Image$$ZI$$Limit		*/
;/*   |            |        |            |                 		*/
;/*   |            |        | ZI Output  | ZI execution  		*/
;/* R |            |        |    section |    region  			*/
;/* A |            |        |            |                 		*/
;/* M |            |        |            | Image$$ZI$$Base 		*/
;/*   |            |        +------------+	    is equal     	*/
;/*   |            |        |            | Iage$$RW$$Limit 		*/
;/*   |            |        |            |                 		*/
;/*   |            |        | RW Output  | RW execution 		*/
;/*   |            |        |    section |    region 			*/
;/*   |            |        |            |                 		*/
;/*---+------------+--------+------------+ Image$$RW$$Base		*/
;/*   | RW Output  |        |            |				*/
;/* R |    section | single |            |  				*/
;/* O +------------+ load   +------------+ Image$$RO$$Limit     	*/
;/*   |            | region |            |                 		*/
;/* M | RO Output  |        | RO Output  | RO execution  		*/
;/*   |    section |        |    section |    region   			*/
;/*---+------------+--------+------------+ 				*/	
;/*    LOAD VIEW            EXECUTION VIEW				*/
;/***********************************************************************/

	;====================================================
	; Now change to user mode and set up user mode stack.
	;====================================================
        MRS     r0, cpsr
	BIC	r0, r0, #LOCK_MASK | MODE_MASK
	ORR	r1, r0, #USR_MODE
	MSR	cpsr_csxf, r1			; 
	LDR	sp, =USR_STACK


;/* Call C_Entry application routine with a pointer to the first */
;/* available memory address after ther compiler's global data   */
;/* This memory may be used by the application.                  */
	;===========================
	; Now we enter the C Program
	;===========================

;/* UART0 Baud Rate Register */   
	LDR	r1, =UARTBRD0			; I/O port data register
        LDR     r2, =0x00280       		; 38400
;/* 0x00a20 //   9600 // cnt0 = 162 cnt1 = 0, 0 */
;/* 0x00500 //  19200 // cnt0 =  80 cnt1 = 0, 1 */
;/* 0x00280 //  38400 // cnt0 =  40 cnt1 = 0, 2 */
;/* 0x001a0 //  57600 // cnt0 =  26 cnt1 = 0, 3 */
;/* 0x000d0 // 115200 // cnt0 =  13 cnt1 = 0, 4 */
;/* 0x00060 // 230400 // cnt0 =   6 cnt1 = 0, 5 */
;/* 0x00020 // 460800 // cnt0 =   2 cnt1 = 0, 6 not available*/
        STR     r2, [r1]

	LDR	r0, =0x3FF0000	   		; SYSCFG register address 
	LDR 	r1,[r0]		   		; Read SYSCFG register value
	LDR	r2, =0x0C000000	   		; lo bits of PID(product id)
; [30:26]
; 00000 = KS32C5000
; 00001 = KS32C50100 s3c4510x
; 11001 = s3c4510B
; 00011 = s3c4530X
; 10011 = s3c4530A
	AND	r0, r1, r2         		; 
	CMP	r0, r2
	BEQ 	UART0_S3C4530_CONF

UART0_S3C4510_CONF
;/* UART0 Line Control Register */
	LDR	r1, =UARTLCON0			; I/O port data register
        LDR     r2, =0x03        		; ULCON_WL8 0x03, word lengt 8 bit
        STR     r2, [r1]
;/* UART0 Control register */    
	LDR	r1, =UARTCONT0			; I/O port data register
        LDR     r2, =0x09        		; Tx mode int, Rx mode int   
        STR     r2, [r1]
	B 	P16_start

UART0_S3C4530_CONF
	LDR	r1, =UCON0			; I/O port data register
        LDR     r2, =0x00003005       		; word len 8 bit, tx mode int, rx mode int
        STR     r2, [r1]

P16_start


;/* write 0/1 to port P16 */

;////////////////////////////////////////////////////////////////////////////////
        LDR     r3, =0x4			; 03.04.2002 loop count

P16_write
	LDR	r0, =0x00000			; write 0 to port P16
	LDR	r1, =IOPDATA			; I/O port data register
	MOV	r2, #0x040000			; loop counter

P16_write_0
	STR	r0, [r1]			; 1 cycle, write to I/O port data register
	SUBS	r2, r2, #1			; 1 cycle, Down Count
	BNE 	P16_write_0			; 3 cycles

	LDR	r0, =0x10000			; write 1 to port P16
	MOV	r2, #0x040000			; loop counter

P16_write_1

	STR	r0, [r1]			; write to I/O port data register
	SUBS	r2, r2, #1			; Down Count
	BNE 	P16_write_1			;

        SUBS    r3, r3, #1 			;
        BNE     P16_write			;

    IF :DEF: ROM_AT_ADDRESS_ZERO
    IF :DEF: LED_ONLY               
;/* Monitor, DRAM remain start from 0x01000000 (16M-32M)*/
    ELSE 
;/* ROM startup test, remap DRAM to 0x00000000, ROM to 0x02000000 */
   	LDR     r0, =SystemWorkDataSDRAM
	LDMIA   r0, {r1-r12}
	LDR	r0, =0x3FF0000 + 0x3010 ; EXTDBWTH Offset : 0x3010
	STMIA   r0, {r1-r12}
    ENDIF 
    ENDIF
        IMPORT  C_Entry				;
        BL      C_Entry				;

	AREA ROMDATA, DATA, READONLY

    IF :DEF: ROM_AT_ADDRESS_ZERO
;======================================================
; DRAM System Initialize Data(KS32C5000 and KS32C50100)
;======================================================
SystemInitData
    	IF :DEF: EDO_DRAM_CONFIG 
	DCD rEXTDBWTH		;
	DCD initROMCON0		;
	DCD initROMCON1		; 
    	DCD initROMCON2		;
	DCD initROMCON3		;
	DCD initROMCON4		;
	DCD initROMCON5		; 
	DCD initDRAMCON0   	;
	DCD initDRAMCON1	;
	DCD initDRAMCON2	;
	DCD initDRAMCON3	;
	DCD rREFEXTCON  	;
    	ENDIF
;======================================================
; SDRAM System Initialize Data	(KS32C50100 only)
;======================================================
SystemInitDataSDRAM
	DCD rEXTDBWTH		;
	DCD initROMCON0		;
	DCD initROMCON1		;
    	DCD initROMCON2		;
	DCD initROMCON3		;
	DCD initROMCON4		;
	DCD initROMCON5		;
	DCD initSDRAMCON0  	;
	DCD initSDRAMCON1	;
	DCD initSDRAMCON2	;
	DCD initSDRAMCON3	;
	DCD rSREFEXTCON 	;

    	IF :DEF: LED_ONLY
;/* Monitor used only SystemInitDataSDRAM memory map */
	ELSE
SystemWorkDataSDRAM
	DCD rEXTDBWTH		;
	DCD workROMCON0		;
	DCD workROMCON1		;
    	DCD workROMCON2		;
	DCD workROMCON3		;
	DCD workROMCON4		;
	DCD workROMCON5		;
	DCD workSDRAMCON0  	;
	DCD workSDRAMCON1	;
	DCD workSDRAMCON2	;
	DCD workSDRAMCON3	;
	DCD rSREFEXTCON 	;
    	ENDIF
    ENDIF							
	ALIGN

;/***********************************************************************/
	AREA    START, CODE
;/***********************************************************************/
	EXPORT	StartDownPgm
StartDownPgm
	MOV	PC, r0

;/***********************************************************************/
	AREA SYS_STACK, NOINIT
;/***********************************************************************/

;/***********************************************************************/
;/*NOINIT -Indicates that the data section is uninitialized, or 	*/
;/*	initialized to zero. It contains only space reservation 	*/
;/*	directives (DCD ,DCDU , DCQ , DCQU , DCW , DCWU  ), with no 	*/
;/*	initialized values. You can decide at link time whether an 	*/
;/*	AREA is uninitialized or zero-initialized (see the Linker 	*/
;/*	chapter in ADS Compiler, Linker, and Utilities Guide).		*/
;/*									*/
;/*DATA  - Contains data, not instructions. READWRITE is the default.   */
;/***********************************************************************/				

;/***********************************************************************/				
;/* Data definition directive SPACE					*/
;/* The SPACE directive reserves a zeroed block of memory. 		*/
;/* %is a synonym for SPACE.						*/
;/*									*/
;/* Syntax								*/
;/*									*/
;/* {label }SPACE expr							*/
;/*									*/
;/* where: expr evaluates to the number of zeroed bytes 		*/
;/* 	   to reserve 							*/
;/***********************************************************************/				
                %       USR_STACK_SIZE
USR_STACK
                %       UDF_STACK_SIZE
UDF_STACK
                %       ABT_STACK_SIZE
ABT_STACK
                %       IRQ_STACK_SIZE
IRQ_STACK
                %       FIQ_STACK_SIZE
FIQ_STACK
                %       SUP_STACK_SIZE
SUP_STACK

;/* Stack sizes are defined in evm50100.a */
;/* The ATPCS,and ARMand Thumb C and C++ compilers always use */
;/* a full descending stack. */

;/***********************************************************************/
	END