mac.h

本source code 為s3c4510的bootloader

#ifdef __GNUC__ 
    __attribute__ ((__packed__))
#endif 								/* __GNUC__  */
etheader ;

typedef 
#ifndef __GNUC__ 
__packed 
#endif 								/* __GNUC__  */
struct MACFrame {	
	etheader 	Header ;
	U8 		LLCData[1506] ;
}
#ifdef __GNUC__ 
    __attribute__ ((__packed__))
#endif 								/* __GNUC__  */
 sMACFrame;

////////////////////////////////////////////////////////////////////////////////
// MAC Tx Status Structure /////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

typedef struct MACTxStatus 
{
 U32 MacTxGood;
 U32 ExCollErr;		// Transmit collission count 
 U32 TxDefferedErr;	// Transmit deferred
 U32 sPaused;		// Paused
 U32 UnderErr;		// Underrun
 U32 DeferErr;		// Deferral
 U32 NCarrErr;		// No carrier
 U32 sSQE;		// Signal quality error
 U32 LateCollErr;	// Late collision
 U32 TxParErr;		// Transmit parity error
 U32 sTxHalted;		// Transmission halted
} 
 pMACTxStatus;


////////////////////////////////////////////////////////////////////////////////
// MAC Rx Status Structure /////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

typedef struct MACRxStatus 
{
 U32 OvMaxSize;
 U32 sCtlRecd;		// Control frame received
 U32 sRx10Stat;		// Receive 10-Mb/s status
 U32 AllgnErr;		// Alignment error
 U32 sCRCErr;		// CRC error
 U32 OverflowErr;	// Overflow error
 U32 sLongErr;		// Long error
 U32 RxParErr;		// Receive parity error
 U32 sRxHalted;		// Reception halted
} 
 pMACRxStatus;


////////////////////////////////////////////////////////////////////////////////
// BDMA Tx Status Structure ////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

typedef struct BDMATxStatus 
{
 U32 BTxNLErr;		// BDMA Tx null list (BTxNL)
 U32 BTxNOErr;		// BDMA Tx not owner (BTxNO)
 U32 BTxEmptyErr;	// BDMA Tx buffer empty (BTxEmpty)
} 
 pBDMATxStatus;


////////////////////////////////////////////////////////////////////////////////
// BDMA Rx Status Structure ////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

typedef struct BDMARxStatus 
{
 U32 BdmaRxCnt;
 U32 BdmaRxGood;
 U32 BRxNLErr;		// BDMA Rx null list (BRxNL)
 U32 BRxNOErr;		// BDMA Rx not owner (BRxNO)
 U32 BRxMSOErr;		// BDMA Rx maximum size over (BRxMSO)
} 
 pBDMARxStatus ;



/****************************************/
/*  PHY(LXT970A) Register Description   */
/****************************************/
/* PHY_CNTL_REG     : 0x00              */
/* PHY_STATUS_REG   : 0x01              */
/* PHY_ID_REG1      : 0x02              */
/* PHY_ID_REG2      : 0x03              */
/* PHY_ANA_REG      : 0x04              */
/* PHY_ANLPAR_REG   : 0x05              */
/* PHY_ANE_REG      : 0x06              */
/* PHY_ECNTL_REG1   : 0x10              */
/* PHY_INTEN_REG    : 0x11              */
/* PHY_INTSTAT_REG  : 0x12              */
/* PHY_ECNTL_REG2   : 0x13              */
/* PHY_CHIPSTAT_REG : 0x14              */
/****************************************/

////////////////////////////////////////////////////////////////////////////////
// [4:0] STACON // PHY register address (addr) /////////////////////////////////
//////////////////////////////////////////////////////////////////////////////// 

#define	PHY_CNTL_REG 	  0x00	/* Control register (Address 0) */
#define	PHY_STATUS_REG 	  0x01	/* Status register (Address 1) */
#define	PHY_ID_REG1    	  0x02	/* PHY identififcation Register 1 (Address 2) */
#define	PHY_ID_REG2    	  0x03	/* PHY identififcation Register 2 (Address 3)*/
#define	PHY_ANA_REG    	  0x04	/* Auto Negotiation Advertisement Register (Address 4) */
#define	PHY_ANLPAR_REG 	  0x05	/* Auto Negotiation Link Partner Ability Register (Address 5) */
#define	PHY_ANE_REG    	  0x06	/* Auto Negotiation Expansion (Address 6)*/
#define	PHY_ECNTL_REG1 	  0x10  /* Mirror Register (Address 16, Hex 10)*/
#define	PHY_INTEN_REG     0x11	/* Interrupt Enable Register (Address 17, Hex 11) */
#define	PHY_INTSTAT_REG   0x12	/* Interrupt Status Register */
#define	PHY_ECNTL_REG2 	  0x13	/* Extended control register */
#define	PHY_CHIPSTAT_REG  0x14	/* Chip Status Register */

// [9:5] STACON // PHY address. The 5-bit address of the PHY device ////////////
// to read or writen /////////////////////////////////////////////////////////// 	
#define PHYHWADDR         0x20	/* A0 = 1, A1,2,3,4 = 0 */

////////////////////////////////////////////////////////////////////////////////	
// PHY control register ////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////	

#define RESET_PHY	(1 << 15)	/* Reset (R/W,Self Clearing) */
// 1 =   Reset chip.
// 0 =   Enable normal operation.

#define ENABLE_LOOPBACK	(1 << 14)	/* Loopback mode (R/W) */
// 1 =   Enable loopback mode. When Loopback is enabled, during 100
// 	 Mbps operation, the LXT970A disconnects its transmitter and receiver
// 	 from the network. Data sent by the controller passes through the chip
// 	 and then gets looped back to the MII. During 10 Mbps operation the
// 	 preamble, SFD, and data loop directly back to the MII.
// 0 =   Disable loopback mode.
#define DR_100MB	(1 << 13)	/* Speed selection (R/W)*/
// 1 =   100 Mbps
// 0 =   10  Mbps
// 
// NOTE  If auto-negotiation is enabled, this bit is ignored. 
// 	 If auto-negotiation is disabled, the default value of bit 0.13 
//       is determined by pin CFG0.    

#define ENABLE_AN	(1 << 12)	/* Auto-Negotiatiation Enable (R/W)*/
// 0.12  Auto-Negotiation Enable
// 1 =   Enable auto-negotiate process (overrides speed select and 
// 	 duplex mode bits).
// 0 =   Disable auto-negotiate process.
// 
// NOTE  The default value of bit 0.12 is determined by pin MF0.

#define PHY_POWER_DOWN  (1 << 11)	/* Power down */
// 0.11  Power Down 
// 1 =   Enable power down.
// 0 =   Enable normal operation.
//
// NOTE  The LXT970A internally maintains all set values of the 
//       configuration registers upon exiting power-down mode.
//       A delay of 500 ns minimum is required from the time 
//       power down is cleared until any register can be written.

#define PHY_MAC_ISOLATE	(1 << 10)	/* Isolate */
// 0.10  Isolate 
// 1 =   Electrically isolate LXT970A from MII.
// 0 =   Normal operation.
// 
// NOTE  The default value of bit 0.10 is determined by pin TRSTE.
#define RESTART_AN	(1 << 9)	/* Restart Auto-negotiation (R/W, Self Cleared)*/
// 0.9   Restart Auto-Negotiation 
// 1 =   Restart auto-negotiation process.
// 0 =   Normal operation.
// 
// NOTE  If auto-negotiation is enabled, the default value of bit 0.9 
//       is determined by pin CFG0. If auto-negotiation is disabled, the
//       default value of bit 0.9 = 0.
#define PHY_FULLDUPLEX	(1 << 8)	/* Duplex mode */
// 0.8   Duplex Mode 
// 1 =   Enable full-duplex.
// 0 =   Enable half-duplex. 
// 
// NOTE  If auto-negotiation is enabled, this bit is ignored. 
//       If auto-negotiation is disabled, the default value of bit 
//       0.8 is determined by pin FDE.
#define PHY_COL_TEST	(1 << 7)	/* Colision Test */
// 0.7   Collision Test
// 1 =   Enable COL signal test. Bit 0.14 must be enabled to use this bit.
//       This bit is used in conjunction with bit 0.14 to test the COL output.
// 0 =   Disable COL signal test.
// 
// NOTE  This bit is ignored unless loopback is enabled (0.14 = 1).

// 0.6:4 Transceiver Test Mode Not Supported. (RO)
#define PHY_TX_TEST_MODE  0x70 		/* Transceiver Test Mode Not */

// 0.3   Master-Slave Enable. Not Supported. (RO)
#define PHY_MASTER_SL_EN   0x08		/* Master-Slave Enable. */

// 0.2   Master-SlaveValue. Not Supported. (RO)
#define PHY_MASTER_SL_VAL  0x02   	/* Master-SlaveValue. */

// 0.1:0 Reserved (R/W)

////////////////////////////////////////////////////////////////////////////////
// PHY Status register /////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

#define PHYSTAT_100BASET4      (1<<15)	/* 100Base-T4 */ 	 
// 1.15 100BASE-T4 Not Supported. Read Only. Default Value=0

#define PHYSTAT_100BASEX_FD    (1<<14)	/* 100Base-X full-duplex */ 
// 1.14 100BASE-X full-duplex. Read Only. Default Value=1
// 	1 = LXT970A able to perform full-duplex 100BASE-X.

#define PHYSTAT_100BASEX_HD    (1<<13)  /* 100BaseX half-duplex */	 
// 1.13 100BASE-X half-duplex. Read Only. Default Value=1 
//      1 = LXT970A able to perform half-duplex 100BASE-X.

#define PHYSTAT_10BASE_FD      (1<<12)	/* 10BaseT full-duplex */ 	 
// 1.12 10 Mb/s full-duplex. Read Only Default Value=1 
//      1 = LXT970A able to operate at 10 Mb/s in full-duplex mode.

#define PHYSTAT_10BASE_HD      (1<<11)	/* 10BaseT half-duplex */	 
// 1.11 10 Mb/s half-duplex. Read Only. Default Value=1 
//      1 = LXT970A able to operate at 10 Mb/s in half-duplex mode. 
					
#define PHYSTAT_100BASET2_FD   (1<<10)	/* 100BaseT2 full-duplex */ 	 
// 1.10 100BASE-T2 full-duplex. Not Supported. Read Only. Default Value=0

#define PHYSTAT_100BASET2_HD   (1<<9)	/* 100BaseT2 half-duplex */ 	 
// 1.9  100BASE-T2 half-duplex. Not Supported. Read Only. Default Value=0
// 1.8  Reserved Ignore on read. Read Only. Default Value=0

#define PHYSTAT_MASTERSL_FAULT (1<<7)	/* Master-Slave Fault */	 
// 1.7  Master-Slave Configuration Fault. Not Supported. RO,0

#define PHYSTAT_MFPREAMB_SUPPR (1<<6)	 
// 1.6  MF Preamble Suppression.  Read Only. Default Value = 0 
//      0 = LXT970A will not accept management frames with preamble
//      suppressed.

#define PHYSTAT_AN_COMPLETE    (1<<5)	/* Auto-Negotiation Complete */
// 1.5  Auto-Negotiation Complete. Read Only. Default Value=0
//      1 = Auto-negotiation process complete.
//      0 = Auto-negotiation process not complete. 

#define PHYSTAT_REMOTE_FAULT   (1<<4)	/* Remote fault */	 
// 1.4  Remote Fault. RO/Latching Hight (This bit remains High until read,
//      and then return Low).
//      1 = Remote fault condition detected.
//      0 = No remote fault condition detected.
// 
//      This bit is set when:
//      Link partner transmits a remote fault condition (bit 5.13 = 1)
//      Link partner protocol is anything other than CSMA-CD 
//      (bits 5.4:0 = <00001>)
//      Link partner advertises T4 capability only (bits 5.9:5