mac.h

本source code 為s3c4510的bootloader

/********************************************************************/
/*       MAC Header for KS32C5000                                   */
/*------------------------------------------------------------------*/
/*      Copyright (C) 1997 Samsung Electronics.                     */
/*------------------------------------------------------------------*/
/*      Modified, programmed by hbahn                               */
/*                                                                  */
/*      Description : 1998-2-10 first edited for KS32C5000          */ 
/********************************************************************/

/* 			*/
/* Modified by 		*/
/* Dmitriy Cherkashin 	*/
/* [e-mail]	*/
/* 2002			*/
/*			*/

#ifndef _MAC_
#define _MAC_

#define MAC_ADDR_SIZE         6      /* dst,src addr is 6bytes each*/ 

#define MaxRxFrameSize  	1520 // Rx Frame Max Size 
#define MAC_MAX_RX_DES  	64   // Max number of Rx Frame Descriptors 
#define MAC_MAX_TX_DES  	16   // Max number of Tx Frame Descriptors

////////////////////////////////////////////////////////////////////////////////
// Tx/Rx common descriptor structure ///////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

typedef struct FrameDes 
 {	
  U32 DataPtr;		  	// Data pointer 	
// cf: RX-reserved, TX-Reserved(25bits) + Control bits(7bits)
  U32 Reserved; 		// 
  U32 StatusLength;		// status & length field
  U32 NextDes;			// next descriptor
 } sFrameDes;

/************************************************************************/
/* 	Data structure of Rx Frame descriptor 				*/
/*									*/ 
/* 	| 31|  30              16 | 15                          0	*/
/* 	----------------------------------------------------------	*/
/* 	| O |             Frame Data Pointer                     |	*/
/* 	----------------------------------------------------------      */
/* 	|                      Reserved                          |	*/
/* 	----------------------------------------------------------      */ 
/* 	| Rx Status               | Frame Length                 |    	*/
/* 	----------------------------------------------------------	*/
/* 	| Next Frame              | Descriptor Pointer           |	*/
/* 	----------------------------------------------------------	*/
/* 									*/
/* 	[31] 	Ownership bit (O) 					*/
/*              0 = CPU							*/
/* 		1 = BDMA						*/
/* 									*/
/* 	[30:0]  Frame data pointer					*/
/* 		Address of the frame data to be saved.			*/
/* 									*/
/* 	[15:0]  Frame length 						*/
/* 		The size of the received frame. 			*/
/* 									*/
/* 	[31:16] Rx status						*/
/* 		The Rx status field of the receive frame is updated	*/
/* 		by the MAC after reception is complete. 		*/
/* 									*/
/* 	[31:0] 	Next frame descriptor pointer				*/
/* 		Address of next frame descriptor 			*/
/************************************************************************/

////////////////////////////////////////////////////////////////////////////////
// TxRx Frame Descriptor ///////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

#define	fOwnership_BDMA	0x80000000 // 0:CPU, 1:BDMA
#define	fOwnership_CPU	0x7fffffff // 0:CPU, 1:BDMA

/************************************************************************/
/* Rx Descriptor Status Bits 						*/
/* 									*/
/* [19]	 Over maximum size (OvMax)			      	      	*/
/*   3	 Set if the received frame data size exceeds the maximum  frame */
/* 	 size. 								*/
/* 									*/
/* [21]  Control received (CtlRcv)				      	*/
/*   5 	 Set if the received packet is a MAC control frame.	        */
/* 									*/
/* [22]  Interrupt on receive (IntRx)				        */
/*   6   Set if reception of packet caused an interrupt condition.      */
/* 	 This includes Good received, if the Engood bit,MACRXCON [14],	*/
/*	 is set. 							*/
/* 									*/
/* [23]  Receive 10 Mb/s status (Rx10Stat)				*/
/*   7   Set if packet was received over the 10-Mbyte/s interface. 	*/
/*	 Reset if packet was received over the MII.			*/
/* 									*/
/* [24]  Alignment error (AlignErr)					*/
/*   8   Frame length in bits was not a multiple of eight and the CRC 	*/
/*       was invalid. 							*/
/* 									*/
/* [25]  CRC error (CRCErr) 						*/
/*   9   CRC at end of packet did not match the computed value, or else */
/* 	 the PHY asserted Rx_er during packet reception.		*/
/* [26]  Overflow error (Overflow)					*/
/*  10   The MAC receive FIFO was full when it needed to store a 	*/
/*       received byte. 						*/
/* [27]  Long error (LongErr) 						*/
/*  11   Received a frame longer than 1518 bytes. Not set if the Long 	*/
/*       enable bit in the receive control register is set. 		*/
/* [29]  Receive parity error (RxPar) 					*/
/*  13   MAC receive FIFO has detected a parity error. 			*/
/* [30]  Good received (Good) 						*/
/*  14   Successfully received a packet with no errors. If EnGood = 1,  */
/*       an interrupt is generated on each packet that is received 	*/
/*       successfully. 							*/
/* [31]  Reception halted (RxHalted) 					*/
/*  15   Reception interrupted by user clearing RxEN or setting Haltlmm */
/*       in the MAC control register. 					*/
/************************************************************************/

#define	RXFDST_OvMax	0x0008	// Over Maximum Size
#define	RXFDST_CtlRecd	0x0020	// set if packet received is a MAC control frame.
#define	RXFDST_IntRx	0x0040	// Interrupt on Receive 
#define RXFDST_Rx10Stat	0x0080	// set if packet was received via the 10bits interface reset if packet 
				// was received via MII
#define	RXFDST_AlignErr	0x0100	// Alignment Error
#define	RXFDST_CRCErr	0x0200	// CRC error
#define	RXFDST_Overflow	0x0400	// MAC receive FIFO was full when it 
				// needed to store a received byte
#define	RXFDST_LongErr	0x0800	// received a frame longer than 1518 bytes 
#define	RXFDST_RxPar	0x2000	// MAC receive FIFO has detected a parity error
#define RXFDST_RxGood	0x4000	// successfully received a packet with no errors
#define RXFDST_RxHalted	0x8000	// Reception interrupted by clearing RxEN

/************************************************************************/
/* 	Data structure of Tx Frame descriptor 				*/
/* 									*/
/* 	| 31|  30              16 | 15  |6  5| 4 | 3 | 2 | 1 | 0 |	*/
/* 	----------------------------------------------------------	*/
/* 	| O |             Frame Data Pointer                     |	*/
/* 	----------------------------------------------------------	*/
/* 	|         Reserved              | WA | A | L | T | C | P |	*/
/* 	----------------------------------------------------------	*/
/* 	| Tx Status               | Frame Length                 |	*/
/* 	----------------------------------------------------------	*/
/* 	| Next Frame              | Descriptor Pointer           |	*/
/* 	----------------------------------------------------------	*/
/* 									*/
/* 	[31] 	Ownership bit (O)					*/
/* 		0 = CPU 1 = BDMA					*/
/* 	[30:0]	Frame data pointer					*/
/* 		The address of the frame data to be transmitted.	*/
/* 	[0] 	No-padding mode (P)					*/
/* 		0 = Padding mode 	1 = No-padding mode		*/
/* 	[1] 	No-CRC mode (C)						*/
/* 		0 = CRC mode		1 = No-CRC mode 		*/
/* 	[2] 	MAC transmit interrupt enable after transmission	*/
/* 		of this frame (T) 					*/
/* 		0 = Disable 		1 = Enable			*/
/* 	[3] 	Little-Endian mode (L)					*/
/* 		0 = Big-endian 		1 = Little-endian		*/
/* 	[4] 	Frame data pointer increment/decrement (A)		*/
/* 		0 = Decrement 		1 = Increment			*/
/* 	[6:5] 	Widget alignment control (WA)				*/
/* 		(Non-aligned data must be transmitted without alignment */
/* 	 	 control.)						*/
/* 		00 = No invalid bytes 	01 = One invalid byte		*/
/* 		10 = Two invalid bytes	11 = Three invalid bytes	*/
/* 	[15:0]	Frame length						*/
/* 		The size of the transmit frame.				*/
/* 	[31:16] Tx status						*/
/* 		This Tx frame status field is updated by the MAC after 	*/
/* 		transmission.						*/
/* 	[31:0]	Next frame descriptor pointer				*/
/* 		The address of the next frame descriptor.		*/
/************************************************************************/

// Tx Frame Descriptor's control bits
#define	TXFDCTRL_PaddingMode	     0x00 // Padding mode 
#define	TXFDCTRL_NoPaddingMode	     0x01 // No-padding mode
#define	TXFDCTRL_NoCRCMode	     0x02 // No-CRC mode
#define	TXFDCTRL_CRCMode	     0x00 // CRC mode
#define	TXFDCTRL_MACTxIntEn	     0x04 // transmit interrupt enable after transmission
#define	TXFDCTRL_LittleEndian	     0x08 // Little-endian 
#define	TXFDCTRL_BigEndian	     0x00 // Big-endian 
#define	TXFDCTRL_SourceAddrDecrement 0x00 // Frame data pointer decrement
#define	TXFDCTRL_SourceAddrIncrement 0x10 // Frame data pointer increment
// 
#define	TXFDCTRL_WidgetAlign00	     0x00 // No Invalid bytes
#define	TXFDCTRL_WidgetAlign01	     0x20 // 1 Invalid byte
#define	TXFDCTRL_WidgetAlign10	     0x40 // 2 Invalid bytes
#define	TXFDCTRL_WidgetAlign11	     0x60 // 3 Invalid bytes

/************************************************************************/
/*[19:16]Transmit collision count (TxCollCnt)				*/
/* 3:0   Count of collisions during transmission of a single packet. 	*/
/* 	 After 16 collisions, TxColl is zero, and ExColl is set. 	*/
/*[20]   Excessive collision (ExColl)					*/
/*  4    16 collisions occured in the same packet. 			*/
/*[21] 5 Transmit deferred (TxDefer) 					*/
/*[22] 6 Paused 							*/
/*[23]   Interrupt on transmit (IntTx) 					*/
/*  7    Set if transmission of packet caused an interrupt condition. 	*/
/*       This includes the enable completion (EnComp), MACTXCON [14],   */
/*       if enabled. 							*/
/*[24]   Underrun (Under)						*/
/*  8    MAC transmit FIFO becomes empty during transmission.		*/
/*[25]   Deferral (Defer) 						*/
/*  9    MAC defers for max_deferral 0.32768 ms for 100 M bits/s or 	*/
/*       3.27680 ms for 10 M bits/s. 					*/
/*[26]   No carrier (NCarr) 						*/
/* 10	 Carrier sense is not detected during the entire transmission 	*/
/*       of a packet (from the SFD to the CRC). 			*/
/*[27]   SQE error (SQErr) 						*/
/* 11    After transmit frame, set if the fake collision (COL) signal 	*/
/*       did not come from the PHY for 1.6 ms. 				*/
/*[28]   Late collision (LateColl) 					*/
/* 12    A collision occurred after 512 bit times (64 byte times). 	*/
/*[29]   Transmit parity error (TxPar) 					*/
/* 13	 MAC transmit FIFO detected a parity error. 			*/
/*[30]   Completion (Comp) 						*/
/* 14    MAC completed a transmit or discard of one packet. 		*/
/*[31]   Transmission halted (TxHalted) 				*/
/* 15    Transmission halted by clearing TxEn or setting the Haltlmm 	*/
/*       in the MAC control register. Or, an interrupt was generated 	*/
/* 	 by an error condition (not completion). 			*/
/************************************************************************/

// Tx Frame descriptor's Status

#define	TXFDST_CollCnt  0x000F	// Transmit collision count
#define	TXFDST_ExColl	0x0010	// Excessive Collision
#define	TXFDST_TxDeffer	0x0020	// Transmit deffered 
#define TXFDST_Paused	0x0040	// Paused : holding data transmission DMA to MAC
#define	TXFDST_IntTx	0x0080	// Interrupt on Transmit 
#define	TXFDST_Under	0x0100	// Underrun */
#define	TXFDST_Defer	0x0200	// Mac defers for Max_DEFERRAL:=0.32768ms 
				// for 100Mbits/s, := 3.2768ms for 10Mbits/s
#define	TXFDST_NCarr	0x0400	// No Carrier sense is detected during the 
				// entire transmission of a packet from SFD 
				// to CRC
#define	TXFDST_SQErr	0x0800	// fake collision signal didn't come from 
				// PHY for 1.6us.
#define TXFDST_LateColl	0x1000	// Late collision 
#define	TXFDST_TxPar	0x2000	// Transmit Parity Error
#define	TXFDST_Comp	0x4000	// MAC transmit or discards one packet
#define TXFDST_TxHalted	0x8000	// Transmission was halted by clearing TxEn..

////////////////////////////////////////////////////////////////////////////////
// MAC Frame Structure /////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////

typedef 
#ifndef __GNUC__ 
__packed 
#endif 								/* __GNUC__  */
struct ETH_HEADER {	
	U8 DestinationAddr[6];	// destination MAC address
	U8 SourceAddr[6];	// source MAC address	
	U8 LengthOrType[2];	// Length or Type
}