init_gnu.h

本source code 為s3c4510的bootloader

#define workDRAMCON1 (CAN1+workDRAMEndPtr1+workDRAMBasePtr1+Trp1+Trc1+Tcp1+Tcs1+dumy1+EDO_Mode1)    
/*----------------------------------------------------------------------*/
/* [7] RAS to CAS delay */
#define SRAS2CASDelay1              1   /* (Trc)0=1cycle,1=2cycle */
/* [9:8] RAS pre-charge time */
#define SRASPrechargeTime1          1   /* (Trp)0=1cycle ~ 3=4clcyle */
/* [31:30] Number of column address bits in DRAM bank 1*/
#define SNoColumnAddr1     	    0   /* 0=8bit,1=9bit,2=10bit,3=11bits */

#define SCAN1 (SNoColumnAddr1   <<30)
#define STrc1 (SRAS2CASDelay1    <<7)
#define STrp1 (SRASPrechargeTime1<<8)

#define initSDRAMCON1 (SCAN1+initDRAMEndPtr1+initDRAMBasePtr1+STrp1+STrc1)
#define workSDRAMCON1 (SCAN1+workDRAMEndPtr1+workDRAMBasePtr1+STrp1+STrc1)  		
/************************************************************************/
/* -> DRAMCON2:RAM Bank2 control register 				*/
/* 		Offset = 0x3034 					*/
/************************************************************************/
/*[0] EDO Mode : 0=Normal DRAM (Fast page mode DRAM), 1=EDO DRAM */
#define EDO_Mode2           	    0   /* (EDO)0=Normal, 1=EDO DRAM */
/*[2:1] CAS strobe time : 00=1 cycle, 01=2 cycles, 10=3 cycles, 11=4 cycles */
#define CasStrobeTime2    	    1   /* (Tcs)0=1cycle ~ 3=4cycle */
/*[3] CAS precharge time*/
#define CasPrechargeTime2  	    0   /* (Tcp)0=1cycle,1=2cycle */
/*[6:4]Reserved : This bits default value is 000. But, you must set to 001  */
#define DRAMCON2Reserved   	    1   /* Must be set to 1 */
/*[7] RAS to CAS delay */
#define RAS2CASDelay2    	    0   /* (Trc)0=1cycle,1=2cycle */
/*[9:8] RAS pre-charge time */
#define RASPrechargeTime2  	    0   /* (Trp)0=1cycle ~ 3=4clcyle */
/*[19:10] DRAM bank 2 base pointer */
#define initDRAMBasePtr2  (0x240<<10)
/*[29:20] DRAM bank 2 Next pointer */
#define initDRAMEndPtr2   (0x280<<20)         	
#define workDRAMBasePtr2  (0x140<<10)/*=0x14000000 */
#define workDRAMEndPtr2   (0x180<<20)/*=0x18000000 */
/*[31:30] Number of column address bits in DRAM bank 2 */
#define NoColumnAddr2  	  	    2   /* 0=8bit,1=9bit,2=10bit,3=11bits */
/*----------------------------------------------------------------------*/
#define Tcs2   (CasStrobeTime2   <<1)   /* CAS strobe time */
#define Tcp2   (CasPrechargeTime2<<3)   /* CAS precharge time */ 
#define dumy2  (DRAMCON2Reserved <<4)   /* dummy cycle */
#define Trc2   (RAS2CASDelay2    <<7)   /* RAS to CAS delay */ 
#define Trp2   (RASPrechargeTime2<<8)   /* RAS precharge time */
#define CAN2   (NoColumnAddr2   <<30)   /* Number of column address bits */ 

#define initDRAMCON2	(CAN2+initDRAMEndPtr2+initDRAMBasePtr2+Trp2+Trc2+Tcp2+Tcs2+dumy2+EDO_Mode2)
#define workDRAMCON2	(CAN2+workDRAMEndPtr2+workDRAMBasePtr2+Trp2+Trc2+Tcp2+Tcs2+dumy2+EDO_Mode2)
/*----------------------------------------------------------------------*/
/* [7] RAS to CAS delay */
#define SRAS2CASDelay2              1   /* (Trc)0=1cycle,1=2cycle */
/* [9:8] RAS precharge time */
#define SRASPrechargeTime2  	    1   /* (Trp)0=1cycle ~ 3=4clcyle */
/* [31:30]Number of column address bits */
#define SNoColumnAddr2              0   /* 0=8bit,1=9bit,2=10bit,3=11bits */

#define SCAN2 (SNoColumnAddr2   <<30)
#define STrc2 (SRAS2CASDelay2    <<7)
#define STrp2 (SRASPrechargeTime2<<8)

#define initSDRAMCON2	(SCAN2+initDRAMEndPtr2+initDRAMBasePtr2+STrp2+STrc2)
#define workSDRAMCON2	(SCAN2+workDRAMEndPtr2+workDRAMBasePtr2+STrp2+STrc2)
/*----------------------------------------------------------------------*/

/************************************************************************/
/* -> DRAMCON3:RAM Bank3 control register 				*/
/* 		Offset = 0x3038 					*/
/************************************************************************/
/*----------------------------------------------------------------------*/ 
/*[0] EDO Mode: 0=Normal DRAM (Fast page mode DRAM), 1=EDO DRAM */
#define EDO_Mode3          	    0   /* (EDO)0=Normal, 1=EDO DRAM */
/*[2:1] CAS strobe time : 00=1 cycle,01=2 cycles, 10=3 Cycles, 11=4 cycles*/
#define CasStrobeTime3     	    1   /* (Tcs)0=1cycle ~ 3=4cycle */
/*[3]CAS pre-charge time*/
#define CasPrechargeTime3    	    0   /* (Tcp)0=1cycle,1=2cycle */
/*[6:4] Rseserved. This value is set 000. But, you must set to 001*/
#define DRAMCON3Reserved   	    1   /* Must be set to 1 */
/*[7] RAS to CAS delay */
#define RAS2CASDelay3               0   /* (Trc)0=1cycle,1=2cycle */
/*[9:8] RAS pre-charge time : 00=1 cycle, 01=2 cycles, 10=3 cycles, 11=4 cycles */
#define RASPrechargeTime3  	    0   /* (Trp)0=1cycle ~ 3=4clcyle */
#define initDRAMBasePtr3  (0x280<<10)   /*[19:10]DRAM bank 3 base pointer */
#define initDRAMEndPtr3   (0x2C0<<20)   /*[29:20] DRAM bank 3 Next pointer*/
#define workDRAMBasePtr3  (0x180<<10)
#define workDRAMEndPtr3   (0x1C0<<20)  

/*[31:30] Number of column address bits in DRAM bank 3*/
#define NoColumnAddr3        	    2   /* 0=8bit,1=9bit,2=10bit,3=11bits */
/*----------------------------------------------------------------------*/
#define Tcs3      (CasStrobeTime3<<1)
#define Tcp3   (CasPrechargeTime3<<3)
#define dumy3   (DRAMCON3Reserved<<4)	/* dummy cycle */
#define Trc3       (RAS2CASDelay3<<7)
#define Trp3   (RASPrechargeTime3<<8)
#define CAN3      (NoColumnAddr3<<30)
/* */
#define initDRAMCON3 (CAN3+initDRAMEndPtr3+initDRAMBasePtr3+Trp3+Trc3+Tcp3+Tcs3+dumy3+EDO_Mode3)
#define workDRAMCON3 (CAN3+workDRAMEndPtr3+workDRAMBasePtr3+Trp3+Trc3+Tcp3+Tcs3+dumy3+EDO_Mode3)

/*----------------------------------------------------------------------*/
/*[7] RAS to CAS delay */
#define SRAS2CASDelay3              1   /* (Trc)0=1cycle,1=2cycle */
/*[9:8] RAS pre-charge time*/
#define SRASPrechargeTime3          1   /* (Trp)0=1cycle ~ 3=4clcyle */
/*[31:30] Number of column address bits in DRAM bank 3*/
#define SNoColumnAddr3              0   /* 0=8bit,1=9bit,2=10bit,3=11bits */

#define SCAN3    (SNoColumnAddr3<<30)
#define STrc3     (SRAS2CASDelay3<<7)
#define STrp3 (SRASPrechargeTime3<<8)
/* */
#define initSDRAMCON3 (SCAN3+initDRAMEndPtr3+initDRAMBasePtr3+STrp3+STrc3)
#define workSDRAMCON3 (SCAN3+workDRAMEndPtr3+workDRAMBasePtr3+STrp3+STrc3)
/*----------------------------------------------------------------------*/

/************************************************************************/
/* ->REFEXTCON:External I/O & Memory Refresh cycle Control Register 	*/
/* 		Offset = 0x303C 					*/
/************************************************************************/
/***********************************************************************/
/*[9-0] 	External I/O bank 0 base pointer (base address)		*/
/*[15] 	Validity of special register field (VSF)			*/
/*		0 = No accessible to memory bank			*/
/*		1 = Accessible to memory bank				*/
/*[16] 	Refresh enable (REN)						*/
/*		0 = Disable DRAM refresh				*/
/*		1 = Enable DRAM refresh					*/
/*[19:17] 	CAS hold time (tCHR)					*/
/*		ROW Cycle Time (tRC) (note 1)				*/
/*		000=1 cycle	001=2 cycles				*/
/*		010=3 cycles	011=4 cycles				*/
/*		100=5 cycles	101=Not Used (6 cycles)			*/
/*	110=Not used	111=Not Used 					*/
/*									*/
/*		NOTE 1: In EDO/normal DRAM mode, CAS hold time		*/
/*		can bee programmed upto 5 cycles.			*/
/*		But in SDRAM mode, this bit fields 			*/
/*		function are defined as ROW Cycle			*/
/*		Time (tRC) and can be programmed up			*/
/*		to 6 cycles.						*/
/*[20] 	CAS setup time (tCSR) (note 2)					*/
/*		0=1 cycle						*/
/*		1=2 cycles						*/
/*     									*/
/*      	NOTE 2: In SDRAM mode, this bit field is 		*/
/*      		reserved.					*/
/*[31:21] 	Refresh count value (duration) 				*/
/*		The refresh period is calculated as 			*/
/* 		(2**11 - Value + 1) fMCLK				*/
/************************************************************************/

#define RefCycle                   16   /* Unit [us], 1k refresh 16ms */
#define CASSetupTime                0   /* 0=1cycle, 1=2cycle */
#define CASHoldTime                 0   /* 0=1cycle, 1=2cycle, 2=3cycle, */
                        	        /* 3=4cycle, 4=5cycle */

#define RefCycleValue   ((2048+1-(RefCycle*fMCLK)) << 21)

#define Tcsr     (CASSetupTime << 20)   /* 1 cycle */
#define Tcs      (CASHoldTime  << 17)   /* 1 cycle */
#define ExtIOBase             0x18360   /* Refresh enable, VSF=1 */

/*    1    8    3    6    0 */
/* 0001 1000 0011 0110 0000 */
/*    6 5432 1098 7654 3210 */
/* External Base 	= 0x360 => 0x360 0000  */
/* [15] VSF 		= 1 */
/* [16] Refresh enable 	= 1 */
#define rREFEXTCON       (RefCycleValue+Tcsr+Tcs+ExtIOBase)
/*----------------------------------------------------------------------*/
#define SRefCycle                  16   /* Unit [us], 4k refresh 64ms */
/* ROW Cycle time */
#define ROWcycleTime      	    4   /* 0=1cycle, 1=2cycle, 2=3cycle, */
                        		/* 3=4cycle, 4=5cycle, */
/* */
#define SRefCycleValue  ((2048+1-(SRefCycle*fMCLK))<<21)
#define STrc            (ROWcycleTime<<17) 
/* */   
#define rSREFEXTCON     (SRefCycleValue+STrc+ExtIOBase)
/*----------------------------------------------------------------------*/

/************************************************************************/
/* KS32C50100 SPECIAL REGISTERS                                         */
/************************************************************************/

#define ASIC_BASE  	    0x3ff0000

/* I/O Port Interface */
#define IOPMOD	   (ASIC_BASE+0x5000)	/* I/O port mode register */
/*Reset value=0x00000000 (All I/O port pins - inputs)				*/
/*[ 0] I/O port mode bit for port 0						*/
/*[17] I/O port mode bit for port 0						*/
/*	0=Input									*/
/*	1=Output								*/
#define IOPCON     (ASIC_BASE+0x5004)	/* I/O port control register 	*/
#define IOPDATA    (ASIC_BASE+0x5008)	/* I/O port data register 	*/

/*  UART SPECIAL REGISTERS 0,1  */
#define UARTLCON0  (ASIC_BASE+0xD000)	/* UART0 Line Control register */
#define UARTCONT0  (ASIC_BASE+0xD004)	/* UART0 Control register */
#define UARTSTAT0  (ASIC_BASE+0xD008)	/* UART0 status register */
#define UARTTXH0   (ASIC_BASE+0xD00C)	/* UART0 transmit buffer register */
#define UARTRXB0   (ASIC_BASE+0xD010)	/* UART0 receive buffer register */
#define UARTBRD0   (ASIC_BASE+0xD014)	/* UART0 baud rate divisor register */

#define UARTLCON1  (ASIC_BASE+0xE000)	/* UART 1 Line Control register */
#define UARTCONT1  (ASIC_BASE+0xE004)	/* UART 1 Control register */
#define UARTSTAT1  (ASIC_BASE+0xE008)	/* UART 1 Status register */
#define UARTTXH1   (ASIC_BASE+0xE00C)	/* UART 1 transmit buffer register */
#define UARTRXB1   (ASIC_BASE+0xE010)	/* UART 1 receiver buffer register */
#define UARTBRD1   (ASIC_BASE+0xE014)	/* UART 1 baud rate divisor */

#define UCON0  	   (ASIC_BASE+0xD000)	/* UART0 control register s3C4530 */
#define USTAT0	   (ASIC_BASE+0xD004)	/* UART0 status register s3C4530 */
#define UCON1  	   (ASIC_BASE+0xE000)	/* UART1 control register s3C4530  */
#define USTAT1	   (ASIC_BASE+0xE004)	/* UART1 status register s3C4530 */
/************************************************************************/