init_gnu.h

本source code 為s3c4510的bootloader

                    	  		/* 0x2=8Word Page, 0x3=16Word Page */
/* Page address access time */
#define rTpa1                (0x0<<2)   /* 0x0=5Cycle, 0x1=2Cycle	; 5 Cycles  */
                                        /* 0x2=3Cycle, 0x3=4Cycle  */
/* Programmable access cycle */
#define rTacc1               (0x6<<4)   /* 0x0=Disable, 0x1=2Cycle ; 7 Cycles */
                                        /* 0x2=3Cycle, 0x3=4Cycle */
                                        /* 0x4=5Cycle, 0x5=6Cycle */
                                        /* 0x6=7Cycle, 0x7=Reserved */

#define initROMCON1     (initROMEndPtr1+initROMBasePtr1+rTacc1+rTpa1+PMC1)
#define workROMCON1     (workROMEndPtr1+workROMBasePtr1+rTacc1+rTpa1+PMC1)

/************************************************************************/
/* -> ROMCON2 :ROM Bank2 Control register 				*/
/*		Offset Address = 0x301C Reset Value    = 0x00000060) 	*/
/************************************************************************/
#define initROMBasePtr2   (0x040<<10)	/*=0x0400000 ;  4 */ 
#define initROMEndPtr2    (0x060<<20)	/*=0x0600000 ;  6 */
#define workROMBasePtr2   (0x240<<10)	/*=0x2400000 ; 36 */ 
#define workROMEndPtr2    (0x260<<20)	/*=0x2600000 ; 38 */

/* Page Mode Configuration */
#define PMC2                      0x0   /* 0x0=Normal ROM, 0x1=4Word Page; Normal */
                        	        /* 0x2=8Word Page, 0x3=16Word Page */
/* Page Access Time */
#define rTpa2                (0x0<<2)   /* 0x0=5Cycle, 0x1=2Cycle	; 5 Cycles */
                              		/* 0x2=3Cycle, 0x3=4Cycle */
/* Programmable access cycle */
#define rTacc2             (0x6 << 4)   /* 0x0=Disable, 0x1=2Cycle */
                                	/* 0x2=3Cycle, 0x3=4Cycle	; 7 Cycles */
                                	/* 0x4=5Cycle, 0x5=6Cycle */
                                	/* 0x6=7Cycle, 0x7=Reserved */

#define initROMCON2     (initROMEndPtr2+initROMBasePtr2+rTacc2+rTpa2+PMC2)
#define workROMCON2     (workROMEndPtr2+workROMBasePtr2+rTacc2+rTpa2+PMC2)

/************************************************************************/
/* -> ROMCON3 :ROM Bank3 Control register				*/
/* 		Offset Address = 0x3020	Reset Value    = 0x00000060)	*/
/************************************************************************/
#define initROMBasePtr3   (0x060<<10)   /*=0x0600000 ;  6 */
#define initROMEndPtr3    (0x080<<20)   /*=0x0800000 ;  8 */
#define workROMBasePtr3   (0x260<<10)   /*=0x2600000 ; 38 */
#define workROMEndPtr3    (0x280<<20)   /*=0x2800000 ; 40 */
/* Page Mode Configuration */
#define PMC3                      0x0   /* 0x0=Normal ROM, 0x1=4Word Page */
                              	        /* 0x2=8Word Page, 0x3=16Word Page */
/* Page Access Time */
#define rTpa3                (0x0<<2)   /* 0x0=5Cycle, 0x1=2Cycle */
                                        /* 0x2=3Cycle, 0x3=4Cycle */
/* Programmable access cycle */
#define rTacc3               (0x0<<4)   /* 0x0=Disable, 0x1=2Cycle ; Disable */
                                        /* 0x2=3Cycle, 0x3=4Cycle */
                                        /* 0x4=5Cycle, 0x5=6Cycle */
                                        /* 0x6=7Cycle, 0x7=Reserved */

#define initROMCON3     (initROMEndPtr3+initROMBasePtr3+rTacc3+rTpa3+PMC3)
#define workROMCON3     (workROMEndPtr3+workROMBasePtr3+rTacc3+rTpa3+PMC3)

/************************************************************************/
/* -> ROMCON4 :ROM Bank4 Control register				*/
/*		Offset Address = 0x3024 Reset  Value   = 0x00000060  	*/
/************************************************************************/
#define initROMBasePtr4   (0x080<<10)   /*=0x0800000 ;  8 ; Disable */
#define initROMEndPtr4    (0x0A0<<20)   /*=0x0A00000 ; 10 */	
#define workROMBasePtr4   (0x280<<10)   /*=0x2800000 ; 40 */
#define workROMEndPtr4    (0x2A0<<20)   /*=0x2A00000 ; 42 */	
/* Page Mode Configuration */ 
#define PMC4                    (0x0)   /* 0x0=Normal ROM, 0x1=4Word Page */
                                        /* 0x2=8Word Page, 0x3=16Word Page */
/* Page Access Time */
#define rTpa4                (0x0<<2)   /* 0x0=5Cycle, 0x1=2Cycle */
                                        /* 0x2=3Cycle, 0x3=4Cycle */ 
/* Programmable access cycle */
#define rTacc4               (0x0<<4)   /* 0x0=Disable, 0x1=2Cycle ; Disable */
                                        /* 0x2=3Cycle, 0x3=4Cycle */
                                        /* 0x4=5Cycle, 0x5=6Cycle */
                                        /* 0x6=7Cycle, 0x7=Reserved */

#define initROMCON4     (initROMEndPtr4+initROMBasePtr4+rTacc4+rTpa4+PMC4)
#define workROMCON4     (workROMEndPtr4+workROMBasePtr4+rTacc4+rTpa4+PMC4)

/************************************************************************/
/* -> ROMCON5 :ROM Bank5 Control register 				*/
/*		Offset Address = 0x3028	Reset Value = 0x00000060 	*/
/************************************************************************/
#define initROMBasePtr5   (0x0A0<<10)   /* =0x0A00000 ; 10 ; Disable */
#define initROMEndPtr5    (0x0C0<<20)   /* =0x0C00000 ; 12 */
#define workROMBasePtr5   (0x2A0<<10)   /* =0x2A00000 ; 42 */
#define workROMEndPtr5    (0x2C0<<20)   /* =0x2C00000 ; 44 */

/* Page Mode Configuration */
#define PMC5                    (0x0)   /* 0x0=Normal ROM, 0x1=4Word Page */ 
                                        /* 0x2=8Word Page, 0x3=16Word Page */
/* Page Access Time */
#define rTpa5                (0x0<<2)   /* 0x0=5Cycle, 0x1=2Cycle */
                                        /* 0x2=3Cycle, 0x3=4Cycle */ 
/* Programmable access cycle */
#define rTacc5               (0x0<<4)   /* 0x0=Disable, 0x1=2Cycle ; Disable */
                                        /* 0x2=3Cycle, 0x3=4Cycle */
                                        /* 0x4=5Cycle, 0x5=6Cycle */
                                        /* 0x6=7Cycle, 0x7=Reserved */

#define initROMCON5     (initROMEndPtr5+initROMBasePtr5+rTacc5+rTpa5+PMC5)
#define workROMCON5     (workROMEndPtr5+workROMBasePtr5+rTacc5+rTpa5+PMC5)

/************************************************************************/
/* -> DRAMCON0 :RAM Bank0 control register     				*/
/* 		Offset      = 0x302C Reset Value = 0x0000 0000		*/
/*									*/
/*[0]		EDO mode 						*/
/*		0 = Normal DRAM (Fast page mode DRAM)			*/
/*		1 = EDO DRAM						*/
/*									*/
/*[2:1]	CAS strobe time	(tCS)						*/
/*		00 = 1 cycle	01 = 2 cycles				*/
/*		10 = 3 cycles	11 = 4 cycles				*/
/*									*/
/*[3:3]	CAS pre-charge time (tCP)					*/
/*		0 = 1 cycle	1 = 2 cycles				*/
/*									*/
/*[6:4]	Reserved							*/
/*									*/
/*[7]		RAS to CAS delay (tRC)					*/
/*		0 = 1 cycle	1 = 2 cycle 				*/
/*									*/
/*[9:8]	RAS pre-charge time (tRP)					*/
/*		00 = 1 cycle	01 = 2 cycles				*/
/*		10 = 3 cycles	11 = 4 cycles				*/
/*									*/
/*[19:10]	DRAM bank base pointer 					*/
/*[29:20]	DRAM bank next pointer 					*/
/*									*/
/*[31:30]	Number of column address bits in DRAM bank 		*/
/*		00 = 8 bits	01 = 9 bits				*/
/*		10 = 10 bits	11 = 11 bits				*/
/************************************************************************/
/* EDO Mode [0] (note: in SDRAM mode, this bit affect SDRAM cycle)*/
#define EDO_Mode0                   1   /*(EDO)0=Normal (Fast page mode DRAM), 1=EDO DRAM */
/* CAS strobe time */
#define CasStrobeTime0              1   /*(Tcs)0=1cycle,1=2cycles,2=3cycles,3=4cycle*/
/* CAR pre-charge time (note: in SDRAM mode, this bit affect SDRAM cycle)*/
#define CasPrechargeTime0           0   /*(Tcp)0=1cycle,1=2cycle */
/* Reserved */
#define DRAMCON0Reserved            1   /* Must be set to 1 */
/* RAS to CAS delay */
#define RAS2CASDelay0               0   /*(Trc)0=1cycle,1=2cycle */
/* RAS pre-charge time */
#define RASPrechargeTime0           2   /*(Trp)0=1cycle ~ 3=4clcyle */
/* DRAM bank base pointer */
#define initDRAMBasePtr0  (0x100<<10)	/*=0x1000000 ; 16 */
/* DRAM bank Next pointer */
#define initDRAMEndPtr0   (0x200<<20)	/*=0x2000000 ; 32 */
#define workDRAMBasePtr0  (0x000<<10)	/*=0x0000000 ;  0 */ 
#define workDRAMEndPtr0   (0x100<<20) 	/*=0x1000000 ; 16 */
#define NoColumnAddr0               2   /* 0=8bit,1=9bit,2=10bit,3=11bits */
/* NOTE : in SDRAM mode, this bit affect SDRAM cycle. */
/*        tCS value[1]: 0 = 1 cycle, 1=2 cycle */

#define Tcs0  (CasStrobeTime0   << 1)	/* CAS strobe time */		
#define Tcp0  (CasPrechargeTime0<< 3)	/* CAS pre-charge time */
#define dumy0 (DRAMCON0Reserved << 4) 	/* dummy cycle */
#define Trc0  (RAS2CASDelay0    << 7)	/* RAS to CAS delay */
#define Trp0  (RASPrechargeTime0<< 8)	/* RAS pre-charge time */
#define CAN0  (NoColumnAddr0    <<30)	/* Number of cilumn address bits */

#define initDRAMCON0 (CAN0+initDRAMEndPtr0+initDRAMBasePtr0+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0)
#define workDRAMCON0 (CAN0+workDRAMEndPtr0+workDRAMBasePtr0+Trp0+Trc0+Tcp0+Tcs0+dumy0+EDO_Mode0)
/*----------------------------------------------------------------------*/
/* SDRAM Bank 0 settings */
/* [7] Ras to CAS Delay */
#define SRAS2CASDelay0  	    0   /* (Trc)0=1cycle,1=2cycle */
/* [9:8] RAS pre-charge time 00=1 cycle, 01=2 cycles, 10=3 cycles, 11=4 cycles*/
#define SRASPrechargeTime0 	    1   /* (Trp)0=1cycle ~ 3=4clcyle */
/* [31:30] Number of column address bits in DRAM bank 0*/
#define SNoColumnAddr0    	    0   /* 0=8bit,1=9bit,2=10bit,3=11bits */
/* HY57V651620B */
/* - Row Address: RA0-RA11, Column Address: CA0-CA7 */
/* - Programmable Burst Length and Burst Type*/
/* 	- 1,2,4,8 or Full page for Sequential Burst */
/* 	- 1,2,3,4 for Interleave Burst */
/* - Programmable CAS Latensy : 2,3 Clocks */

#define STrc0 (SRAS2CASDelay0    <<7)	/* RAS to CAS Delay */
#define STrp0 (SRASPrechargeTime0<<8)	/* RAS pre-charge time */
#define SCAN0 (SNoColumnAddr0  << 30)	/* Number of column address bits */ 

#define initSDRAMCON0 (SCAN0+initDRAMEndPtr0+initDRAMBasePtr0+STrp0+STrc0+dumy0)
#define workSDRAMCON0 (SCAN0+workDRAMEndPtr0+workDRAMBasePtr0+STrp0+STrc0+dumy0)
/************************************************************************/
/* -> DRAMCON1:RAM Bank1 control register 				*/
/* 		Offset      = 0x3030 Reset Value = 0x00000000		*/
/************************************************************************/
/* [0] EDO mode: 0=Normal EDO (Fast page mode DRAM), 1=EDO DRAM */
#define EDO_Mode1                   1   /* (EDO)0=Normal, 1=EDO DRAM */
/* [2:1] CAS strobe time: 00=1 cycle, 01=2 cycles, 10=3 cycles, 11=4 cycles */
#define CasStrobeTime1              1   /* (Tcs)0=1cycle ~ 3=4cycle */
/* [3:3] CAS pre-charge time: 0=1 cycle, 1=2 cycles*/
#define CasPrechargeTime1  	    0   /* (Tcp)0=1cycle,1=2cycle */
/* [6:4] This bits default value is 000. But, you must set to 001 */
#define DRAMCON1Reserved   	    1   /* Must be set to 1 */
/* [7]   RAS to CAS delay : 0=1cycle. 1=2 cycles */
#define RAS2CASDelay1               0   /* (Trc)0=1cycle,1=2cycle */
/* [9:8] RAS pre-charge time : 00=1 cycle, 01=2 cycles, 10=3 cycles, 11=4 cycles*/
#define RASPrechargeTime1     	    0   /* (Trp)0=1cycle ~ 3=4clcyle */
#define initDRAMBasePtr1  (0x200<<10)   /* [19:10] DRAM bank 1 base pointer */ 
#define initDRAMEndPtr1   (0x240<<20)   /* [29:20] DRAM bank 1 Next pointer */
#define workDRAMBasePtr1  (0x100<<10) 
#define workDRAMEndPtr1   (0x140<<20) 
/* [31:30] Number of column address bits in DRAM bank 1 */
#define NoColumnAddr1              2    /* 0=8bit,1=9bit,2=10bit,3=11bits */
/*----------------------------------------------------------------------*/
#define Tcs1   (CasStrobeTime1   <<1)	/* CAS strobe time */
#define Tcp1   (CasPrechargeTime1<<3)	/* CAS pre-charge time */
#define dumy1  (DRAMCON1Reserved <<4) 	/* dummy cycle */
#define Trc1   (RAS2CASDelay1    <<7)	/* RAS to CAS delay */ 
#define Trp1   (RASPrechargeTime1<<8)	/* RAS pre-charge time */ 
#define CAN1   (NoColumnAddr    <<30)	/* Number of column address bits in DRAM bank 1 */

#define initDRAMCON1 (CAN1+initDRAMEndPtr1+initDRAMBasePtr1+Trp1+Trc1+Tcp1+Tcs1+dumy1+EDO_Mode1)