init_gnu.h

本source code 為s3c4510的bootloader

/*************************************************************************/
/*                                                                       */
/* FILE NAME                                      VERSION                */
/*                                                                       */
/* snds.a                                 SNDS100 Board version 1.0      */
/*                                                                       */
/* COMPONENT                                                             */
/*                                                                       */
/* DESCRIPTION                                                           */
/*                                                                       */
/*     SNDS100 for KS32C5000, KS32C50100 ASSEBLER SYSTEM HEADER FILE     */
/*                                                                       */
/* AUTHOR                                                                */
/*                                                                       */
/*      Young Sun KIM, Samsung Electronics, Inc.                         */
/*                                                                       */
/* DATA STRUCTURES                                                       */
/*                                                                       */
/*                                                                       */
/* FUNCTIONS                                                             */
/*                                                                       */
/* DEPENDENCIES                                                          */
/*                                                                       */
/*                                                                       */
/* HISTORY                                                               */
/*                                                                       */
/*         NAME            DATE                    REMARKS               */
/*                                                                       */
/*      Young Sun KIM   09-25-1998      Created initial version 1.0      */
/*************************************************************************/

/* 			*/
/* Modified by 		*/
/* Dmitriy Cherkashin 	*/
/* [e-mail]	*/
/* 2002,2003,2004	*/
/*/			*/

/************************************************************************/
/* Format of the Program Status Register                                */
/************************************************************************/
/*                                                                      */
/* 31  30  29   28         7   6   5   4   3   2   1   0                */
/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+              */
/*| N | Z | C | V |      | I | F | T |     M4 ~ M0       |              */
/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+              */
/* 									*/	 
/* 7:0 	(C)onftrol bits						  	*/ 
/* 15:8   	e(X)tension bits					*/
/* 23:16	(S)tatus bits						*/
/* 31:24	(F)lag bits						*/  
/*                                                                      */
/************************************************************************/

/************************************************************************/
/* Processor Mode and Mask                                              */
/************************************************************************/
#define FBit	     	         0x40   /* FIQ &=0x */
#define IBit	                 0x80   /* IRQ */
#define LOCK_MASK                0xC0   /* Interrupt lockout mask value */
#define MODE_MASK                0x1F   /* Processor Mode Mask */

#define UDF_MODE                 0x1B   /* Undefine Mode(UDF) */
#define ABT_MODE                 0x17   /* Abort Mode(ABT) */
#define SUP_MODE                 0x13   /* Supervisor Mode (SVC) */
#define IRQ_MODE                 0x12   /* Interrupt Mode (IRQ) */
#define FIQ_MODE                 0x11   /* Fast Interrupt Mode (FIQ) */
#define USR_MODE                 0x10   /* User Mode(USR) */

/*************************************************************************/
/* SYSTEM STACK MEMORY  : 8K bytes system stacks are defined at memory.a */
/*************************************************************************/
#ifdef LED_ONLY
#define DRAM_BASE           0x3FE0000   /* Internal SRAM */
#define DRAM_LIMIT          0x3FE2000   /* */
#define USR_STACK_SIZE            256   /* User stack size */ 
#define UDF_STACK_SIZE            128   /* Undefined mode stack size */
#define ABT_STACK_SIZE            128   /* Abort mode stack size */
#define IRQ_STACK_SIZE            128   /* IRQ mode stack size */
#define FIQ_STACK_SIZE            128   /* FIQ mode stack size */
#define SUP_STACK_SIZE            128   /* Supervisor mode stack size */
#else 
#define DRAM_BASE           0x1000000   /* Address of DRAM start byte */
#define DRAM_LIMIT          0x2000000   /* 16 Mbytes, next byte after DRAM */
#define USR_STACK_SIZE           2048   /* User stack size */ 
#define UDF_STACK_SIZE            512   /* Undefined mode stack size */
#define ABT_STACK_SIZE            512   /* Abort mode stack size */
#define IRQ_STACK_SIZE           2048   /* IRQ mode stack size */
#define FIQ_STACK_SIZE           2048   /* FIQ mode stack size */
#define SUP_STACK_SIZE           2048   /* Supervisor mode stack size */
#endif 							/* LED_ONLY */
    
/*************************************************************************/
/*  SYSTEM CLOCK                                                         */
/*************************************************************************/
#ifdef KS32C50100
#define fMCLK      	           50   /* System Clock MHz */
#else 
#define fMCLK     	           50   /* System Clock MHz */
#endif							/* KS32C50100 */
									
/************************************************************************/
/*  SYSTEM MEMORY CONTROL REGISTER EQU TABLES                           */
/************************************************************************/
 
/************************************************************************/
/* -> EXTDBWTH:Memory Bus Width register 				*/
/*		Offset = 0x3010, Reset Value = 0x0000000		*/
/* 									*/
/* [ 1: 0] DSR0 - Data bus width for ROM/SRAM/FLASH bank 0 		*/
/*									*/
/* DSR0 is read-only data at the B0SIZE[1:0] pins. DSR0 is read-only    */
/* because ROM/SRAM/FLASH bank 0 is used to boot the ROM while the	*/
/* data bus width for ROM/SRAM/FLASH bank 0 is set using B0SIZE[1:0]	*/
/* 									*/
/* [ 3: 2] DSR1 - Data bus width for ROM/SRAM/FLASH bank 1 		*/
/* [ 5: 4] DSR2 - Data bus width for ROM/SRAM/FLASH bank 2 		*/
/* [ 7: 6] DSR3 - Data bus width for ROM/SRAM/FLASH bank 3 		*/
/* [ 9: 8] DSR4 - Data bus width for ROM/SRAM/FLASH bank 4 		*/
/* [11:10] DSR5 - Data bus width for ROM/SRAM/FLASH bank 5 		*/
/*		   00 = Disable 					*/
/*		   01 = Byte (8 bits) 					*/
/*		   10 = Half-word (16 bits) 				*/
/*		   11 = Word (32 bits) 					*/
/*									*/
/* [13:12] DSD0 - Data bus width for DRAM bank 0 			*/
/* [15:14] DSD1 - Data bus width for DRAM bank 1 			*/
/* [17:16] DSD2 - Data bus width for DRAM bank 2 			*/
/* [19:18] DSD0 - Data bus width for DRAM bank 3 			*/
/*		   00 = Disable 					*/
/*		   01 = Byte (8 bits) 					*/
/*		   10 = Half-word (16 bits) 				*/
/*		   11 = Word (32 bits) 					*/
/*           								*/
/* [21:20] DSX0 - Data bus width for external I/O bank 0 		*/
/* [23:22] DSX1 - Data bus width for external I/O bank 1 		*/
/* [25:24] DSX2 - Data bus width for external I/O bank 2 		*/
/* [27:26] DSX0 - Data bus width for external I/O bank 3 		*/
/*		   00 = Disable 					*/
/*		   01 = Byte (8 bits) 					*/
/*		   10 = Half-word (16 bits) 				*/
/*		   11 = Word (32 bits) 					*/
/************************************************************************/
/* ROM/SRAM/FLASH */
#define DSR0  	               (2<<0)   /* ROM0 0 : Disable */
					/*      1 : Byte */
					/*      2 : Half-Word */
					/*      3 : Word */
#define DSR1  	              (0<< 2)   /* ROM1   : (Byte) */
#define DSR2  	              (0<< 4)   /* ROM2   : (Byte) */ 	
#define DSR3  	              (0<< 6)   /* ROM3   : (disable) */
#define DSR4  	              (0<< 8)   /* ROM4   : (disable) */
#define DSR5  	              (0<<10)   /* ROM5   : (disable) */
/* Data bus width for DRAM bank 0,1,2,3 */
#define DSD0  	              (3<<12)   /* DRAM0  : (Word) */  
#define DSD1  	              (0<<14)   /* DRAM1  : (disable) */
#define DSD2  	              (0<<16)   /* DRAM2  : (disable) */
#define DSD3  	              (0<<18)   /* DRAM3  : (disable) */
/* Data bus width for external I/O banks 0,1,2,3 */
#define DSX0  	              (0<<20)   /* EXTIO0 : (disable) */
#define DSX1  	              (0<<22)   /* EXTIO1 : (disable) */
#define DSX2  	              (0<<24)   /* EXTIO2 : (disable) */
#define DSX3  	              (0<<26)   /* EXTIO3 : (disable) */	

#define rEXTDBWTH   (DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3)
									
/************************************************************************/
/* -> ROMCON0 :ROM Bank0 Control register 				*/
/* 		Offset Address=0x3014, Reset Value=0x20000060		*/
/*									*/
/* [1:0] 	PCM Page mode configuration  				*/
/*		00 = Normal Rom 					*/
/*		01 = 4-word page 					*/
/*		10 = 8-word page 					*/
/*		11 = 16-word page					*/
/* [3:2]	tPA Page address access time 				*/
/*		00 = 5 cycles		01 = 2 cycles			*/
/*		10 = 3 cycles		11 = 4 cycles			*/
/*									*/
/* [6:4]	tACC Programmable access cycle 				*/
/* 		000= Disable bank 	001= 2 cycles			*/
/* 		010= 3 cycles		011= 4 cycles			*/
/* 		100= 5 cycles		101= 6 cycles			*/
/* 		110= 7 cycles		111= Reserved			*/
/* 									*/
/* [19:10]	ROM/SRAM/Flash bank base pointer 			*/
/* [29:20]	ROM/SRAM/Flash bank next pointer 			*/
/* 									*/
/************************************************************************/

#define initROMBasePtr0   (0x000<<10)   /* =0x0000000 ;  0 */
#define initROMEndPtr0    (0x020<<20)   /* =0x0200000 ;  2 */
#define workROMBasePtr0   (0x200<<10)   /* =0x2000000 ; 32 */
#define workROMEndPtr0    (0x220<<20)   /* =0x2200000 ; 34 */

/* Page Mode Configuration (PCM)*/
#define PMC0                      0x0   /* 0x0=Normal ROM, 0x1=4Word Page */ 
                            	        /* 0x2=8Word Page, 0x3=16Word Page */
/* Page address access time */ 
#define rTpa0                (0x0<<2)   /* 0x0=5Cycle, 0x1=2Cycle ; 5 Cycles */
                                        /* 0x2=3Cycle, 0x3=4Cycle */ 
/* Programmable access cycle */
#define rTacc0               (0x4<<4)   /* 0x0=Disable, 0x1=2Cycle	; */
                                        /* 0x2=3Cycle, 0x3=4Cycle */
                                        /* 0x4=5Cycle, 0x5=6Cycle */
                            	        /* 0x6=7Cycle, 0x7=Reserved */

#define initROMCON0     (initROMEndPtr0+initROMBasePtr0+rTacc0+rTpa0+PMC0)
#define workROMCON0     (workROMEndPtr0+workROMBasePtr0+rTacc0+rTpa0+PMC0)

/************************************************************************/
/* -> ROMCON1 :ROM Bank1 Control register 				*/
/*		Offset Address = 0x3018	Reset Value    = 0x00000060	*/
/************************************************************************/ 
#define initROMBasePtr1   (0x020<<10) /*=0x0200000 ;  2 */
#define initROMEndPtr1    (0x040<<20) /*=0x0400000 ;  4 */
#define workROMBasePtr1   (0x220<<10) /*=0x2200000 ; 34 */
#define workROMEndPtr1    (0x240<<20) /*=0x2400000 ; 36 */

/* Page Mode Configuration (PCM) */
#define PMC1                      0x0   /* 0x0=Normal ROM, 0x1=4Word Page ; Normal */