usbrx.c

基于dragon_MX1_ads的装载启动代码armboot

#include "../Include/type.h"
#include "../Include/mx1.h"

#define		USB_DISK_START		0x0B000000		// last 16M of SDRAM
#define 	DISK_LAST_SECTOR	0x00006FFF		// last sector of a 14M disk

U8 bootSector[512] = {
	0xEB,0x3C,0x90,0x4D,0x53,0x44,0x4F,0x53,0x35,0x2E,0x30,0x00,0x02,0x08,0x01,0x00,
	0x02,0x00,0x02,0x00,0x70,0xF8,0x0B,0x00,0x3F,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,
	0x00,0x00,0x00,0x00,0x00,0x00,0x29,0x8F,0x08,0x77,0xFE,0x4E,0x4F,0x20,0x4E,0x41,
	0x4D,0x45,0x20,0x20,0x20,0x20,0x46,0x41,0x54,0x31,0x32,0x20,0x20,0x20,0x33,0xC9,
	0x8E,0xD1,0xBC,0xF0,0x7B,0x8E,0xD9,0xB8,0x00,0x20,0x8E,0xC0,0xFC,0xBD,0x00,0x7C,
	0x38,0x4E,0x24,0x7D,0x24,0x8B,0xC1,0x99,0xE8,0x3C,0x01,0x72,0x1C,0x83,0xEB,0x3A,
	0x66,0xA1,0x1C,0x7C,0x26,0x66,0x3B,0x07,0x26,0x8A,0x57,0xFC,0x75,0x06,0x80,0xCA,
	0x02,0x88,0x56,0x02,0x80,0xC3,0x10,0x73,0xEB,0x33,0xC9,0x8A,0x46,0x10,0x98,0xF7,
	0x66,0x16,0x03,0x46,0x1C,0x13,0x56,0x1E,0x03,0x46,0x0E,0x13,0xD1,0x8B,0x76,0x11,
	0x60,0x89,0x46,0xFC,0x89,0x56,0xFE,0xB8,0x20,0x00,0xF7,0xE6,0x8B,0x5E,0x0B,0x03,
	0xC3,0x48,0xF7,0xF3,0x01,0x46,0xFC,0x11,0x4E,0xFE,0x61,0xBF,0x00,0x00,0xE8,0xE6,
	0x00,0x72,0x39,0x26,0x38,0x2D,0x74,0x17,0x60,0xB1,0x0B,0xBE,0xA1,0x7D,0xF3,0xA6,
	0x61,0x74,0x32,0x4E,0x74,0x09,0x83,0xC7,0x20,0x3B,0xFB,0x72,0xE6,0xEB,0xDC,0xA0,
	0xFB,0x7D,0xB4,0x7D,0x8B,0xF0,0xAC,0x98,0x40,0x74,0x0C,0x48,0x74,0x13,0xB4,0x0E,
	0xBB,0x07,0x00,0xCD,0x10,0xEB,0xEF,0xA0,0xFD,0x7D,0xEB,0xE6,0xA0,0xFC,0x7D,0xEB,
	0xE1,0xCD,0x16,0xCD,0x19,0x26,0x8B,0x55,0x1A,0x52,0xB0,0x01,0xBB,0x00,0x00,0xE8,
	0x3B,0x00,0x72,0xE8,0x5B,0x8A,0x56,0x24,0xBE,0x0B,0x7C,0x8B,0xFC,0xC7,0x46,0xF0,
	0x3D,0x7D,0xC7,0x46,0xF4,0x29,0x7D,0x8C,0xD9,0x89,0x4E,0xF2,0x89,0x4E,0xF6,0xC6,
	0x06,0x96,0x7D,0xCB,0xEA,0x03,0x00,0x00,0x20,0x0F,0xB6,0xC8,0x66,0x8B,0x46,0xF8,
	0x66,0x03,0x46,0x1C,0x66,0x8B,0xD0,0x66,0xC1,0xEA,0x10,0xEB,0x5E,0x0F,0xB6,0xC8,
	0x4A,0x4A,0x8A,0x46,0x0D,0x32,0xE4,0xF7,0xE2,0x03,0x46,0xFC,0x13,0x56,0xFE,0xEB,
	0x4A,0x52,0x50,0x06,0x53,0x6A,0x01,0x6A,0x10,0x91,0x8B,0x46,0x18,0x96,0x92,0x33,
	0xD2,0xF7,0xF6,0x91,0xF7,0xF6,0x42,0x87,0xCA,0xF7,0x76,0x1A,0x8A,0xF2,0x8A,0xE8,
	0xC0,0xCC,0x02,0x0A,0xCC,0xB8,0x01,0x02,0x80,0x7E,0x02,0x0E,0x75,0x04,0xB4,0x42,
	0x8B,0xF4,0x8A,0x56,0x24,0xCD,0x13,0x61,0x61,0x72,0x0B,0x40,0x75,0x01,0x42,0x03,
	0x5E,0x0B,0x49,0x75,0x06,0xF8,0xC3,0x41,0xBB,0x00,0x00,0x60,0x66,0x6A,0x00,0xEB,
	0xB0,0x4E,0x54,0x4C,0x44,0x52,0x20,0x20,0x20,0x20,0x20,0x20,0x0D,0x0A,0x4E,0x54,
	0x4C,0x44,0x52,0x20,0x69,0x73,0x20,0x6D,0x69,0x73,0x73,0x69,0x6E,0x67,0xFF,0x0D,
	0x0A,0x44,0x69,0x73,0x6B,0x20,0x65,0x72,0x72,0x6F,0x72,0xFF,0x0D,0x0A,0x50,0x72,
	0x65,0x73,0x73,0x20,0x61,0x6E,0x79,0x20,0x6B,0x65,0x79,0x20,0x74,0x6F,0x20,0x72,
	0x65,0x73,0x74,0x61,0x72,0x74,0x0D,0x0A,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xAC,0xBF,0xCC,0x55,0xAA
	};

	U32	gEPconfigData[55] = {
	// EP0
	0x00000000,
	0x00000000,
	0x00000008,
	0x00000000,
	0x00000000,
	// EP1
	0x00000014,		// EP#:1, CF#: 1, IF#:0
	0x00000014,		// BULK, IN
	0x00000020,		// MAX PS: 32
	0x000000C0,		// 0xC0, except for EP0
	0x00000001,		// FIFO#: 1
	// EP2
	0x00000024,		// EP#:2, CF#: 1, IF#:0
	0x00000010,		// BULK, OUT
	0x00000020,		// MAX PS: 32
	0x000000C0,		// 0xC0, except for EP0
	0x00000002,		// FIFO#: 2
	// EP3
	0x00000034,		// EP#:3, CF#: 1, IF#:0
	0x0000001C,		// INTR, IN
	0x00000010,		// MAX PS: 16
	0x000000C0,		// 0xC0, except for EP0
	0x00000003,		// FIFO#: 3
	// EP4
	0x00000044,		// EP#:4, CF#: 1, IF#:0
	0x00000018,		// INTR, OIUT
	0x00000010,		// MAX PS: 16
	0x000000C0,		// 0xC0, except for EP0
	0x00000004,		// FIFO#: 4
	// EP5
	0x00000054,		// EP#:5, CF#: 1, IF#:0
	0x0000001C,		// INTR, IN
	0x00000010,		// MAX PS: 16
	0x000000C0,		// 0xC0, except for EP0
	0x00000005,		// FIFO#: 5
	// EP6
	0x00000018,		// EP#:1, CF#: 2, IF#:0
	0x00000014,		// BULK, IN
	0x00000020,		// MAX PS: 32
	0x000000C0,		// 0xC0, except for EP0
	0x00000001,		// FIFO#: 1
	// EP7
	0x00000028,		// EP#:2, CF#: 2, IF#:0
	0x00000010,		// BULK, OUT
	0x00000020,		// MAX PS: 32
	0x000000C0,		// 0xC0, except for EP0
	0x00000002,		// FIFO#: 2
	// EP8
	0x00000038,		// EP#:3, CF#: 2, IF#:0
	0x0000001C,		// INTR, IN
	0x00000010,		// MAX PS: 16
	0x000000C0,		// 0xC0, except for EP0
	0x00000003,		// FIFO#: 3
	// EP9
	0x00000048,		// EP#:4, CF#: 2, IF#:0
	0x00000018,		// INTR, OIUT
	0x00000010,		// MAX PS: 16
	0x000000C0,		// 0xC0, except for EP0
	0x00000004,		// FIFO#: 4
	// EP10
	0x00000058,		// EP#:5, CF#: 2, IF#:0
	0x0000001C,		// INTR, IN
	0x00000010,		// MAX PS: 16
	0x000000C0,		// 0xC0, except for EP0
	0x00000005,		// FIFO#: 5
	};

U8  _gUsbDevReq[8];     /* device request from host */
const U32 _gUsbDevDscptr[5] = {
//    0x12011001, 0x00000008, 0xC40700A2, 0x00130000, 0x00000001 };		// assume big endian
    0x12011001, 0x00000008, 0xC4070000, 0x00130000, 0x00000001 };		// assume big endian
const U32 _gUsbConfDscptr[8] = {
//    0x09022000, 0x01010080, 0xFA090400, 0x00020806,
    0x09022000, 0x010100C0, 0x01090400, 0x00020806,
//    0x50000705, 0x81022000, 0x00070502, 0x02200000};
    0x50040705, 0x81022000, 0x00070502, 0x02200000};

P_U8	_gpUsbBufPtr;           // pointer to buffer data
U32   _gUsbNumSector;         // number of sector to read/write
U32   _gUsbCurSector;         // current sector being read/write
U32   _gUsbPacketCount;       // USB packet count
U8		_gCBW[31];					// command block wrapper

U8		quit;
U32	gLastSector;

void formatDrive()
{
	U32	i, j, k;
	U8		*p;

	p = (U8 *)USB_DISK_START;

	// write boot sector
	for (i=0; i<512; i++)
	{
		*(p++) = bootSector[i];
	}

	// write FAT (2 copies)
	for (i=0; i<2; i++)
	{
		*(p++) = 0xF8;
		*(p++) = 0xFF;
		*(p++) = 0xFF;
		for (j=3; j<512; j++)
			*(p++) = 0;
		for (j=1; j<11; j++)
			for (k=0; k<512; k++)
				*(p++) = 0;
	}

	// write directory entries
	for (i=0; i<32; i++)
		for (j=0; j<512; j++)
			*(p++) = 0;
}

/*
void delay(U32 count)
{
    U32 i;

    i = 0;
    while (i<count)
    {
        i++;
    }
}
*/
void initUSB()
{
	U8	i;

//	EUARTputString("Init USB module ...\n");

	// set clock for 48 MHz USB clock
	//_reg_CCM_CSCR = 0x47008403;
// PLAM
	_reg_CCM_CSCR &= ~USB_DIV_MASK;
	_reg_CCM_CSCR |= 0x04000000;	// set USB DIV to divide-by-2
// end PLAM	
	// config port for USBD
	_reg_PTB_GIUS &= 0x000FFFFF;		// set PB31-28 to UART2 and PB27-20 to USBD
	_reg_PTB_GPR &= 0x000FFFFF;		// select primary peripheral

	// init USB module

 	// reset and enable USB device module
	_reg_USBD_ENABLE &= ~0x40000000;	    /* disable module */
//	delay(10);
	i = 0;
	while (i<10)
	{
	    i++;
	}
	_reg_USBD_ENABLE &= ~0x00000001;	/* select 32-bit mode FIFO */
	_reg_USBD_ENABLE &= ~0x10000000;	/* Set big endian */
	_reg_USBD_ENABLE |= 0x40000000;	/* remark: resetting the module will enable module automatically */
	while (!(_reg_USBD_ENABLE & 0x40000000));		// wait until it is enabled
//	EUARTputString("USBD reset and enable okay.\n");

	// fill endpoint configuration buffer
	for (i=0; i<55; i++)
	{
		_reg_USBD_EPBUF = gEPconfigData[i];
		while (_reg_USBD_CFGBSY & 0x40000000);		// wait until busy bit is cleared
	}
//	EUARTputString("USBD config okay.\n");

	// mask interrupts
	_reg_USBD_INTR_STAT = 0x800000FF;		// clear general interrupts
	_reg_USBD_INTR_MASK = 0x800000FF;		// mask all general interrupts
	_reg_USBD_EP0_INTR_STAT = 0x000001FF;	// clear EP interrupts
	_reg_USBD_EP0_INTR_MASK = 0x000001FF;	// mask all EP interrupts
	_reg_USBD_EP1_INTR_STAT = 0x000001FF;	// clear EP interrupts
	_reg_USBD_EP1_INTR_MASK = 0x000001FF;	// mask all EP interrupts
	_reg_USBD_EP2_INTR_STAT = 0x000001FF;	// clear EP interrupts
	_reg_USBD_EP2_INTR_MASK = 0x000001FF;	// mask all EP interrupts
	_reg_USBD_EP3_INTR_STAT = 0x000001FF;	// clear EP interrupts
	_reg_USBD_EP3_INTR_MASK = 0x000001FF;	// mask all EP interrupts
	_reg_USBD_EP4_INTR_STAT = 0x000001FF;	// clear EP interrupts
	_reg_USBD_EP4_INTR_MASK = 0x000001FF;	// mask all EP interrupts
	_reg_USBD_EP5_INTR_STAT = 0x000001FF;	// clear EP interrupts
	_reg_USBD_EP5_INTR_MASK = 0x000001FF;	// mask all EP interrupts

	// configure USB_EPn_STAT registers and flush FIFOs
	_reg_USBD_EP0_STAT = 0x00000002;
	_reg_USBD_EP1_STAT = 0x000000D2;		// IN, MAX PS 32, BULK
	_reg_USBD_EP2_STAT = 0x00000052;		// OUT, MAX pS 32, BULK
	_reg_USBD_EP3_STAT = 0x000000BA;		// IN, MAX PS 16, INTR
	_reg_USBD_EP4_STAT = 0x0000003A;		// OUT, MAX PS 16, INTR
	_reg_USBD_EP5_STAT = 0x000000BA;		// IN, MAX PS 16, INTR

	// configure USB_EPn_FCTRL registers
	_reg_USBD_EP0_FCTRL = 0x0F000000;
	_reg_USBD_EP1_FCTRL = 0x0B000000;
	_reg_USBD_EP2_FCTRL = 0x0F000000;
	_reg_USBD_EP3_FCTRL = 0x0B000000;
	_reg_USBD_EP4_FCTRL = 0x0F000000;
	_reg_USBD_EP5_FCTRL = 0x0B000000;

	// configure USB_EPn_FALRM registers
	_reg_USBD_EP0_FALRM = 0x00000000;
	_reg_USBD_EP1_FALRM = 0x00000020;
	_reg_USBD_EP2_FALRM = 0x00000020;
	_reg_USBD_EP3_FALRM = 0x00000010;
	_reg_USBD_EP4_FALRM = 0x00000010;
	_reg_USBD_EP5_FALRM = 0x00000010;

	while (_reg_USBD_INTR_STAT & RST_START_MASK);	// wait until reset signaling finished
	_reg_USBD_CTRL = 0x0000001A;				// enable module

//	EUARTputString("USB module ready.\n");
}

void handleGetDevDscptr()
{
	/* 8 bytes per packet */
	_reg_USBD_EP0_FDAT = _gUsbDevDscptr[0];
	_reg_USBD_EP0_FCTRL |= 0x20000000;  // next write is last one of packet
	_reg_USBD_EP0_FDAT = _gUsbDevDscptr[1];
//	EUARTputString("handleGetDevDscptr.\n");
	/* if length is not exactly 0x12, just return one packet */
	/* otherwise, return all 0x12 bytes */
	if (_gUsbDevReq[6] == 0x12)
	{
		_reg_USBD_EP0_FDAT = _gUsbDevDscptr[2];
		_reg_USBD_EP0_FCTRL |= 0x20000000;  // next write is last one of packet
		_reg_USBD_EP0_FDAT = _gUsbDevDscptr[3];
		
		// due a bug in gcc, half-word access is compiled into word access
		// so we'll use byte access instead
		*((volatile U8 *)((U32)&_reg_USBD_EP0_FDAT+3)) = (U8)(_gUsbDevDscptr[4]>>8);
		_reg_USBD_EP0_FCTRL |= 0x20000000;  // next write is last one of packet
		*((volatile U8 *)((U32)&_reg_USBD_EP0_FDAT+3)) = (U8)_gUsbDevDscptr[4];
	}
}

void handleGetConfDscptr()
{
	/* if length is exactly 9, return 9 bytes only */
	if (_gUsbDevReq[6] == 0x09)
	{
		_reg_USBD_EP0_FDAT = _gUsbConfDscptr[0];
		_reg_USBD_EP0_FCTRL |= 0x20000000;  // next write is last one of packet
		_reg_USBD_EP0_FDAT = _gUsbConfDscptr[1];
		
		/* here comes the last byte */
		_reg_USBD_EP0_FCTRL |= 0x20000000;  // next write is last one of packet
		*((volatile U8 *)((U32)&_reg_USBD_EP0_FDAT+3)) = (U8)(_gUsbConfDscptr[2]>>24);
	}
	else    /* otherwise, return all 32 bytes */
	{
		_reg_USBD_EP0_FDAT = _gUsbConfDscptr[0];
		_reg_USBD_EP0_FCTRL |= 0x20000000;  // next write is last one of packet
		_reg_USBD_EP0_FDAT = _gUsbConfDscptr[1];
		
		_reg_USBD_EP0_FDAT = _gUsbConfDscptr[2];
		_reg_USBD_EP0_FCTRL |= 0x20000000;  // next write is last one of packet
		_reg_USBD_EP0_FDAT = _gUsbConfDscptr[3];
		
		_reg_USBD_EP0_FDAT = _gUsbConfDscptr[4];
		_reg_USBD_EP0_FCTRL |= 0x20000000;  // next write is last one of packet
		_reg_USBD_EP0_FDAT = _gUsbConfDscptr[5];
		
		_reg_USBD_EP0_FDAT = _gUsbConfDscptr[6];
		_reg_USBD_EP0_FCTRL |= 0x20000000;  // next write is last one of packet
		_reg_USBD_EP0_FDAT = _gUsbConfDscptr[7];
		
		/* need to end with a zero length packet */
		_reg_USBD_EP0_STAT |= ZLPS_MASK;    // next one is a zero length packet
	}
}