📄 bootloader.c~
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#include "Include/type.h"#include "Include/mx1.h"#include "Include/devnode.h"extern void EUARTinit(void);extern U8 EUARTdataReady(void);extern U8 EUARTgetData(void);extern void EUARTputData(U8);extern void EUARTputString(U8 *line);#define CMD_LINE_LEN 80#define DELAY_LOOP_COUNT 0x20000devnode_t *pNode1, *pNode2;char *pMemName, *pCmdNodeName, *pCmdLine, *pChar;const char memName[] = "DRAMM";const char cmdNodeName[] = "command line";#ifdef SYNCFLASH/*char cmdLine[CMD_LINE_LEN] = "root=/dev/mdsk mem=48M";*/char cmdLine[CMD_LINE_LEN] = "root=/dev/mtdblock/2 rw mem=48M";#endif#ifdef AMDFLASHchar cmdLine[CMD_LINE_LEN] = "root=/dev/mtdblock/2 rw mem=48M";#endifint main(){ U32 *pSource, *pDestin, count; U8 countDown, bootOption; U32 delayCount; U32 fileSize, i; char c; char freq = '1'; // default of 1 means FCLK = 150MHz, BCLK=48MHz char *pCmdLine; char *pMem; init(); cs8900MX1Init(); EUARTinit(); while(1) {#ifdef SYNCFLASH EUARTputString("\n\nDBMX1 Linux Bootloader ver 0.3.8\n");#endif#ifdef AMDFLASH EUARTputString("\n\nDBMX1 Linux Bootloader ver 0.3.8\n");#endif EUARTputString("Copyright (C) 2002 Motorola Semiconductors Hong Kong Ltd.\n\n"); EUARTputString((U8 *)cmdLine); EUARTputString("\nFCLK = "); switch(freq) { case '1': EUARTputString("150, BCLK = 48\n"); break; case '2': EUARTputString("150, BCLK = 96\n"); break; case '3': EUARTputString("192, BCLK = 48\n"); break; case '4': EUARTputString("192, BCLK = 96\n"); break; case '5': EUARTputString("200, BCLK = 48\n"); break; case '6': EUARTputString("200, BCLK = 96\n"); break; default: break;// cannot happen! } EUARTputString("\n\n"); // alternate boot-up options ? while (EUARTdataReady()) EUARTgetData(); // clear input buffer EUARTputString("Press any key for alternate boot-up options ... "); countDown = 2; bootOption = 0; while ((countDown) && (!bootOption)) { EUARTputString("\b\b"); // two back spaces EUARTputHex(countDown); delayCount = 0; do { delayCount++; if (EUARTdataReady()) bootOption = 1; } while ((delayCount < DELAY_LOOP_COUNT) && (!bootOption)); --countDown; } EUARTputString("\b\b"); // two back spaces EUARTputHex(countDown); EUARTputString("\n\n"); if (bootOption) { while (EUARTdataReady()) EUARTgetData(); // clear input buffer // print options EUARTputString("0. Program bootloader image\n"); EUARTputString("1. Program kernel image\n"); EUARTputString("2. Program root-disk image\n"); EUARTputString("3. Download kernel and boot from RAM\n"); EUARTputString("4. Download kernel and boot with ver 0.3.x bootloader format\n"); EUARTputString("5. Boot a ver0.3.x kernel\n"); EUARTputString("6. Boot with a different command line\n"); EUARTputString("7. Boot with a different FCLK/BCLK setting\n"); EUARTputString("\n Please enter selection -> "); do { while (!EUARTdataReady()); // wait for key press bootOption = EUARTgetData(); if (bootOption >= 0x20) { EUARTputData('\b'); EUARTputData(bootOption); } } while ((bootOption <= '0') && (bootOption >= '6')); EUARTputString("\n\n"); if ((bootOption >= '0') && (bootOption <= '4')) { fileSize = usbrx(); EUARTputData('\n'); } if ((bootOption >= '0') && (bootOption <= '2')) // i.e. flash programming { switch (bootOption) { case '0': // i.e. program bootloader progFlash(0x0B006E00, 0, fileSize); break; case '1': // i.e. program kernel image progFlash(0x0B006E00, 1, fileSize); break; case '2': // i.e. program root-disk progFlash(0x0B006E00, 2, fileSize); } EUARTputString("\nPress RESET button on ADS board ..."); while (1); // infinite loop } } if (bootOption == '6') // i.e. boot with a different command line { EUARTputString("New command line: "); i = 0; do { while (!EUARTdataReady()); // wait for key press c = EUARTgetData(); if (c != '\r') { if (c == '\b') { if (i > 0) { // erase the character EUARTputData('\b'); EUARTputData(' '); EUARTputData('\b'); --i; } } else { EUARTputData(c); cmdLine[i++] = c; } } } while ((c != '\r') && (i < CMD_LINE_LEN-1)); if (i > 0) cmdLine[i] = 0; // mark end of string EUARTputData('\n'); } if (bootOption == '7') // i.e. boot with a different FCLK/BCLK setting { EUARTputString("Please select setting (Current setting is "); EUARTputData(freq); EUARTputString("):\n"); EUARTputString("\t1. FCLK = 150MHz, BCLK = 48MHz\n"); EUARTputString("\t2. FCLK = 150MHz, BCLK = 96MHz\n"); EUARTputString("\t3. FCLK = 192MHz, BCLK = 48MHz\n"); EUARTputString("\t4. FCLK = 192MHz, BCLK = 96MHz\n"); EUARTputString("\t5. FCLK = 200MHz, BCLK = 48MHz\n"); EUARTputString("\t6. FCLK = 200MHz, BCLK = 96MHz\n"); while (!EUARTdataReady()); // wait for key press freq = EUARTgetData(); switch(freq) { case '1': _reg_CCM_MPCTL0 = 0x04632410; _reg_CCM_CSCR &= ~0x00003C00; _reg_CCM_CSCR |= 0x00000400; break; case '2': default: _reg_CCM_MPCTL0 = 0x04632410; _reg_CCM_CSCR &= ~0x00003C00; break; case '3': _reg_CCM_MPCTL0 = 0x003f1437; _reg_CCM_CSCR &= ~0x00003C00; _reg_CCM_CSCR |= 0x00000400; break; case '4': _reg_CCM_MPCTL0 = 0x003f1437; _reg_CCM_CSCR &= ~0x00003C00; break; case '5': _reg_CCM_MPCTL0 = 0x0063180a; _reg_CCM_CSCR &= ~0x00003C00; _reg_CCM_CSCR |= 0x00000400; break; case '6': _reg_CCM_MPCTL0 = 0x0063180a; _reg_CCM_CSCR &= ~0x00003C00; break; } // trigger the restart bit (bit 21) _reg_CCM_CSCR |= 0x00200000; continue; // back to start of while(1) } if ((bootOption == '3') || (bootOption == '4')) { // i.e. download kernel and run // copy kernel from 0x0B006E00 to 0x08008000 count = fileSize; pSource = (U32 *)0x0B006E00; pDestin = (U32 *)0x08008000; do { *(pDestin++) = *(pSource++); count -= 4; } while (count > 0); } else // i.e. kernel image is in FLASH { // copy kernel from FLASH to RAM EUARTputString("Copying kernel from Flash to RAM ...\n"); //DMA copy *(P_U32)DMA_DCR |= 0x2; *(P_U32)DMA_DCR |= 0x1; *(P_U32)DMA_DAR1= 0x08008000; *(P_U32)DMA_CCR1= 0; *(P_U32)DMA_BLR1 = 0; *(P_U32)DMA_BUCR1= (int)0x100; #ifdef SYNCFLASH *(P_U32)DMA_SAR1= 0x0C100000;#endif#ifdef AMDFLASH *(P_U32)DMA_SAR1= 0x10100000;#endif *(P_U32)DMA_CNTR1 = 0x200000; *(P_U32)DMA_CCR1 |= 0x1; //start dma while ( !(*(P_U32)DMA_ISR) ){}; *(P_U32)DMA_DCR = 0; *(P_U32)DMA_DCR |= 0x2; *(P_U32)DMA_DCR = 0; } EUARTputString("Booting kernel ...\n\n"); if ((bootOption == '4') || (bootOption == '5')) // boot a ver0.1.x kernel { // prepare devnodes // Parameters passed to kernel must reside in the memory range // of 0x08000000 to 0x083FFFFF (kernel will map to this 4M of // memory during startup with proper MMU setting). // We should be very careful of not to put parameters in those // locations occupied by the kernel itself. So we'll use the // last 4K only. pNode1 = (devnode_t *) 0x083FF000; pNode2 = (devnode_t *) 0x083FF100; pMemName = (char *) 0x083FF200; pChar = (char *)&memName; do { } while ((*(pMemName++) = *(pChar++)) != 0); pMemName = (char *) 0x083FF200; pCmdNodeName = (char *) 0x083FF300; pChar = (char *)&cmdNodeName; do { } while ((*(pCmdNodeName++) = *(pChar++)) != 0); pCmdNodeName = (char *) 0x083FF300; pCmdLine = (char *) 0x083FF400; pChar = (char *)&cmdLine; do { } while ((*(pCmdLine++) = *(pChar++)) != 0); pCmdLine = (char *) 0x083FF400; pNode1->next = (devnode_t *)0; pNode1->type = (DEVNODE_DEVICE << 16) | DEVNODE_DEVICE_MEMORY; pNode1->params[0] = 0; pNode1->params[1] = MEM_SIZE; pNode1->name = pMemName; pNode1->data = (void *)0; pNode1->size = 0; pNode2->next = pNode1; pNode2->type = (DEVNODE_OS << 16) | DEVNODE_OS_COMMAND_LINE; pNode2->params[0] = 0; pNode2->params[1] = 0; pNode2->name = pCmdNodeName; pNode2->data = pCmdLine; pNode2->size = 23; JumpToKernel0x((void *)0x8008000, 0, 17, pNode2) ; } // the command line is passed through the last 4K of the 3M memory allocated to the kernel // this 3M memory block will be mapped to the kernel space during kernel startup pMem = (char *)0x083FF000; pCmdLine = (char *)&cmdLine; while ((*(pMem++)=*(pCmdLine++)) != 0); JumpToKernel((void *)0x8008000, 0x083FF000) ; return (0); } //end while(1)}
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