divfr_16.asm

嵌入式系统开发中

/*******************************************************************************
Copyright(c) 2000 - 2002 Analog Devices. All Rights Reserved.
Developed by Joint Development Software Application Team, IPDC, Bangalore, India
for Blackfin DSPs  ( Micro Signal Architecture 1.0 specification).

By using this module you agree to the terms of the Analog Devices License
Agreement for DSP Software. 
********************************************************************************
Module Name     : divfr_16.asm
Label name      :  __divfr_16
Version         :   1.0
Change History  :

                Version     Date          Author      Comments
                1.0         06/19/2001    Srinivas    Original 

Description     : This function performs signed fractional division of 
                  Numerator (32 bit) and Denominator (16 bits) using  DIVS and
                  DIVQ.
  
Prototype       : fract16 _divfr_16(fract32 Numerator, fract16 Denominator)

Registers Used  : R0, R1, P0, LC0.

Performance     :
                Code size      : 14 bytes.

*******************************************************************************/
.section L1_code;
.global __divfr_16;
.align 8;
    
__divfr_16 :   
    
    P0 = 15;
    DIVS(R0,R1);
    
    LOOP .DIV_LP LC0 = P0;
    LOOP_BEGIN .DIV_LP;
    DIVQ(R0,R1);
    LOOP_END .DIV_LP;
    R0 = R0.L (X);
    RTS;  

__divfr_16.end: