dm9000x.c

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/*
  dm9000.c: Version 1.1 09/11/2001
  
        A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
	Copyright (C) 1997  Sten Wang

	This program is free software; you can redistribute it and/or
	modify it under the terms of the GNU General Public License
	as published by the Free Software Foundation; either version 2
	of the License, or (at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
	GNU General Public License for more details.

  Author: Sten Wang, 886-3-5798797-8517, E-mail: [e-mail]
  Date:   10/28,1998

  (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.


V0.11	06/20/2001	REG_0A bit3=1, default enable BP with DA match
	06/22/2001 	Support DM9801 progrmming	
	 	 	E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
		 	E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
		     		R17 = (R17 & 0xfff0) | NF + 3
		 	E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
		     		R17 = (R17 & 0xfff0) | NF
v1.00               modify by simon 2001.9.5
                        change for kernel 2.4.x    
v1.1   11/09/2001      fix force mode bug             
*/
#if defined(MODVERSIONS)
#include <linux/modversions.h>
#endif
				
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/version.h>
#include <asm/dma.h>
#include <linux/spinlock.h>
#include <linux/delay.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <asm/arch/quasar.h>

/* Board/System/Debug information/definition ---------------- */

// optimization option
// 							RX				TX
// no optmization : 	11.2 / 8.9		9.2 / 7.4
// INLINE_OPTIMIZE : 	12.5 / 9.9		10.2 / 8.2
// SERIESIO_OPTIMIZE :	12.9 / 10.3		11.7 / 9.3
// 										12.4 / 9.9 (write address only one time)
//
// WAITCYCLE_OPTIMIZE : 14.9 / 11.9		13.7 / 11.0 (+3.0, 3.6)
// LOOP_OPTIMIZE : 		12.8 / 10.2		12.6 / 10.1
// IORW_OPTIMIZE :		12.9 / 10.3		12.6 / 10.0

#define INLINE_OPTIMIZE			1
#define SERIESIO_OPTIMIZE		1
#define WAITCYCLE_OPTIMIZE		0			// good but dangerous. depends on CPU clock
#define LOOP_OPTIMIZE			0			// not good : no performance improvement
#define IORW_OPTIMIZE			0			// slight performance improvement

#define DM9000_IGNOREID			1			// even thought the ID doesn't match DM9000_ID, regards the card exist
#define DM9000_CHECKIRQSTAT		0			// check if the IRQ is enabled at every timer

#define DM9000_RXDMA			1			// Use LBC => Q2H => HOST Memory DMA
#define DM9000_RXDMA_DEBUG		0
#define DM9000_RXDMA_DMAINT		0

#ifdef CONFIG_SD_NETRXIDLE		
#define CONFIG_SD_NETRXIDLEMODE	2			// 1 : prcess packet directly
											// 2 : process through softirq queue
#endif

#define DM9000_ID	0x90000A46

#define DM9000_REG00	0x00
#define DM9000_REG05	0x30	/* SKIP_CRC/SKIP_LONG */
#define DM9000_REG08	0x27
#define DM9000_REG09	0x38
#define DM9000_REG0A	0x08
#define DM9000_REGFF	0x83	/* IMR */

#define DM9000_PHY	0x40	/* PHY address 0x01 */
#define DM9000_PKT_MAX	1536	/* Received packet max size */
#define DM9000_PKT_RDY	0x01	/* Packet ready to receive */
#define DM9000_MIN_IO	0x300
#define DM9000_MAX_IO	0x370
#define DM9000_INT_MII	0x00
#define DM9000_EXT_MII	0x80

#define DM9000_VID_L	0x28
#define DM9000_VID_H	0x29
#define DM9000_PID_L	0x2A
#define DM9000_PID_H	0x2B

#define DM9801_NOISE_FLOOR	0x08
#define DM9802_NOISE_FLOOR	0x05

#define DMFE_SUCC       0
#define MAX_PACKET_SIZE 1514
#define DMFE_MAX_MULTICAST 14

#define DMFE_TIMER_WUT  jiffies+(HZ*2)	/* timer wakeup time : 2 second */
#define DMFE_TX_TIMEOUT (HZ*2)	/* tx packet time-out time 1.5 s" */

#if defined(DM9000_DEBUG)
#define DMFE_DBUG(dbug_now, msg, vaule) if (dmfe_debug || dbug_now) printk(KERN_ERR "dmfe: %s %x\n", msg, vaule)
#else
#define DMFE_DBUG(dbug_now, msg, vaule) 
#endif

#if LINUX_VERSION_CODE < 0x20300
#define DEVICE device
#else
#define DEVICE net_device
#endif

enum DM9000_PHY_mode {
	DM9000_10MHD = 0, DM9000_100MHD = 1, DM9000_10MFD = 4,
	DM9000_100MFD = 5, DM9000_AUTO = 8, DM9000_1M_HPNA =0x10 };

enum DM9000_NIC_TYPE {
	FASTETHER_NIC = 0, HOMERUN_NIC = 1, LONGRUN_NIC = 2 };

/* Structure/enum declaration ------------------------------- */
typedef struct board_info {
	struct DEVICE *next_dev;	/* next device */

	u32 runt_length_counter;	/* counter: RX length < 64byte */ 
	u32 long_length_counter;	/* counter: RX length > 1514byte */ 
	u32 reset_counter;		/* counter: RESET */ 
	u32 reset_tx_timeout;		/* RESET caused by TX Timeout */ 
	u32 reset_rx_status;		/* RESET caused by RX Statsus wrong */ 

	u16 ioaddr;			/* Register I/O base address */
	u16 io_data;			/* Data I/O address */
	u16 irq;			/* IRQ */

	u16 tx_pkt_cnt;
	u16 queue_pkt_len;
	u16 queue_start_addr;
	u16 dbug_cnt;
	u8 reg0, reg5, reg8, reg9, rega;	/* registers saved */
	u8 op_mode;			/* PHY operation mode */
	u8 io_mode;			/* 0:word, 2:byte */
	u8 phy_addr;
	u8 link_failed;			/* Ever link failed */
	u8 device_wait_reset;		/* device state */
	u8 nic_type;			/* NIC type */
	struct timer_list timer;
	/*struct enet_statistics stats;*/ /* statistic counter */ 
        //mark by simon 2001.9.4
	struct net_device_stats stats; // add by simon 2001.9.4 for kernel 2.4
	unsigned char srom[128];
	spinlock_t lock; //add by simon 2001.9.4
} board_info_t;

/* Global variable declaration ----------------------------- */
static int dmfe_debug = 0;
static struct DEVICE * dmfe_root_dev = NULL;      /* First device */

/* For module input parameter */
static int debug = 0;
static int mode = DM9000_AUTO;
static int media_mode = DM9000_AUTO;
static u8 reg5 = DM9000_REG05;
static u8 reg8 = DM9000_REG08;
static u8 reg9 = DM9000_REG09;
static u8 rega = DM9000_REG0A;
static u8 nfloor = 0;

unsigned long CrcTable[256] = {
   0x00000000L, 0x77073096L, 0xEE0E612CL, 0x990951BAL,
   0x076DC419L, 0x706AF48FL, 0xE963A535L, 0x9E6495A3L,
   0x0EDB8832L, 0x79DCB8A4L, 0xE0D5E91EL, 0x97D2D988L,
   0x09B64C2BL, 0x7EB17CBDL, 0xE7B82D07L, 0x90BF1D91L,
   0x1DB71064L, 0x6AB020F2L, 0xF3B97148L, 0x84BE41DEL,
   0x1ADAD47DL, 0x6DDDE4EBL, 0xF4D4B551L, 0x83D385C7L,
   0x136C9856L, 0x646BA8C0L, 0xFD62F97AL, 0x8A65C9ECL,
   0x14015C4FL, 0x63066CD9L, 0xFA0F3D63L, 0x8D080DF5L,
   0x3B6E20C8L, 0x4C69105EL, 0xD56041E4L, 0xA2677172L,
   0x3C03E4D1L, 0x4B04D447L, 0xD20D85FDL, 0xA50AB56BL,
   0x35B5A8FAL, 0x42B2986CL, 0xDBBBC9D6L, 0xACBCF940L,
   0x32D86CE3L, 0x45DF5C75L, 0xDCD60DCFL, 0xABD13D59L,
   0x26D930ACL, 0x51DE003AL, 0xC8D75180L, 0xBFD06116L,
   0x21B4F4B5L, 0x56B3C423L, 0xCFBA9599L, 0xB8BDA50FL,
   0x2802B89EL, 0x5F058808L, 0xC60CD9B2L, 0xB10BE924L,
   0x2F6F7C87L, 0x58684C11L, 0xC1611DABL, 0xB6662D3DL,
   0x76DC4190L, 0x01DB7106L, 0x98D220BCL, 0xEFD5102AL,
   0x71B18589L, 0x06B6B51FL, 0x9FBFE4A5L, 0xE8B8D433L,
   0x7807C9A2L, 0x0F00F934L, 0x9609A88EL, 0xE10E9818L,
   0x7F6A0DBBL, 0x086D3D2DL, 0x91646C97L, 0xE6635C01L,
   0x6B6B51F4L, 0x1C6C6162L, 0x856530D8L, 0xF262004EL,
   0x6C0695EDL, 0x1B01A57BL, 0x8208F4C1L, 0xF50FC457L,
   0x65B0D9C6L, 0x12B7E950L, 0x8BBEB8EAL, 0xFCB9887CL,
   0x62DD1DDFL, 0x15DA2D49L, 0x8CD37CF3L, 0xFBD44C65L,
   0x4DB26158L, 0x3AB551CEL, 0xA3BC0074L, 0xD4BB30E2L,
   0x4ADFA541L, 0x3DD895D7L, 0xA4D1C46DL, 0xD3D6F4FBL,
   0x4369E96AL, 0x346ED9FCL, 0xAD678846L, 0xDA60B8D0L,
   0x44042D73L, 0x33031DE5L, 0xAA0A4C5FL, 0xDD0D7CC9L,
   0x5005713CL, 0x270241AAL, 0xBE0B1010L, 0xC90C2086L,
   0x5768B525L, 0x206F85B3L, 0xB966D409L, 0xCE61E49FL,
   0x5EDEF90EL, 0x29D9C998L, 0xB0D09822L, 0xC7D7A8B4L,
   0x59B33D17L, 0x2EB40D81L, 0xB7BD5C3BL, 0xC0BA6CADL,
   0xEDB88320L, 0x9ABFB3B6L, 0x03B6E20CL, 0x74B1D29AL,
   0xEAD54739L, 0x9DD277AFL, 0x04DB2615L, 0x73DC1683L,
   0xE3630B12L, 0x94643B84L, 0x0D6D6A3EL, 0x7A6A5AA8L,
   0xE40ECF0BL, 0x9309FF9DL, 0x0A00AE27L, 0x7D079EB1L,
   0xF00F9344L, 0x8708A3D2L, 0x1E01F268L, 0x6906C2FEL,
   0xF762575DL, 0x806567CBL, 0x196C3671L, 0x6E6B06E7L,
   0xFED41B76L, 0x89D32BE0L, 0x10DA7A5AL, 0x67DD4ACCL,
   0xF9B9DF6FL, 0x8EBEEFF9L, 0x17B7BE43L, 0x60B08ED5L,
   0xD6D6A3E8L, 0xA1D1937EL, 0x38D8C2C4L, 0x4FDFF252L,
   0xD1BB67F1L, 0xA6BC5767L, 0x3FB506DDL, 0x48B2364BL,
   0xD80D2BDAL, 0xAF0A1B4CL, 0x36034AF6L, 0x41047A60L,
   0xDF60EFC3L, 0xA867DF55L, 0x316E8EEFL, 0x4669BE79L,
   0xCB61B38CL, 0xBC66831AL, 0x256FD2A0L, 0x5268E236L,
   0xCC0C7795L, 0xBB0B4703L, 0x220216B9L, 0x5505262FL,
   0xC5BA3BBEL, 0xB2BD0B28L, 0x2BB45A92L, 0x5CB36A04L,
   0xC2D7FFA7L, 0xB5D0CF31L, 0x2CD99E8BL, 0x5BDEAE1DL,
   0x9B64C2B0L, 0xEC63F226L, 0x756AA39CL, 0x026D930AL,
   0x9C0906A9L, 0xEB0E363FL, 0x72076785L, 0x05005713L,
   0x95BF4A82L, 0xE2B87A14L, 0x7BB12BAEL, 0x0CB61B38L,
   0x92D28E9BL, 0xE5D5BE0DL, 0x7CDCEFB7L, 0x0BDBDF21L,
   0x86D3D2D4L, 0xF1D4E242L, 0x68DDB3F8L, 0x1FDA836EL,
   0x81BE16CDL, 0xF6B9265BL, 0x6FB077E1L, 0x18B74777L,
   0x88085AE6L, 0xFF0F6A70L, 0x66063BCAL, 0x11010B5CL,
   0x8F659EFFL, 0xF862AE69L, 0x616BFFD3L, 0x166CCF45L,
   0xA00AE278L, 0xD70DD2EEL, 0x4E048354L, 0x3903B3C2L,
   0xA7672661L, 0xD06016F7L, 0x4969474DL, 0x3E6E77DBL,
   0xAED16A4AL, 0xD9D65ADCL, 0x40DF0B66L, 0x37D83BF0L,
   0xA9BCAE53L, 0xDEBB9EC5L, 0x47B2CF7FL, 0x30B5FFE9L,
   0xBDBDF21CL, 0xCABAC28AL, 0x53B39330L, 0x24B4A3A6L,
   0xBAD03605L, 0xCDD70693L, 0x54DE5729L, 0x23D967BFL,
   0xB3667A2EL, 0xC4614AB8L, 0x5D681B02L, 0x2A6F2B94L,
   0xB40BBE37L, 0xC30C8EA1L, 0x5A05DF1BL, 0x2D02EF8DL
};

/* function declaration ------------------------------------- */
int dmfe_probe(struct DEVICE *);
static int dmfe_open(struct DEVICE *);
static int dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
static int dmfe_stop(struct DEVICE *);
//static struct enet_statistics * dmfe_get_stats(struct DEVICE *); make by simon 2001.9.4 for kernel 2.4
static struct net_device_stats * dmfe_get_stats(struct DEVICE *); // add by simon 2001.94 for kernel 2.4
static int dmfe_do_ioctl(struct DEVICE *, struct ifreq *, int);
static void dmfe_interrupt(int , void *, struct pt_regs *);
static void dmfe_timer(unsigned long);
static void dmfe_init_dm9000(struct DEVICE *);
static unsigned long cal_CRC(unsigned char *, unsigned int, u8);
static u16 phy_read(board_info_t *, int);
static void phy_write(board_info_t *, int, u16);
static u16 read_srom_word(board_info_t *, int);
static void dmfe_packet_receive(struct DEVICE *, board_info_t *);
static void dm9000_hash_table(struct DEVICE *);

#ifdef CONFIG_SD_SKBUFFIDLE
extern void skbuff_cache_idle(void);
extern struct sk_buff *dev_alloc_skb_cache(int len);
#endif

/* debugging code */

#if DM9000_RXDMA_DEBUG

static void dump_mem_word(u16 *ptr, int len)
{
	int i;

	for (i = 0; i < len; ++i) {
		if ((i & 0x07) == 0x00) 
			printk("%04x : ", i);
		printk("%04x ", ptr[i]);
		if ((i & 0x07) == 0x07)
			printk("\n");
	}
	if ((i & 0x07) != 0x00)
		printk("\n");
}

static void dump_mem_word_diff(u16 *ptr, u16 *ptr2, int len)
{
	int i;

	for (i = 0; i < len; ++i) {
		if ((i & 0x07) == 0x00) 
			printk("%04x : ", i);
		if (ptr[i] == ptr2[i])
			printk("     ");
		else 
			printk("%04x ", ptr2[i]);
		if ((i & 0x07) == 0x07)
			printk("\n");
	}
	if ((i & 0x07) != 0x00)
		printk("\n");
}

static int list_mem_word_diff(u16 *ptr, u16 *ptr2, int len)
{
	int i, ndiff;

	printk("DIFF : ");

	for (i = 0, ndiff = 0; i < len; ++i) 
		if (ptr[i] != ptr2[i]) {
			++ndiff;
			printk("%d ", i);
		}

	printk("total = %d\n", ndiff);

	return ndiff;
}

#endif

/* I/O */

#if INLINE_OPTIMIZE
#define DMFE_INLINE	__inline__
#else
#define DMFE_INLINE
#endif

unsigned DMFE_INLINE char dmfe_inb(unsigned int addr)
{
	return (unsigned char) (quasar_lbc_readl(addr) & 0x000000ff);
}

unsigned short DMFE_INLINE dmfe_inw(unsigned int addr)
{
	return (unsigned short) (quasar_lbc_readl(addr) & 0x0000ffff);
}

void DMFE_INLINE dmfe_outb(unsigned int value, unsigned int addr)
{
	quasar_lbc_writel(addr, value & 0x000000ff);
}

void DMFE_INLINE dmfe_outw(unsigned int value, unsigned int addr)
{
	quasar_lbc_writel(addr, value & 0x0000ffff);
}

// WAITCYCLE_OPTIMIZE
//   CPU clock : 150MHz
//   After initializing transaction, it needs long time until the transaction be completed
//   It takes 4 transactions of reading STATUS register (*pstatus)
//   or takes about 43 CPU clocks
//     insw() loop : 
//       Write Address (initiating transaction)
//       39 NOP cycles
//       4 other cycles (including one load instruction)
//       Read Data
//       => needs 43 cycles
//     outsw() loop : 
//       2 other cycles (including one load instruction)
//       Write Data (initiating transaction)
//       38 NOP cycles
//       3 other cycles
//       => needs 43 cycles
//   For safety, this code inserts 41 and 40 NOP instructions

#if SERIESIO_OPTIMIZE

void dmfe_insw(u16 *ptr, int len, int addr)
{
	int i;
	
	volatile unsigned int *pquasar = (volatile unsigned int *) QUASAR_MAP_AREA;
	volatile unsigned int *paddr = pquasar + (QUASAR_LBC_READ_ADDR >> 2);
	volatile unsigned int *pdata = pquasar + (QUASAR_LBC_READ_DATA >> 2);
	volatile unsigned int *pstatus = pquasar + (QUASAR_LBC_STATUS >> 2);

#if WAITCYCLE_OPTIMIZE
	#define RX_ONETIME									\
		*paddr = addr;									\
		__asm__ __volatile__ ( 							\
			"nop\n" "nop\n" "nop\n" "nop\n" "nop\n" 	\
			"nop\n" "nop\n" "nop\n" "nop\n" "nop\n" 	\
			"nop\n" "nop\n" "nop\n" "nop\n" "nop\n" 	\
			"nop\n" "nop\n" "nop\n" "nop\n" "nop\n" 	\
			"nop\n" "nop\n" "nop\n" "nop\n" "nop\n" 	\
			"nop\n" "nop\n" "nop\n" "nop\n" "nop\n" 	\
			"nop\n" "nop\n" "nop\n" "nop\n" "nop\n" 	\
			"nop\n" "nop\n" "nop\n" "nop\n" "nop\n" 	\
			"nop\n" 									\
		);												\
		ptr[i] = *pdata;
#else
	#define RX_ONETIME									\
		*paddr = addr; 									\
		while (*pstatus & 0x01) 						\
			; 											\
		ptr[i] = *pdata;
#endif

#if LOOP_OPTIMIZE
	int loop16 = len & (~0x0f);

	for (i = 0; i < loop16; ) {
		RX_ONETIME
		++i;
		RX_ONETIME
		++i;
		RX_ONETIME
		++i;
		RX_ONETIME
		++i;
		RX_ONETIME
		++i;
		RX_ONETIME
		++i;
		RX_ONETIME
		++i;
		RX_ONETIME
		++i;
		RX_ONETIME
		++i;
		RX_ONETIME
		++i;
		RX_ONETIME
		++i;
		RX_ONETIME
		++i;
		RX_ONETIME
		++i;
		RX_ONETIME
		++i;
		RX_ONETIME
		++i;
		RX_ONETIME
		++i;
	}
	for (; i < len; ++i) {
		RX_ONETIME
	}
#else
	for (i = 0; i < len; ++i) {
		RX_ONETIME
	}
#endif
}

void dmfe_outsw(u16 *ptr, int len, int addr)
{
	int i;

	volatile unsigned int *pquasar = (volatile unsigned int *) QUASAR_MAP_AREA;
	volatile unsigned int *paddr = pquasar + (QUASAR_LBC_WRITE_ADDR >> 2);
	volatile unsigned int *pdata = pquasar + (QUASAR_LBC_WRITE_DATA >> 2);
	volatile unsigned int *pstatus = pquasar + (QUASAR_LBC_STATUS >> 2);

#if WAITCYCLE_OPTIMIZE
	#define TX_ONETIME									\
		*pdata = ptr[i];								\
		__asm__ __volatile__ ( 							\
			"nop\n" "nop\n" "nop\n" "nop\n" "nop\n" 	\
			"nop\n" "nop\n" "nop\n" "nop\n" "nop\n" 	\
			"nop\n" "nop\n" "nop\n" "nop\n" "nop\n" 	\
			"nop\n" "nop\n" "nop\n" "nop\n" "nop\n" 	\
			"nop\n" "nop\n" "nop\n" "nop\n" "nop\n" 	\
			"nop\n" "nop\n" "nop\n" "nop\n" "nop\n" 	\
			"nop\n" "nop\n" "nop\n" "nop\n" "nop\n" 	\
			"nop\n" "nop\n" "nop\n" "nop\n" "nop\n" 	\
		);
#else
	#define TX_ONETIME									\
		*pdata = ptr[i];								\
		while (*pstatus & 0x02)							\
			;
#endif

#if LOOP_OPTIMIZE
	int loop16 = len & (~0x0f);

	*paddr = addr;
	for (i = 0; i < loop16; ) {
		TX_ONETIME
		++i;
		TX_ONETIME
		++i;
		TX_ONETIME
		++i;
		TX_ONETIME
		++i;
		TX_ONETIME
		++i;
		TX_ONETIME
		++i;
		TX_ONETIME
		++i;
		TX_ONETIME
		++i;
		TX_ONETIME
		++i;
		TX_ONETIME
		++i;
		TX_ONETIME
		++i;
		TX_ONETIME
		++i;
		TX_ONETIME
		++i;
		TX_ONETIME
		++i;
		TX_ONETIME
		++i;
		TX_ONETIME
		++i;
	}
	for (; i < len; ++i) {
		TX_ONETIME
	}
#else
	*paddr = addr;
	for (i = 0; i < len; ++i) {
		TX_ONETIME
	}
#endif
}

#endif

#if IORW_OPTIMIZE

unsigned char dmfe_iorb(int addr, int reg)
{
	volatile unsigned int *pquasar = (volatile unsigned int *) QUASAR_MAP_AREA;

	pquasar[QUASAR_LBC_WRITE_ADDR >> 2] = addr;
	pquasar[QUASAR_LBC_WRITE_DATA >> 2] = reg;
	while (pquasar[QUASAR_LBC_STATUS >> 2] & 0x02)
		;
	pquasar[QUASAR_LBC_READ_ADDR >> 2] = addr + 4;
	while (pquasar[QUASAR_LBC_STATUS >> 2] & 0x01)
		;
	return (unsigned char) pquasar[QUASAR_LBC_READ_DATA >> 2];
}

unsigned char dmfe_iowb(int addr, int reg, int data)
{
	volatile unsigned int *pquasar = (volatile unsigned int *) QUASAR_MAP_AREA;

	pquasar[QUASAR_LBC_WRITE_ADDR >> 2] = addr;
	pquasar[QUASAR_LBC_WRITE_DATA >> 2] = reg;
	while (pquasar[QUASAR_LBC_STATUS >> 2] & 0x02)
		;
	pquasar[QUASAR_LBC_WRITE_ADDR >> 2] = addr + 4;
	pquasar[QUASAR_LBC_WRITE_DATA >> 2] = data;
	while (pquasar[QUASAR_LBC_STATUS >> 2] & 0x02)
		;
}

#define ior(db, reg)		dmfe_iorb(db->ioaddr, reg)