head-arm-netarm.s

这是一个SIGMA方案的PMP播放器的UCLINUX程序,可播放DVD,VCD,CD MP3...有很好的参考价值.

 * Jump to linux
 */

		mov	fp, #0
		b	start_kernel


/*
 * NET+ARM development board blink routine - turns led on and then off
 * approx one second on, one second off.
 * NET+40 board: The RED led is on bit 2 (0x04)
 */

		.globl	_netarm_led_blink
_netarm_led_blink:

/*
 * config C1 as GPIO output
 */
		ldr	r4, =NETARM_GEN_MODULE_BASE
		ldr	r1, [r4, #+NETARM_GEN_PORTC]
		ldr	r2, =((0xFFFFFFFF) ^ (NETARM_GEN_PORT_MODE(NA_BLINK_LED) | \
			                      NETARM_GEN_PORT_DIR(NA_BLINK_LED)))
		and	r1, r1, r2
		ldr	r2, =(NETARM_GEN_PORT_DIR(NA_BLINK_LED))
		orr	r1, r1, r2
		str	r1, [r4, #+NETARM_GEN_PORTC]
/*
 * turn the LED off ( output high )
 */
1:
		eor	r1, r1, #(NA_BLINK_LED)
		str	r1, [r4, #+NETARM_GEN_PORTC]
/*
 * wait a bit - million iterations, give or take
 */
		mov	r2, #0x100000
2:
		subs	r2, r2, #1
		bgt	2b

		b 	1b		

		.globl	_netarm_led_FAIL
_netarm_led_FAIL:

		mov	r0, lr
		bl	_printhex8

/*
 * config port C pins as GPIO output
 */
		ldr	r4, =NETARM_GEN_MODULE_BASE
		ldr	r1, [r4, #+NETARM_GEN_PORTC]
		ldr	r2, =((0xFFFFFFFF) ^ \
		                (NETARM_GEN_PORT_MODE(NA_BLINK_LED | NA_FAIL_LED) | \
			         NETARM_GEN_PORT_DIR(NA_BLINK_LED | NA_FAIL_LED)))
		and	r1, r1, r2
		ldr	r2, =(NETARM_GEN_PORT_DIR(0x06))
		orr	r1, r1, r2
		orr	r1, r1, #(NA_BLINK_LED | NA_FAIL_LED)
		eor	r1, r1, #NA_FAIL_LED
		str	r1, [r4, #+NETARM_GEN_PORTC]
/*
 * turn the LED off ( output high )
 */
1:
		eor	r1, r1, #(NA_BLINK_LED | NA_FAIL_LED)
		str	r1, [r4, #+NETARM_GEN_PORTC]
/*
 * wait a bit - million iterations, give or take
 */
		mov	r2, #0x20000
2:
		subs	r2, r2, #1
		bgt	2b

		b 	1b		

		.globl	_netarm_led_FAIL2
_netarm_led_FAIL2:

		mov	r0, lr
		bl	_printhex8

/*
 * config port C "blink" pin as GPIO output
 */
		ldr	r4, =NETARM_GEN_MODULE_BASE
		ldr	r1, [r4, #+NETARM_GEN_PORTC]
		ldr	r2, =((0xFFFFFFFF) ^ (NETARM_GEN_PORT_MODE(NA_BLINK_LED) | \
			                      NETARM_GEN_PORT_DIR(NA_BLINK_LED)))
		and	r1, r1, r2
		ldr	r2, =(NETARM_GEN_PORT_DIR(NA_BLINK_LED))
		orr	r1, r1, r2
		orr	r1, r1, #(NA_BLINK_LED | NA_FAIL_LED)
		eor	r1, r1, #NA_FAIL_LED
		str	r1, [r4, #+NETARM_GEN_PORTC]
/*
 * turn the LED off ( output high )
 */
1:
		eor	r1, r1, #(NA_BLINK_LED)
		str	r1, [r4, #+NETARM_GEN_PORTC]
/*
 * wait a bit - 64k iterations, give or take
 */
		mov	r2, #0x10000
2:
		subs	r2, r2, #1
		bgt	2b

		b 	1b		

_netarm_debug_serial_init:
/* step 0... make sure pins are configured for serial */
		ldr	r4, =NETARM_GEN_MODULE_BASE
		
		ldr	r1, =( NETARM_GEN_PORT_MODE(0xef) | \
			       NETARM_GEN_PORT_DIR(0xe0) )
		str	r1, [r4, #+NETARM_GEN_PORTA]
		str	r1, [r4, #+NETARM_GEN_PORTB]

		ldr	r4, =NETARM_SER_MODULE_BASE
		
/* first turn em off */
		mov	r1, #0
		str	r1, [r4, #+NETARM_SER_CH1_CTRL_A]
		str	r1, [r4, #+NETARM_SER_CH2_CTRL_A]
		
/* clear match register */
@		mov	r1, #0
		str	r1, [r4, #+NETARM_SER_CH1_RX_MATCH]
		str	r1, [r4, #+NETARM_SER_CH2_RX_MATCH]

/* setup bit rate generator */
		ldr	r1, =NETARM_SER_BR_X16(DEFAULT_BAUD_RATE)
		str	r1, [r4, #+NETARM_SER_CH1_BITRATE]
		str	r1, [r4, #+NETARM_SER_CH2_BITRATE]

/* setup rx buffer gap timer */
		ldr	r1, =NETARM_SER_RXGAP(DEFAULT_BAUD_RATE)
		str	r1, [r4, #+NETARM_SER_CH1_RX_BUF_TMR]
		str	r1, [r4, #+NETARM_SER_CH2_RX_BUF_TMR]

/* setup port mode */		
		mov	r1, #NETARM_SER_CTLB_UART_MODE
		str	r1, [r4, #+NETARM_SER_CH1_CTRL_B]
		str	r1, [r4, #+NETARM_SER_CH2_CTRL_B]

		ldr	r1, =( NETARM_SER_CTLA_ENABLE |		\
			       NETARM_SER_CTLA_P_NONE |		\
			       NETARM_SER_CTLA_2STOP | 		\
			       NETARM_SER_CTLA_8BITS |		\
			       NETARM_SER_CTLA_DTR_EN |		\
			       NETARM_SER_CTLA_RTS_EN)
		str	r1, [r4, #+NETARM_SER_CH1_CTRL_A]
		str	r1, [r4, #+NETARM_SER_CH2_CTRL_A]

		mov	pc, lr		

_netarm_debug_serial_dump:
		ldr	r9, =NETARM_SER_MODULE_BASE
		mov	r10, lr
		
		ldr	r0, =_serial_hdr
		bl	_printascii

		mov	r0, #'\n'
		bl	_printch

/* read control A */
		ldr	r0, =_serial_ctla
		bl	_printascii

		ldr	r0, [r9, #+NETARM_SER_CH1_CTRL_A]
		bl	_printhex8
		mov	r0, #' '
		bl	_printch
		
		ldr	r0, [r9, #+NETARM_SER_CH2_CTRL_A]
		bl	_printhex8
		mov	r0, #'\n'
		bl	_printch

/* read control A */
		ldr	r0, =_serial_ctlb
		bl	_printascii

		ldr	r0, [r9, #+NETARM_SER_CH1_CTRL_B]
		bl	_printhex8
		mov	r0, #' '
		bl	_printch
		
		ldr	r0, [r9, #+NETARM_SER_CH2_CTRL_B]
		bl	_printhex8
		mov	r0, #'\n'
		bl	_printch

/* read match register */
		ldr	r0, =_serial_mr
		bl	_printascii

		ldr	r0, [r9, #+NETARM_SER_CH1_RX_MATCH]
		bl	_printhex8
		mov	r0, #' '
		bl	_printch

		ldr	r0, [r9, #+NETARM_SER_CH2_RX_MATCH]
		bl	_printhex8
		mov	r0, #'\n'
		bl	_printch

/* bit rate generator */
		ldr	r0, =_serial_brr
		bl	_printascii

		ldr	r0, [r9, #+NETARM_SER_CH1_BITRATE]
		bl	_printhex8
		mov	r0, #' '
		bl	_printch
		
		ldr	r0, [r9, #+NETARM_SER_CH2_BITRATE]
		bl	_printhex8
		mov	r0, #'\n'
		bl	_printch
		
/* rx buffer gap timer */
		ldr	r0, =_serial_bgt
		bl	_printascii

		ldr	r0, [r9, #+NETARM_SER_CH1_RX_BUF_TMR]
		bl	_printhex8
		mov	r0, #' '
		bl	_printch

		ldr	r0, [r9, #+NETARM_SER_CH2_RX_BUF_TMR]
		bl	_printhex8
		mov	r0, #'\n'
		bl	_printch

		mov	lr, r10
		mov	pc, lr		

_netarm_debug_mem_ctl_dump:
		ldr	r9, =NETARM_MEM_MODULE_BASE
		mov	r10, lr
		
		ldr	r0, =_memctl_hdr
		bl	_printascii

/* MMCR */
		ldr	r0, [r9, #+NETARM_MEM_MODULE_CONFIG]
		bl	_printhex8

		mov	r0, #'\n'
		bl	_printch
		
/* CS0 BAR */
		ldr	r0, =_memctl_bar1
		bl	_printascii

		mov	r0, #0
		bl	_printhex2

		ldr	r0, =_memctl_bar2
		bl	_printascii

		ldr	r0, [r9, #+NETARM_MEM_CS0_BASE_ADDR]
		bl	_printhex8
		
		mov	r0, #'\n'
		bl	_printch
		
/* CS0 OPT */
		ldr	r0, =_memctl_opt1
		bl	_printascii

		mov	r0, #0
		bl	_printhex2

		ldr	r0, =_memctl_opt2
		bl	_printascii

		ldr	r0, [r9, #+NETARM_MEM_CS0_OPTIONS]
		bl	_printhex8
		
		mov	r0, #'\n'
		bl	_printch
		
/* CS1 BAR */
		ldr	r0, =_memctl_bar1
		bl	_printascii

		mov	r0, #1
		bl	_printhex2

		ldr	r0, =_memctl_bar2
		bl	_printascii

		ldr	r0, [r9, #+NETARM_MEM_CS1_BASE_ADDR]
		bl	_printhex8
		
		mov	r0, #'\n'
		bl	_printch
		
/* CS1 OPT */
		ldr	r0, =_memctl_opt1
		bl	_printascii

		mov	r0, #1
		bl	_printhex2

		ldr	r0, =_memctl_opt2
		bl	_printascii

		ldr	r0, [r9, #+NETARM_MEM_CS1_OPTIONS]
		bl	_printhex8
		
		mov	r0, #'\n'
		bl	_printch
		
/* CS2 BAR */
		ldr	r0, =_memctl_bar1
		bl	_printascii

		mov	r0, #2
		bl	_printhex2

		ldr	r0, =_memctl_bar2
		bl	_printascii

		ldr	r0, [r9, #+NETARM_MEM_CS2_BASE_ADDR]
		bl	_printhex8
		
		mov	r0, #'\n'
		bl	_printch
		
/* CS2 OPT */
		ldr	r0, =_memctl_opt1
		bl	_printascii

		mov	r0, #2
		bl	_printhex2

		ldr	r0, =_memctl_opt2
		bl	_printascii

		ldr	r0, [r9, #+NETARM_MEM_CS2_OPTIONS]
		bl	_printhex8
		
		mov	r0, #'\n'
		bl	_printch
		
/* CS3 BAR */
		ldr	r0, =_memctl_bar1
		bl	_printascii

		mov	r0, #3
		bl	_printhex2

		ldr	r0, =_memctl_bar2
		bl	_printascii

		ldr	r0, [r9, #+NETARM_MEM_CS3_BASE_ADDR]
		bl	_printhex8
		
		mov	r0, #'\n'
		bl	_printch
		
/* CS3 OPT */
		ldr	r0, =_memctl_opt1
		bl	_printascii

		mov	r0, #3
		bl	_printhex2

		ldr	r0, =_memctl_opt2
		bl	_printascii

		ldr	r0, [r9, #+NETARM_MEM_CS3_OPTIONS]
		bl	_printhex8
		
		mov	r0, #'\n'
		bl	_printch
		
/* CS4 BAR */
		ldr	r0, =_memctl_bar1
		bl	_printascii

		mov	r0, #4
		bl	_printhex2

		ldr	r0, =_memctl_bar2
		bl	_printascii

		ldr	r0, [r9, #+NETARM_MEM_CS4_BASE_ADDR]
		bl	_printhex8
		
		mov	r0, #'\n'
		bl	_printch
		
/* CS4 OPT */
		ldr	r0, =_memctl_opt1
		bl	_printascii

		mov	r0, #4
		bl	_printhex2

		ldr	r0, =_memctl_opt2
		bl	_printascii

		ldr	r0, [r9, #+NETARM_MEM_CS4_OPTIONS]
		bl	_printhex8
		
		mov	r0, #'\n'
		bl	_printch
		
/* return */

		mov	lr, r10
		mov	pc, lr		

#if 1
/*
 * Useful debugging routines
 */
		.globl	_printhex8
_printhex8:	mov	r1, #8
		b	printhex

		.globl	_printhex4
_printhex4:	mov	r1, #4
		b	printhex

		.globl	_printhex2
_printhex2:	mov	r1, #2
printhex:	ldr	r2, =hexbuf
		add	r3, r2, r1
		mov	r1, #0
		strb	r1, [r3]
1:		and	r1, r0, #15
		mov	r0, r0, lsr #4
		cmp	r1, #10
		addlt	r1, r1, #'0'
		addge	r1, r1, #'a' - 10
		strb	r1, [r3, #-1]!
		teq	r3, r2
		bne	1b
		mov	r0, r2

		.globl	_printascii
_printascii:
		ldr	r3, =NETARM_SER_MODULE_BASE
		b	3f
1:		
		ldr	r2, [r3, #+NETARM_SER_CH1_STATUS_A]
		tst	r2, #NETARM_SER_STATA_TX_RDY
		beq	1b
		strb	r1, [r3, #+NETARM_SER_CH1_FIFO]
		teq	r1, #'\n'
		moveq	r1, #'\r'
		beq	1b
3:		teq	r0, #0
		ldrneb	r1, [r0], #1
		teqne	r1, #0
		bne	1b
		mov	pc, lr

		.globl	_printch
_printch:
@#ifdef CONFIG_ARCH_RPC
@		mov	r3, #0xe0000000
@		orr	r3, r3, #0x00010000
@		orr	r3, r3, #0x00000fe0
@#else
@		mov	r3, #0xf0000000
@		orr	r3, r3, #0x0be0
@#endif
		ldr	r3, =NETARM_SER_MODULE_BASE
		mov	r1, r0
		mov	r0, #0
		b	1b

/*
 * Useful debugging routine: List first 8 words
 */
		.globl	_printexcvectors
_printexcvectors:
		mov	r10, lr
		ldr	r0, =_excvec_hdr
		bl	_printascii

		mov	r9,#0
1:		ldr	r0, [r9], #4
		bl	_printhex8
		mov	r0, #'\n'
		bl	_printch
		cmp	r9, #32
		bne	1b

		mov	lr, r10
		mov	pc,lr

/*
 * Useful debugging routines
 */
		.globl	_printhex8
_printhex8_b:	mov	r1, #8
		b	printhex

		.globl	_printhex4
_printhex4_b:	mov	r1, #4
		b	printhex

		.globl	_printhex2
_printhex2_b:	mov	r1, #2
printhex_b:	ldr	r2, =hexbuf
		add	r3, r2, r1
		mov	r1, #0
		strb	r1, [r3]
1:		and	r1, r0, #15
		mov	r0, r0, lsr #4
		cmp	r1, #10
		addlt	r1, r1, #'0'
		addge	r1, r1, #'a' - 10
		strb	r1, [r3, #-1]!
		teq	r3, r2
		bne	1b
		mov	r0, r2

		.globl	_printascii_b
_printascii_b:
@#ifdef CONFIG_ARCH_RPC
@		mov	r3, #0xe0000000
@		orr	r3, r3, #0x00010000
@		orr	r3, r3, #0x00000fe0
@#else
@		mov	r3, #0xf0000000
@		orr	r3, r3, #0x0be0
@#endif
		ldr	r3, =NETARM_SER_MODULE_BASE
		b	3f
@1:		ldrb	r2, [r3, #0x18]
@		tst	r2, #0x10
@		beq	1b
1:		
		ldr	r2, [r3, #+NETARM_SER_CH1_STATUS_A]
		tst	r2, #NETARM_SER_STATA_TX_RDY
		beq	1b
@		strb	r1, [r3]
		strb	r1, [r3, #+NETARM_SER_CH1_FIFO]
@2:		ldrb	r2, [r3, #0x14]
@		and	r2, r2, #0x60
@		teq	r2, #0x60
@		bne	2b
		teq	r1, #'\n'
		moveq	r1, #'\r'
		beq	1b
3:		teq	r0, #0
		ldrneb	r1, [r0], #1
		teqne	r1, #0
		bne	1b
		mov	pc, lr

		.globl	_printch
_printch_b:
@#ifdef CONFIG_ARCH_RPC
@		mov	r3, #0xe0000000
@		orr	r3, r3, #0x00010000
@		orr	r3, r3, #0x00000fe0
@#else
@		mov	r3, #0xf0000000
@		orr	r3, r3, #0x0be0
@#endif
		ldr	r3, =NETARM_SER_MODULE_BASE
		mov	r1, r0
		mov	r0, #0
		b	1b

#endif

/*  These values should stay in sync with linux/kernel.h */
L_STACK_MAGIC:
		.long 0xdeadbeef
L_STACK_UNTOUCHED_MAGIC:
		.long 0xfeef1ef0

		.data
		.align	12
_hello_world:	.ascii	"NET+Lx Bootloader v0.9\n\0"
_serial_hdr:	.ascii	"Serial Configuration:\n"
		.ascii	"Channel               01       02\0"
_serial_ctla:	.ascii	"Serial Control A : \0"
_serial_ctlb:	.ascii	"Serial Control B : \0"
_serial_bgt:	.ascii	"Buffer Gap Timer : \0"
_serial_brr:	.ascii	"Bit Rate Control : \0"
_serial_mr:	.ascii	"Match Register   : \0"
_memctl_hdr:	.ascii	"Memory Control Module Configuration:\n"
		.ascii	"Mem Config Reg   : \0"
_memctl_bar1:	.ascii	"BAR\0"
_memctl_bar2:	.ascii	"            : \0"
_memctl_opt1:	.ascii	"OPT\0"
_memctl_opt2:	.ascii	"            : \0"
_excvec_hdr:	.ascii	"Exception vectors (0x00-0x1C):\n\0"

#ifdef	CONFIG_BLK_DEV_RAMDISK_DATA

		.align	12
		.globl	__ramdisk_data
__ramdisk_data:
#include "ramdisk.inc"
		.globl	__ramdisk_data_end
__ramdisk_data_end:
		.align
	
#endif

		.align	8
LC0:		.long	__bss_start
        	.long	processor_id
        	.long	_end
		.long   __machine_arch_type
        	.long	init_task_union+8192

		.section	.rodata
		.align	12
__zzzz:		.space	16
		.align

		.bss
		.align	12
hexbuf:		.space 16
		.align