740.diff

这是一个SIGMA方案的PMP播放器的UCLINUX程序,可播放DVD,VCD,CD MP3...有很好的参考价值.

--- proc-arm720.S	Wed Jul 25 06:52:44 2001
+++ proc-arm740.S	Mon Feb 25 19:32:52 2002
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720
+ *  linux/arch/arm/mm/proc-arm740.S: MMU functions for ARM740
  *
  *  Copyright (C) 2000 Steve Hill ([e-mail])
  *                     Rob Scott ([e-mail])
@@ -29,6 +29,7 @@
  *			out of 'proc-arm6,7.S' per RMK discussion
  *   07-25-2000 SJH	Added idle function.
  *   08-25-2000	DBS	Updated for integration of ARM Ltd version.
+ *   12-03-2001 FG      Forked 740 function from 720
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
@@ -37,8 +38,8 @@
 #include <asm/hardware.h>
 
 /*
- * Function: arm720_cache_clean_invalidate_all (void)
- *	   : arm720_cache_clean_invalidate_page (unsigned long address, int size,
+ * Function: arm740_cache_clean_invalidate_all (void)
+ *	   : arm740_cache_clean_invalidate_page (unsigned long address, int size,
  *                                    int flags)
  *
  * Params  : address	Area start address
@@ -47,11 +48,11 @@
  *
  * Purpose : Flush all cache lines
  */
-ENTRY(cpu_arm720_cache_clean_invalidate_all)
-ENTRY(cpu_arm720_cache_clean_invalidate_range)
-ENTRY(cpu_arm720_icache_invalidate_range)
-ENTRY(cpu_arm720_icache_invalidate_page)
-ENTRY(cpu_arm720_dcache_invalidate_range)
+ENTRY(cpu_arm740_cache_clean_invalidate_all)
+ENTRY(cpu_arm740_cache_clean_invalidate_range)
+ENTRY(cpu_arm740_icache_invalidate_range)
+ENTRY(cpu_arm740_icache_invalidate_page)
+ENTRY(cpu_arm740_dcache_invalidate_range)
 		mov	r0, #0
 		mcr	p15, 0, r0, c7, c7, 0		@ flush cache
 		mov	pc, lr
@@ -60,24 +61,24 @@
  * These just expect cache lines to be cleaned.  Since we have a writethrough
  * cache, we never have any dirty cachelines to worry about.
  */
-ENTRY(cpu_arm720_dcache_clean_range)
-ENTRY(cpu_arm720_dcache_clean_page)
-ENTRY(cpu_arm720_dcache_clean_entry)
-ENTRY(cpu_arm720_flush_ram_page)
+ENTRY(cpu_arm740_dcache_clean_range)
+ENTRY(cpu_arm740_dcache_clean_page)
+ENTRY(cpu_arm740_dcache_clean_entry)
+ENTRY(cpu_arm740_flush_ram_page)
 		mov	pc, lr
 
 /*
- * Function: arm720_tlb_invalidate_all (void)
+ * Function: arm740_tlb_invalidate_all (void)
  *
  * Purpose : flush all TLB entries in all caches
  */
-ENTRY(cpu_arm720_tlb_invalidate_all)
+ENTRY(cpu_arm740_tlb_invalidate_all)
 		mov	r0, #0
 		mcr	p15, 0, r0, c8, c7, 0		@ flush TLB (v4)
 		mov	pc, lr
 
 /*
- * Function: arm720_tlb_invalidate_page (unsigned long address, int end, int flags)
+ * Function: arm740_tlb_invalidate_page (unsigned long address, int end, int flags)
  *
  * Params  : address	Area start address
  *	   : end	Area end address
@@ -85,7 +86,7 @@
  *
  * Purpose : flush a TLB entry
  */
-ENTRY(cpu_arm720_tlb_invalidate_range)
+ENTRY(cpu_arm740_tlb_invalidate_range)
 1:		mcr	p15, 0, r0, c8, c7, 1		@ flush TLB (v4)
 		add	r0, r0, #4096
 		cmp	r0, r1
@@ -93,19 +94,19 @@
 		mov	pc, lr
 
 /*
- * Function: arm720_tlb_invalidate_page (unsigned long address, int flags)
+ * Function: arm740_tlb_invalidate_page (unsigned long address, int flags)
  *
  * Params  : address	Address
  *	   : flags	b0 = I-TLB as well
  *
  * Purpose : flush a TLB entry
  */
-ENTRY(cpu_arm720_tlb_invalidate_page)
+ENTRY(cpu_arm740_tlb_invalidate_page)
 		mcr	p15, 0, r0, c8, c7, 1		@ flush TLB (v4)
 		mov	pc, lr
 
 /*
- * Function: arm720_data_abort ()
+ * Function: arm740_data_abort ()
  *
  * Params  : r0 = address of aborted instruction
  *
@@ -142,7 +143,7 @@
 		and	r3, r3, #255
 		mov	pc, lr
 
-ENTRY(cpu_arm720_data_abort)
+ENTRY(cpu_arm740_data_abort)
 		ldr	r4, [r0]			@ read instruction causing problem
 		tst	r4, r4, lsr #21			@ C = bit 20
 		sbc	r1, r1, r1			@ r1 = C - 1
@@ -256,22 +257,22 @@
 		b	Ldata_saver7
 
 /*
- * Function: arm720_check_bugs (void)
- *	   : arm720_proc_init (void)
- *	   : arm720_proc_fin (void)
+ * Function: arm740_check_bugs (void)
+ *	   : arm740_proc_init (void)
+ *	   : arm740_proc_fin (void)
  *
  * Notes   : This processor does not require these
  */
-ENTRY(cpu_arm720_check_bugs)
+ENTRY(cpu_arm740_check_bugs)
 		mrs	ip, cpsr
 		bic	ip, ip, #F_BIT
 		msr	cpsr, ip
 		mov	pc, lr
 
-ENTRY(cpu_arm720_proc_init)
+ENTRY(cpu_arm740_proc_init)
 		mov	pc, lr
 
-ENTRY(cpu_arm720_proc_fin)
+ENTRY(cpu_arm740_proc_fin)
 		stmfd	sp!, {lr}
 		mov	ip, #F_BIT | I_BIT | SVC_MODE
 		msr	cpsr_c, ip
@@ -283,20 +284,20 @@
 		ldmfd	sp!, {pc}
 
 /*
- * Function: arm720_proc_do_idle(void)
+ * Function: arm740_proc_do_idle(void)
  * Params  : r0 = unused
  * Purpose : put the processer in proper idle mode
  */
-ENTRY(cpu_arm720_do_idle)
+ENTRY(cpu_arm740_do_idle)
 		mov	pc, lr
 
 /*
- * Function: arm720_set_pgd(unsigned long pgd_phys)
+ * Function: arm740_set_pgd(unsigned long pgd_phys)
  * Params  : pgd_phys	Physical address of page table
  * Purpose : Perform a task switch, saving the old process' state and restoring
  *	     the new.
  */
-ENTRY(cpu_arm720_set_pgd)
+ENTRY(cpu_arm740_set_pgd)
 		mov	r1, #0
 		mcr	p15, 0, r1, c7, c7, 0		@ invalidate cache
 		mcr	p15, 0, r0, c2, c0, 0		@ update page table ptr
@@ -304,27 +305,27 @@
 		mov	pc, lr
 
 /*
- * Function: arm720_set_pmd ()
+ * Function: arm740_set_pmd ()
  *
  * Params  : r0 = Address to set
  *	   : r1 = value to set
  *
  * Purpose : Set a PMD and flush it out of any WB cache
  */
-ENTRY(cpu_arm720_set_pmd)
+ENTRY(cpu_arm740_set_pmd)
 		tst	r1, #3
 		orrne	r1, r1, #16			@ Updatable bit is
 		str	r1, [r0]			@ always set on ARM720
 		mov	pc, lr
 
 /*
- * Function: arm720_set_pte(pte_t *ptep, pte_t pte)
+ * Function: arm740_set_pte(pte_t *ptep, pte_t pte)
  * Params  : r0 = Address to set
  *	   : r1 = value to set
  * Purpose : Set a PTE and flush it out of any WB cache
  */
 		.align	5
-ENTRY(cpu_arm720_set_pte)
+ENTRY(cpu_arm740_set_pte)
 		str	r1, [r0], #-1024		@ linux version
 
 		eor	r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY
@@ -346,40 +347,65 @@
 		mov	pc, lr
 
 /*
- * Function: arm720_reset
+ * Function: arm740_reset
  * Params  : r0 = address to jump to
  * Notes   : This sets up everything for a reset
  */
-ENTRY(cpu_arm720_reset)
+ENTRY(cpu_arm740_reset)
 		mov	ip, #0
 		mcr	p15, 0, ip, c7, c7, 0		@ invalidate cache
 		mcr	p15, 0, ip, c8, c7, 0		@ flush TLB (v4)
 		mrc	p15, 0, ip, c1, c0, 0		@ get ctrl register
-		bic	ip, ip, #0x000f			@ ............wcam
-		bic	ip, ip, #0x2100			@ ..v....s........
+		bic	ip, ip, #0x000e				@ ............wcam
 		mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
 		mov	pc, r0
 
 	
 cpu_armvlsi_name:
 		.asciz	"ARM"
-cpu_arm720_name:
-		.asciz	"ARM720T"
+cpu_arm740_name:
+		.asciz	"ARM740T"
 		.align
 
 		.section ".text.init", #alloc, #execinstr
 
-__arm720_setup:	mov	r0, #0
+__arm740_setup:
+
+@setup memory regions
+@ 
+
+		mov	r0, #0
 		mcr	p15, 0, r0, c7, c7, 0		@ invalidate caches
-		mcr	p15, 0, r0, c8, c7, 0		@ flush TLB (v4)
-		mcr	p15, 0, r4, c2, c0		@ load page table pointer
-		mov	r0, #0x1f			@ Domains 0, 1 = client
-		mcr	p15, 0, r0, c3, c0		@ load domain access register
+
+		mov r0, #0x0					@disable region 3-7
+		mcr p15, 0, r0, c6, c3
+		mcr p15, 0, r0, c6, c4
+		mcr p15, 0, r0, c6, c5
+		mcr p15, 0, r0, c6, c6
+		mcr p15, 0, r0, c6, c7
+	
+
+		mov r0, #0x0000003F			@ (base = 0, size = 4GB, non cacheable, no write buffer)
+		mcr p15, 0, r0, c6,	c0		@ enable region 0, default
+		mov r0, #0x00000037			@ (base = 0, size = 256MB, cacheable, write buffered)
+		mcr p15, 0, r0, c6,	c1		@enable region 1, RAM
+		mov r0, #0x20000000
+		add r0, r0, #0x37			@ (base = 512MB, size = 256MB, cacheable, write buffered)
+		mcr p15, 0, r0, c6,	c2		@enable region 2, ROM/Flash
+
+		mov r0, #0x06				
+		mcr p15, 0, r0, c2, c0		@ Region 1&2 cacheable
+		mov r0, #0x02			
+		mcr p15, 0, r0, c3, c0		@ Region 1 write buferred
+
+		mov r0, #0xff00
+		add r0, r0, #0x00ff
+		mcr p15, 0, r0, c5, c0		@ all read/write access
 
 		mrc	p15, 0, r0, c1, c0		@ get control register
-		bic	r0, r0, #0x0e00			@ ..V. ..RS BLDP WCAM
-		orr	r0, r0, #0x2100			@ .... .... .111 .... (old)
-		orr	r0, r0, #0x003d			@ ..1. ..01 ..11 1101 (new)
+		orr r0, r0, #0x00030000		@ Split cache mode
+		orr	r0, r0, #0x0000000d		@ MPU, Cache, Write Buffer on
+	
 		mov	pc, lr				@ __ret (head-armv.S)
 
 /*
@@ -387,45 +413,45 @@
  *	     come through these
  */
 		.type	arm720_processor_functions, #object
-ENTRY(arm720_processor_functions)
-		.word	cpu_arm720_data_abort
-		.word	cpu_arm720_check_bugs
-		.word	cpu_arm720_proc_init
-		.word	cpu_arm720_proc_fin
-		.word	cpu_arm720_reset
-		.word	cpu_arm720_do_idle
+ENTRY(arm740_processor_functions)
+		.word	cpu_arm740_data_abort
+		.word	cpu_arm740_check_bugs
+		.word	cpu_arm740_proc_init
+		.word	cpu_arm740_proc_fin
+		.word	cpu_arm740_reset
+		.word	cpu_arm740_do_idle
 
 		/* cache */
-		.word	cpu_arm720_cache_clean_invalidate_all
-		.word	cpu_arm720_cache_clean_invalidate_range
-		.word	cpu_arm720_flush_ram_page
+		.word	cpu_arm740_cache_clean_invalidate_all
+		.word	cpu_arm740_cache_clean_invalidate_range
+		.word	cpu_arm740_flush_ram_page
 
 		/* dcache */
-		.word	cpu_arm720_dcache_invalidate_range
-		.word	cpu_arm720_dcache_clean_range
-		.word	cpu_arm720_dcache_clean_page
-		.word	cpu_arm720_dcache_clean_entry
+		.word	cpu_arm740_dcache_invalidate_range
+		.word	cpu_arm740_dcache_clean_range
+		.word	cpu_arm740_dcache_clean_page
+		.word	cpu_arm740_dcache_clean_entry
 
 		/* icache */
-		.word	cpu_arm720_icache_invalidate_range
-		.word	cpu_arm720_icache_invalidate_page
+		.word	cpu_arm740_icache_invalidate_range
+		.word	cpu_arm740_icache_invalidate_page
 
 		/* tlb */
-		.word	cpu_arm720_tlb_invalidate_all
-		.word	cpu_arm720_tlb_invalidate_range
-		.word	cpu_arm720_tlb_invalidate_page
+		.word	cpu_arm740_tlb_invalidate_all
+		.word	cpu_arm740_tlb_invalidate_range
+		.word	cpu_arm740_tlb_invalidate_page
 
 		/* pgtable */
-		.word	cpu_arm720_set_pgd
-		.word	cpu_arm720_set_pmd
-		.word	cpu_arm720_set_pte
-		.size	arm720_processor_functions, . - arm720_processor_functions
+		.word	cpu_arm740_set_pgd
+		.word	cpu_arm740_set_pmd
+		.word	cpu_arm740_set_pte
+		.size	arm740_processor_functions, . - arm740_processor_functions
 
-		.type	cpu_arm720_info, #object
-cpu_arm720_info:
+		.type	cpu_arm740_info, #object
+cpu_arm740_info:
 		.long	cpu_armvlsi_name
-		.long	cpu_arm720_name
-		.size	cpu_arm720_info, . - cpu_arm720_info
+		.long	cpu_arm740_name
+		.size	cpu_arm740_info, . - cpu_arm70_info
 	
 		.type	cpu_arch_name, #object
 cpu_arch_name:	.asciz	"armv4"
@@ -442,15 +468,15 @@
 	
 		.section ".proc.info", #alloc, #execinstr
 
-		.type	__arm720_proc_info, #object
-__arm720_proc_info:
-		.long	0x41807200				@ cpu_val
-		.long	0xffffff00				@ cpu_mask
+		.type	__arm740_proc_info, #object
+__arm740_proc_info:
+		.long	0x41807400				@ cpu_val
+		.long	0xfffffF00				@ cpu_mask
 		.long	0x00000c1e				@ section_mmu_flags
-		b	__arm720_setup				@ cpu_flush
+		b	__arm740_setup				@ cpu_flush
 		.long	cpu_arch_name				@ arch_name
 		.long	cpu_elf_name				@ elf_name
 		.long	HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT	@ elf_hwcap
-		.long	cpu_arm720_info				@ info
-		.long	arm720_processor_functions
-		.size	__arm720_proc_info, . - __arm720_proc_info
+		.long	cpu_arm740_info				@ info
+		.long	arm740_processor_functions
+		.size	__arm740_proc_info, . - __arm740_proc_info