fs400.h

这是一个SIGMA方案的PMP播放器的UCLINUX程序,可播放DVD,VCD,CD MP3...有很好的参考价值.

/*--------------------------------------------------------------------------------

	FS400.h
	
	This file contains all of the constants used to access the FS400 registers.

-------------------------------------------------------------------------------*/

// NOTE: #define FS400_LOW_LEVEL to obtain access to the FS400 low level registers
// NOTE: #define FS400_DEBUG to obtain access to the FS400 debug registers

#ifndef	_FS400_H_
#define	_FS400_H_

//--------------------------------------------------
//			FS400 I2C Address
//--------------------------------------------------

// There are two 7-bit addresses, 0x4A and 0x6A. 
// The address if selectable via pins on the FS40x
// There are also two 10-bit addresses, 0x224 and 0x276,
// however, the source is not designed to used them.

#define	FS400_I2C_ADDRESS		(0x4A << 1) // Address shifted left by one to make room for Read/Write bit 

//--------------------------------------------------
//			FS400 Register Addresses
//--------------------------------------------------

	// FS400 Version Number

#define	FS400_VERSION			0x1E	// Current version number (binary ... 0x1E = version 30)

	// Low Level Hardware Register Addresses

#ifdef	FS400_LOW_LEVEL
#define	FS400_IHO				0x00	// Input Horizontal Offset
#define	FS400_IVO				0x02	// Input Vertical Offset
#define	FS400_IHA				0x04	// Input Horizontal Active Width
#define	FS400_ILS				0x06	// Input Lines Stored
#define	FS400_IHS				0x08	// Input Horizontal Samples
#define	FS400_IHC				0x0A	// Input Horizontal Count
#define	FS400_IVC				0x0C	// Input Horizontal Count
#define	FS400_VSC				0x0E	// Vertical Scaling Coeficient
#define	FS400_CR				0x10	// Control Register
#define	FS400_SR				0x12	// Status Register
#define	FS400_CRE				0x14	// Control Register Extended
#define	FS400_SHV				0x16	// Start Horizontal Video
#define	FS400_EHV				0x18	// End Horizontal Video
#define	FS400_SVV				0x1A	// Start Vertical Video
#define	FS400_EVV				0x1C	// End Vertical Video
#define	FS400_AVT				0x1E	// Active Video Threshold
#define	FS400_OHO				0x20	// Output Horizontal Offset
#define	FS400_OVO				0x22	// Output Vertical Offset
#define	FS400_HSC				0x24	// Horizontal Scaling Coeficient
#define	FS400_FLK				0x2C	// Flicker Filter
#define	FS400_BIST				0x32	// Hardware BIST Register (Built-in self test)
#define	FS400_GPO				0x34	// General Purpose Output

#define	FS400_IHO_MASK			0x07FF
#define	FS400_IVO_MASK			0x0FFF
#define	FS400_IHA_MASK			0x03FF
#define	FS400_ILS_MASK			0x03FF
#define	FS400_IHS_MASK			0x07FF
#define	FS400_IHC_MASK			0x03FF
#define	FS400_IVC_MASK			0x0FFF
#define	FS400_VSC_MASK			0x00FF
#define	FS400_CR_MASK			0xFFFF
#define	FS400_SR_MASK			0x3F0F
#define	FS400_CRE_MASK			0xFF3F
#define	FS400_SHV_MASK			0x07FF
#define	FS400_EHV_MASK			0x07FF
#define	FS400_SVV_MASK			0x07FF
#define	FS400_EVV_MASK			0x07FF
#define	FS400_AVT_MASK			0x00FF
#define	FS400_OHO_MASK			0x07FF
#define	FS400_OVO_MASK			0x03FF
#define	FS400_HSC_MASK			0x01FF
#define	FS400_FLK_MASK			0x001F
#define	FS400_BIST_MASK			0xFFFF	// no description
#define	FS400_GPO_MASK			0x000F

#endif

// High Level Hardware Resgister Addresses
#define	FS400_CON				0x26	// Contrast
#define	FS400_BRT				0x28	// Brightness
#define	FS400_SHP				0x2A	// Sharpness
#define	FS400_CSC				0x2E	// Chroma Scale Coeficient

// High Level Software Register Addresses
#define	FS400_SCR				0x60	// Software Control Register
#define	FS400_SCR_FLK			0x60	//AA Software Control Register
#define	FS400_SSR				0x62	// Software Status Register
#define	FS400_HCRS				0x64	// Hardware Control Register Shadow
#define	FS400_HCRES				0x66	// Hardware Control Register Extended Shadow
#define	FS400_HPO				0x68	// Horizontal Position Offset
#define	FS400_VPO				0x6A	// Vertical Position Offset
#define	FS400_HSS				0x6C	// Horizontal Scale Step
#define	FS400_VSS				0x6E	// Vertical Scale Step
#define	FS400_HPP				0x70	// Horizontal Pan Position
#define	FS400_VPP				0x72	// Vertical Pan Position
#define	FS400_TVP				0x74	// TV Pixels
#define	FS400_TVL				0x76	// TV Lines
#define	FS400_CCR				0x78	// Configuration Command Register
#define	FS400_CDR				0x7A	// Configuration Data Register
#define	FS400_HOHOS				0x7C	// Hardware Output Horizontal Offset Shadow
#define	FS400_HOVOS				0x7E	// Hardware Ouptut Vertical Offset Shadow

//--------------------------------------------------
//			FS400 Register Field Definitions
//--------------------------------------------------

	// Input Horizontal Count

#ifdef	FS400_LOW_LEVEL
#define	IHC_THRESHOLD			4		// +-4
#endif

	// Input Vertical Count

#ifdef	FS400_LOW_LEVEL
#define	IVC_THRESHOLD			1		// +-1
#endif

	// Control Register

#ifdef	FS400_LOW_LEVEL
#define	CR_RESET				0x0001
#define	CR_CLKOFF				0x0002
#define	CR_ADCOFF				0x0004
#define	CR_COMPOFF				0x0008
#define	CR_YCOFF				0x0010
#define	CR_LNTCH				0x0020
#define	CR_CBP					0x0040
#define	CR_PEDSTL				0x0080
#define	CR_TV_CLK_SEL_MASK		0x0300
#define	CR_PROGINT				0x0400
#define	CR_PALNTSC				0x0800
#define	CR_OFMT_MASK			0x3000
#define	CR_OFMT_YC				0x0000
#define	CR_OFMT_COMP			0x0000
#define	CR_OFMT_RGB				0x1000
#define	CR_OFMT_YUV				0x2000
#endif

	// Control Register Extended

#ifdef	FS400_LOW_LEVEL
#define	CRE_ZOOM				0x0001
#define	CRE_RGBGAIN				0x0002
#define	CRE_FREEZE				0x0004
#define	CRE_VGACLKPOL			0x0008
#define	CRE_VGACLKREF			0x0010
#define	CRE_VGAINTDET			0x0020
#define	CRE_BIPGEN_MASK			0x0F00
#define	CRE_BIPGEN_TALL			0x0800
#define	CRE_BIPGEN_SHORT		0x0000
#define	CRE_BIPGEN_OFF			0x0000
#define	CRE_BIPGEN_ALL			0x0100
#define	CRE_BIPGEN_100B			0x0200
#define	CRE_BIPGEN_75B			0x0300
#define	CRE_BIPGEN_HATCH		0x0400
#define	CRE_BIPGEN_REDG			0x0500
#define	CRE_BIPGEN_GRNG			0x0600
#define	CRE_BIPGEN_BLUG			0x0700
#define	CRE_SVVCLR				0x1000
#define	CRE_EVVCLR				0x2000
#define	CRE_SHVCLR				0x4000
#define	CRE_EHVCLR				0x8000
#define	CRE_CLRALL				0xF000
#endif

	// Status Register

// Contrast Register
#define	CON_MIN					0
#define	CON_MAX					63
#define	CON_RANGE				64
#define	CON_RESET				32

// Brightness Register
#define	BRT_MIN					-128
#define	BRT_MAX					127
#define	BRT_RANGE				256
#define	BRT_RESET				0

// Sharpness Register
#define	SHP_MIN					0
#define	SHP_MAX					31
#define	SHP_RANGE				32
#define	SHP_RESET				8

// CSC Register
#define	CSC_MIN					0
#define	CSC_MAX					63
#define	CSC_RANGE				64
#define	CSC_RESET				32

//AA FLK Register
#define	FLK_MIN					0
#define	FLK_MAX					21
#define	FLK_RANGE				22
#define	FLK_RESET				0
//AA HPO Register
#define	HPO_MIN					-32768
#define	HPO_MAX					32767
#define	HPO_RANGE				65536
#define	HPO_RESET				0
//AA VPO Register
#define	VPO_MIN					-32768
#define	VPO_MAX					32767
#define	VPO_RANGE				65536
#define	VPO_RESET				0

//AA HSS Register
#define	HSS_MIN					-32768
#define	HSS_MAX					32767
#define	HSS_RANGE				65536
#define	HSS_RESET				0
//AA VSS Register
#define	VSS_MIN					-32768
#define	VSS_MAX					32767
#define	VSS_RANGE				65536
#define	VSS_RESET				0

//AA HPP Register
#define	HPP_MIN					-32768
#define	HPP_MAX					32767
#define	HPP_RANGE				65536
#define	HPP_RESET				0
//AA VPP Register
#define	VPP_MIN					-32768
#define VPP_MAX					32767
#define	VPP_RANGE				65536
#define	VPP_RESET				0

// used bits high level registers
#define	FS400_CON_MASK			0x003F
#define	FS400_BRT_MASK			0x00FF
#define	FS400_SHP_MASK			0x001F
#define	FS400_CSC_MASK			0x003F
#define	FS400_SCR_MASK			0xFFFF
#define	FS400_SSR_MASK			0xFFFF
#define	FS400_HCRS_MASK			0xFFFF
#define	FS400_HCRES_MASK		0xFFFF
#define	FS400_HPO_MASK			0xFFFF
#define	FS400_VPO_MASK			0xFFFF
#define	FS400_HSS_MASK			0xFFFF
#define	FS400_VSS_MASK			0xFFFF
#define	FS400_HPP_MASK			0xFFFF
#define	FS400_VPP_MASK			0xFFFF
#define	FS400_TVP_MASK			0xFFFF
#define	FS400_TVL_MASK			0xFFFF
#define	FS400_CCR_MASK			0xFFFF
#define	FS400_CDR_MASK			0xFFFF
#define	FS400_HOHOS_MASK		0xFFFF
#define	FS400_HOVOS_MASK		0xFFFF

	// General Programmable Output

#define	GPO_ANALOG_FILTER		0x0001

#define	GPO_MASK				GPO_ANALOG_FILTER

	// Software Control Register

#define	SCR_RESET				0x0001
#define	SCR_ENABLE				0x0002
#define	SCR_OCAL				0x0004
#define	SCR_CLRMCC				0x0008
#define	SCR_RSTVMODE			0x0010
#define	SCR_RSTICAL				0x0020
#define	SCR_RSTCALC				0x0040
#define	SCR_ENICTBL				0x0080
#define	SCR_DSICAL				0x0100
#define	SCR_DSVMDET				0x0200
#define	SCR_CNTRSML				0x0400
#define	SCR_MICALNEW			0x0800

#define	SCR_FLK_TICK			0x1000
#define	SCR_FLK_MASK			0xF000
#define	SCR_FLK_SHIFT			12
#define	SCR_FLK_MIN				0
#define	SCR_FLK_MAX				8
#define	SCR_FLK_RANGE			9
#define	SCR_FLK_RESET			8

	// Software Status Register

#define	SSR_READY				0x0001
#define	SSR_ERROR				0x0002
#define	SSR_MCS					0x0004
#define	SSR_MCC					0x0008
#define	SSR_ICALAQRD			0x0010
#define	SSR_VSYNCACT			0x0020
#define	SSR_HSYNCACT			0x0040
#define	SSR_CHECKSUM_MASK		0xFF00

	// Hardware Control Register Shadow

#define	HCRS_CLKOFF				0x0002
#define	HCRS_ADCOFF				0x0004
#define	HCRS_COMPOFF			0x0008
#define	HCRS_YCOFF				0x0010
#define	HCRS_LNTCH				0x0020
#define	HCRS_CBP				0x0040
#define	HCRS_PEDSTL				0x0080
#define	HCRS_TVCLK_MASK			0x0300
#define	HCRS_TVCLK0				0x0100
#define	HCRS_TVCLK1				0x0200
#define	HCRS_PROGINT			0x0400
#define	HCRS_PALNTSC			0x0800
#define	HCRS_IS_PAL				HCRS_PALNTSC
#define	HCRS_IS_NTSC			0x0000
#define	HCRS_OFMT_MASK			0x3000
#define	HCRS_OFMT0				0x1000
#define	HCRS_OFMT1				0x2000
#define	HCRS_OFMT_YC			0x0000
#define	HCRS_OFMT_COMP			0x0000
#define	HCRS_OFMT_RGB			0x1000
#define	HCRS_OFMT_YUV			0x2000
#define	HCRS_MASK				(HCRS_CLKOFF | HCRS_ADCOFF | HCRS_COMPOFF | HCRS_YCOFF | HCRS_LNTCH | HCRS_CBP | HCRS_PEDSTL | HCRS_TVCLK_MASK | HCRS_PROGINT | HCRS_PALNTSC | HCRS_OFMT_MASK)

#define	HCRS_LOWPWR				(HCRS_CLKOFF | HCRS_ADCOFF | HCRS_COMPOFF | HCRS_YCOFF)

#define	HCRS_SYSTEM_MASK		(HCRS_TVCLK_MASK | HCRS_PROGINT | HCRS_PALNTSC)
#define	HCRS_NTSC				0
#define	HCRS_PAL				HCRS_PALNTSC
#define	HCRS_SUPER_NTSC			HCRS_TVCLK1
#define	HCRS_SUPER_PAL			(HCRS_TVCLK1 | HCRS_PALNTSC)
#define	HCRS_VGA				(HCRS_TVCLK1 | HCRS_PROGINT)
#define	HCRS_SVGA				(HCRS_TVCLK1 | HCRS_PROGINT | HCRS_PALNTSC)
#define	HCRS_PROGRESSIVE_NTSC	(HCRS_TVCLK0 | HCRS_PROGINT)
#define	HCRS_100HZ_PAL			(HCRS_TVCLK0 | HCRS_PALNTSC)

#define	HCRS_SYSTEM_SHIFT		8

	// Hardware Control Register Extended Shadow

#define	HCRES_ZOOM				0x0001
#define	HCRES_RGBGAIN			0x0002
#define	HCRES_FREEZE			0x0004
#define	HCRES_VGAINTDET			0x0020
#define	HCRES_BIPGEN_MASK		0x0700
#define	HCRES_BIPGEN_ALL		0x0100
#define	HCRES_BIPGEN_100B		0x0200
#define	HCRES_BIPGEN_75B		0x0300
#define	HCRES_BIPGEN_HATCH		0x0400
#define	HCRES_BIPGEN_REDG		0x0500
#define	HCRES_BIPGEN_GRNG		0x0600
#define	HCRES_BIPGEN_BLUG		0x0700

#define	HCRES_MASK				(HCRES_ZOOM | HCRES_RGBGAIN | HCRES_FREEZE | HCRES_VGAINTDET)
#define	HCRES_MASK_OCAL			(HCRES_RGBGAIN | HCRES_FREEZE | HCRES_VGAINTDET | HCRES_BIPGEN_MASK)

	// Configuration Command Register

#define	CCR_COMPLETE			0x0000
#define	CCR_READ				0x0100
#define	CCR_WRITE				0x0200

#define	CCR_VERSION				0x0000
#define	CCR_FREQUENCY			0x0001
#define	CCR_FLT_FREQ			0x0002
#define	CCR_AVT					0x0003
#define	CCR_AVT_RGBGAIN			0x0004
#define	CCR_MIN_HAT				0x0005
#define	CCR_MAX_HAT				0x0006
#define	CCR_DEF_HAT				0x0007
#define	CCR_MIN_SHV				0x0008
#define	CCR_MAX_SHV				0x0009
#define	CCR_DEF_SHV				0x000A
#define	CCR_MIN_VAT				0x000B
#define	CCR_MAX_VAT				0x000C
#define	CCR_DEF_VAT				0x000D
#define	CCR_MIN_SVV				0x000E
#define	CCR_MAX_SVV				0x000F
#define	CCR_DEF_SVV				0x0010
#define	CCR_COUNTER				0x0011
#define	CCR_PIXEL_SIZE			0x0012
#define	CCR_LINE_SIZE			0x0013
#define	CCR_MICAL_HAT			0x0014
#define	CCR_MICAL_VAT			0x0015
#define	CCR_MICAL_SHV			0x0016
#define	CCR_MICAL_SVV			0x0017
#define	CCR_HSS_MIN				0x0018
#define	CCR_HSS_MAX				0x0019
#define	CCR_VSS_MIN				0x001A
#define	CCR_VSS_MAX				0x001B
#define	CCR_HPX_MIN				0x001C
#define	CCR_HPX_MAX				0x001D
#define	CCR_VPX_MIN				0x001E
#define	CCR_VPX_MAX				0x001F
#define	CCR_GPO					0x0020
#define	CCR_IHC					0x0021
#define	CCR_IVC					0x0022
#define	CCR_HAT					0x0023
#define	CCR_SHV					0x0024
#define	CCR_VAT					0x0025
#define	CCR_SVV					0x0026

#define	CCR_ICAL_TABLE			0x0027

#define	CCR_ICAL_TABLE_0		0x0027
#define	CCR_ICAL_TABLE_0_IVC	0x0027
#define	CCR_ICAL_TABLE_0_IHC	0x0028
#define	CCR_ICAL_TABLE_0_HAT	0x0029
#define	CCR_ICAL_TABLE_0_SHV	0x002A
#define	CCR_ICAL_TABLE_0_VAT	0x002B
#define	CCR_ICAL_TABLE_0_SVV	0x002C

#define	CCR_ICAL_TABLE_1		0x002D
#define	CCR_ICAL_TABLE_1_IVC	0x002D
#define	CCR_ICAL_TABLE_1_IHC	0x002E
#define	CCR_ICAL_TABLE_1_HAT	0x002F
#define	CCR_ICAL_TABLE_1_SHV	0x0030
#define	CCR_ICAL_TABLE_1_VAT	0x0031
#define	CCR_ICAL_TABLE_1_SVV	0x0032

#define	CCR_ICAL_TABLE_2		0x0033
#define	CCR_ICAL_TABLE_2_IVC	0x0033
#define	CCR_ICAL_TABLE_2_IHC	0x0034
#define	CCR_ICAL_TABLE_2_HAT	0x0035
#define	CCR_ICAL_TABLE_2_SHV	0x0036
#define	CCR_ICAL_TABLE_2_VAT	0x0037
#define	CCR_ICAL_TABLE_2_SVV	0x0038

#define	CCR_ICAL_TABLE_3		0x0039
#define	CCR_ICAL_TABLE_3_IVC	0x0039
#define	CCR_ICAL_TABLE_3_IHC	0x003A
#define	CCR_ICAL_TABLE_3_HAT	0x003B
#define	CCR_ICAL_TABLE_3_SHV	0x003C
#define	CCR_ICAL_TABLE_3_VAT	0x003D
#define	CCR_ICAL_TABLE_3_SVV	0x003E

#define	CCR_MAX					0x003E

#ifdef	FS400_DEBUG
#define	CCR_READ_MEM8			0x5100
#define	CCR_WRITE_MEM8			0x5200
#define	CCR_READ_MEM16			0x6100
#define	CCR_WRITE_MEM16			0x6200
#endif

#define	CCR_CMD_MASK			0xFF00
#define	CCR_ADDR_MASK			0x00FF

//--------------------------------------------------
//			Percent Constants (x% * 65536)
//--------------------------------------------------

#define	ZERO_PERCENT			0
#define	HALF_PERCENT			328
#define	ONE_PERCENT				655
#define	TWO_PERCENT				1311
#define	TWO_HALF_PERCENT		1638
#define	FIVE_PERCENT			3277
#define	TEN_PERCENT				6554
#define	TWELVE_PERCENT			7864
#define	FIFTEEN_PERCENT			9830
#define	TWENTY_PERCENT			13107
#define	TWENTY_FIVE_PERCENT		16384
#define	THIRTY_THREE_PERCENT	21627
#define	FORTY_PERCENT			26214
#define	FIFTY_PERCENT			32768
#define	SIXTY_PERCENT			39322
#define	SIXTY_SIX_PERCENT		43253
#define	SEVENTY_PERCENT			45875
#define	SEVENTY_FIVE_PERCENT	49152
#define	EIGHTY_PERCENT			52429
#define	EIGHT_FIVE_PERCENT		55706
#define	NINTY_PERCENT			58982
#define	NINTY_FIVE_PERCENT		62259
#define	NINTY_SEVEN_HALF_PERCENT 63898
#define	NINTY_EIGHT_PERCENT		64225
#define	NINTY_NINE_PERCENT		64881

#endif	// _FS400_H_