em847x.h

这是一个SIGMA方案的PMP播放器的UCLINUX程序,可播放DVD,VCD,CD MP3...有很好的参考价值.

/*****************************************************************************
*  em847x.h : definitions for EM847X only
*  REALmagic Quasar Hardware Library
*  Created by Aurelia Popa-Radu
*  Copyright Sigma Designs Inc
*  Sigma Designs Proprietary and confidential
*  Created on 08/01/01
*  Description:
*****************************************************************************/

#ifndef __EM847X_H__
#define __EM847X_H__

#ifdef __cplusplus
extern "C"{
#endif 

// flags for display filters
#define Q4CTRL1_4TAP_VERT_UP_DOWN	BIT6
#define Q4CTRL1_BILIN_VERT_UP_DOWN	BIT3
#define Q4CTRL1_BILIN_HORZ_UP		BIT2

// QPM_to_host_master_ena register
#define Port1_to_MasterWriteToHost		0x0001
#define Port1_to_SlaveWriteToHost		0x0000
#define Port2_to_MasterWriteToHost		0x0000
#define Port2_to_SlaveWriteToHost		0x0001

// related values to DRAM_portmux
#define DRAM_portmux_CHW0_Mask			0x0003
#define DRAM_portmux_W0_to_CHW0			0x0000
#define DRAM_portmux_W0a_to_CHW0		0x0001
#define DRAM_portmux_W0b_to_CHW0		0x0002

#define DRAM_portmux_CHW3_Mask			0x000c
#define DRAM_portmux_W3_to_CHW3			0x0000
#define DRAM_portmux_W3a_to_CHW3		0x0004
#define DRAM_portmux_W3b_to_CHW3		0x0008

#define DRAM_portmux_CHW4_Mask			0x0030
#define DRAM_portmux_W4_to_CHW4			0x0000
#define DRAM_portmux_W4a_to_CHW4		0x0010
#define DRAM_portmux_W4b_to_CHW4		0x0020
#define DRAM_portmux_W4c_to_CHW4		0x0030	// only for em848x

#define DRAM_portmux_CHR0_Mask			0x0040
#define DRAM_portmux_CHR0_to_r0			0x0000
#define DRAM_portmux_CHR0_to_r0a		0x0040

#define DRAM_portmux_VCLuma_to_CHW0		DRAM_portmux_W0a_to_CHW0
#define DRAM_portmux_VCChroma_to_CHW3	DRAM_portmux_W3a_to_CHW3
#define DRAM_portmux_VCChroma_to_CHW4	DRAM_portmux_W4c_to_CHW4	// only for em848x
#define DRAM_portmux_CHR0_to_LWCH0		DRAM_portmux_CHR0_to_r0a
#define DRAM_portmux_CHR0_to_Port1		DRAM_portmux_CHR0_to_r0

// defines video PLL register
#define USE_VIDEO_PLL_FOR_VCLK		0x8000	// bit15= use PLL for VClk
#define USE_EXTVCLK_FOR_VCLK		0x0000	//
#define Q4_POWER_UP_VIDEO_PLL		0x4000	// bit14= power up PLL
// Fout = FRef*(N+2)/(M+2), where N = bits 7..0, M = bits 13..8

// EM847x changes bit14 from powerdown to power up PLL

// defines video capture registers
#define VC_cfg_601					0x0001
#define VC_cfg_656					0x0000
#define VC_cfg_420					0x0002
#define VC_cfg_422					0x0000
#define VC_cfg_PackLuma				0x0004
#define VC_cfg_UnPackLuma			0x0000
#define VC_cfg_PackChroma			0x0008
#define VC_cfg_UnPackChroma			0x0000
#define VC_cfg_Interlaced			0x0010	// only for 601
#define VC_cfg_NonInterlaced		0x0000
#define VC_cfg_16bits				0x0020
#define VC_cfg_8bits				0x0000
#define VC_cfg_Zoom					0x0040
#define VC_cfg_NoZoom				0x0000
#define VC_cfg_Mpeg2				0x0080
#define VC_cfg_Mpeg1				0x0000
#define VC_cfg_HSyncHi				0x0100
#define VC_cfg_HSyncLo				0x0000
#define VC_cfg_VSyncHi				0x0200
#define VC_cfg_VSyncLo				0x0000
#define VC_cfg_VSyncActiveLeadingEdge	0x0400
#define VC_cfg_VSyncActiveTrailingEdge	0x0000

#define VC_inf_VSyncIntReset		0x8000

// defines related with LBC_interrupt_reg
#define LBC_SM_INTR_ENABLE				0x0010
#define LBC_SM_DMAREQ_ENABLE			0x0020
#define LBC_FSGPIO_ENABLE				0x0040	//??
#define LBC_AUDIO_INTR_ENABLE			0x0080	//??

#define LBC_SM_INTR_ACTIVE_HI			0x0000
#define LBC_SM_INTR_ACTIVE_LO			0x0100
#define LBC_SM_DMAREQ_ACTIVE_HI			0x0000
#define LBC_SM_DMAREQ_ACTIVE_LO			0x0200

#define INFO_SM_SLAVE					0x0000
#define INFO_SM_MASTER					0x0001
#define INFO_SM_WAIT_TXFIFO				0x0002
#define INFO_SM_PARAMS					0x0004
#define INFO_SM_WAIT_TXFIFO_PARAMS		0x0008
#define INFO_SM_START					0x0010
#define INFO_SM_WAIT_TXFIFO_CMD			0x0020
#define INFO_SM_XFER_UCODE_IO			0x0040
#define INFO_SM_XFER_UCODE_BURST_DRAM	0x0080
#define INFO_SM_XFER_UCODE_BURST_SYS	0x0100

// defines related with LBC_config
#define LBC_config_LG					0x0000	// bits 0,1
#define LBC_config_Kfir					0x0001
#define LBC_config_Sm2288				0x0002

#define LBC_config_swap_bytes			0x0004	// bits 2

#define LBC_config_delay_0				0x0000	// bits 5,6,7
#define LBC_config_delay_1				0x0020
#define LBC_config_delay_2				0x0040
#define LBC_config_delay_4				0x0080

#define LBC_config_LWCH0_to_R0a			0x0000
#define LBC_config_LWCH0_to_W4			0x0200
#define LBC_config_LRCH0_to_W0b			0x0000
#define LBC_config_LRCH0_to_W4a			0x0400
#define LBC_config_LRCH0_to_W0b_Port1	0x0800
#define LBC_config_LRCH0_to_W4a_Port1	0x0c00
#define LBC_config_LRCH0_to_Port1		0x1000
#define LBC_config_LRCH0_to_Port2		0x1400
#define LBC_config_LRCH0_to_W0b_Port2	0x1800
#define LBC_config_LRCH0_to_W4a_Port2	0x1c00

#define LBC_config_LRCH1_to_W3b			0x0000
#define LBC_config_LRCH1_to_W4b			0x2000
#define LBC_config_LRCH1_to_W3b_Port1	0x4000
#define LBC_config_LRCH1_to_W4b_Port1	0x6000
#define LBC_config_LRCH1_to_Port1		0x8000
#define LBC_config_LRCH1_to_Port2		0xa000
#define LBC_config_LRCH1_to_W3b_Port2	0xc800
#define LBC_config_LRCH1_to_W4b_Port2	0xe000

// defines related with the transfer path of the LBC transfer
#define Sm2288_Interface		LBC_config_Sm2288		// bits 0,1
#define LBC_Swap_Bytes			LBC_config_swap_bytes	// bit 2

#define LBC_dma_delay_0			LBC_config_delay_0		// bits 5,6,7

#define Dma_Transfer			0x80000000	// bit 31
#define IO_Transfer				0x00000000
#define SM2288_INTEL_BURST		0x8000		// same as DMA_START for Sm2288

#define Data_Type				0x0F00	// bits 8..11
#define Audio_Raw				0x0400
#define Audio_Cbs				0x0500
#define Video_Cbs				0x0600
#define Mux_Cbs					0x0700

#define LRCH0_Port1_HostMaster	0x00000000	// bits 16..23
#define LRCH0_Port2_HostMaster	0x00010000
#define LRCH0_Port1_HostSlave	0x00020000
#define LRCH0_Port2_HostSlave	0x00030000

#define LRCH1_Port1_HostMaster	0x00040000
#define LRCH1_Port2_HostMaster	0x00050000
#define LRCH1_Port1_HostSlave	0x00060000
#define LRCH1_Port2_HostSlave	0x00070000

// types to define the transfer to StreamMachine
#define HostMaster_W4_LWCH0_Dram	0x00080000
#define HostMaster_W4_LWCH0_Ucode	0x00090000
#define Dram_CHR0_LWCH0_Dram		0x000A0000
#define Dram_CHR0_LWCH0_Ucode		0x000B0000

#define Q3CTRL3_PCLK_DIVIDE_BY_2		0x8000
#define Q3CTRL3_DIGITAL_OUTPUT_24BIT	0x1000

// for sigma TV
#define DACS_MASK		0x0400
#define Q4_DACS_DISABLE	0x0000	// bit inverted
#define Q4_DACS_ENABLE	0x0400	// bit inverted
#define PICT_SYNC_OFF	0x00c0

#ifndef  EM8xxx_AudioPLL_N_48000
	// Aclk256 = Fin * m/(2*(m+n)), where Fin=mclk.
	// For 85.5 MHz, mclk is 128.25MHz.
	#define  EM8xxx_AudioPLL_N_8000  62077	// 15.59
	#define  EM8xxx_AudioPLL_M_8000   2048
	#define  EM8xxx_AudioPLL_N_11025 34057	// 28.07
	#define  EM8xxx_AudioPLL_M_11025  1568
	#define  EM8xxx_AudioPLL_N_12000 61053	// 15.59
	#define  EM8xxx_AudioPLL_M_12000  3072

	#define  EM8xxx_AudioPLL_N_16000 60029	// 15.59
	#define  EM8xxx_AudioPLL_M_16000  4096
	#define  EM8xxx_AudioPLL_N_22050 64978	// 14.03
	#define  EM8xxx_AudioPLL_M_22050  6272
	#define  EM8xxx_AudioPLL_N_24000 57981	// 15.59
	#define  EM8xxx_AudioPLL_M_24000  6144

	#define  EM8xxx_AudioPLL_N_32000 55933	// 15.59
	#define  EM8xxx_AudioPLL_M_32000  8192
	#define  EM8xxx_AudioPLL_N_44100 58706	// 14.03
	#define  EM8xxx_AudioPLL_M_44100 12544
	#define  EM8xxx_AudioPLL_N_48000 51837	// 15.59
	#define  EM8xxx_AudioPLL_M_48000 12288

	#define  EM8xxx_AudioPLL_N_64000 47741	// 15.59
	#define  EM8xxx_AudioPLL_M_64000 16384
	#define  EM8xxx_AudioPLL_N_88200 46162	// 14.03
	#define  EM8xxx_AudioPLL_M_88200 25088
	#define  EM8xxx_AudioPLL_N_96000 39549	// 15.59
	#define  EM8xxx_AudioPLL_M_96000 24576
#endif

#ifdef __cplusplus
}
#endif 

#endif