fip_private.h

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/*
 * fip_private.h
 */

#ifndef _FIP_PRIVATE_H_
#define _FIP_PRIVATE_H_

#include <cyg/infra/diag.h>
#include <cyg/infra/cyg_ass.h>
#include <cyg/hal/hal_diag.h>
#include <cyg/kernel/kapi.h>

//XXX Fix all this
#include <cyg/hal/hal_jasper.h>

#define QUASAR_DRAM_PLLCONTROL_REG              ( (volatile unsigned int * ) (JASPER_QUASAR_BASE + QUASAR_DRAM_PLLCONTROL) )

#define PIO_0_INT_STATUS_REG                    ( (volatile unsigned int * ) (JASPER_PIO0_BASE + PIO_INT) )
#define PIO_0_DATA_REG                          ( (volatile unsigned int * ) (JASPER_PIO0_BASE + PIO_DATA) )
#define PIO_0_DIR_REG                           ( (volatile unsigned int * ) (JASPER_PIO0_BASE + PIO_DIR) )
#define PIO_0_POL_REG                           ( (volatile unsigned int * ) (JASPER_PIO0_BASE + PIO_POL) )
#define PIO_0_INT_ENABLE_REG                    ( (volatile unsigned int * ) (JASPER_PIO0_BASE + PIO_INTEN) )

#define PIO_1_INT_STATUS_REG                    ( (volatile unsigned int * ) (JASPER_PIO1_BASE + PIO_INT) )
#define PIO_1_DATA_REG                          ( (volatile unsigned int * ) (JASPER_PIO1_BASE + PIO_DATA) )
#define PIO_1_DIR_REG                           ( (volatile unsigned int * ) (JASPER_PIO1_BASE + PIO_DIR) )
#define PIO_1_POL_REG                           ( (volatile unsigned int * ) (JASPER_PIO1_BASE + PIO_POL) )
#define PIO_1_INT_ENABLE_REG                    ( (volatile unsigned int * ) (JASPER_PIO1_BASE + PIO_INTEN) )

#define TIMER_TMRSTAT_REG                       ( (volatile unsigned int * ) (JASPER_TIMER_BASE + TIMER_TMRSTAT) )
#define TIMER1_CNTL_REG                         ( (volatile unsigned int * ) (JASPER_TIMER_BASE + TIMER_TMR1CTL) )
#define TIMER1_LOAD_REG                         ( (volatile unsigned int * ) (JASPER_TIMER_BASE + TIMER_TMR1LOAD) )
#define TIMER0_CNTL_REG                         ( (volatile unsigned int * ) (JASPER_TIMER_BASE + TIMER_TMR0CTL) )
#define TIMER0_LOAD_REG                         ( (volatile unsigned int * ) (JASPER_TIMER_BASE + TIMER_TMR0LOAD) )
#define TIMER0_VAL_REG                         ( (volatile unsigned int * ) (JASPER_TIMER_BASE + TIMER_TMR0VAL) )


#define FIP_COMMAND_REG                         ( (volatile unsigned int * ) (JASPER_FIP_BASE + FIP_COMMAND) )
#define FIP_DISPLAY_DATA_REG                    ( (volatile unsigned int * ) (JASPER_FIP_BASE + FIP_DISPLAY_DATA) )
#define FIP_LED_DATA_REG                        ( (volatile unsigned int * ) (JASPER_FIP_BASE + FIP_LED_DATA) )
#define FIP_KEY_DATA1_REG                       ( (volatile unsigned int * ) (JASPER_FIP_BASE + FIP_KEY_DATA1) )
#define FIP_KEY_DATA2_REG                       ( (volatile unsigned int * ) (JASPER_FIP_BASE + FIP_KEY_DATA2) )
#define FIP_SWITCH_DATA_REG                     ( (volatile unsigned int * ) (JASPER_FIP_BASE + FIP_SWITCH_DATA) )
#define FIP_CLK_DIV_REG                         ( (volatile unsigned int * ) (JASPER_FIP_BASE + FIP_CLK_DIV) )
#define FIP_TRISTATE_MODE_REG                   ( (volatile unsigned int * ) (JASPER_FIP_BASE + FIP_TRISTATE_MODE) )


#define FIP_CMD_DISP_MODE_08DIGITS_20SEGMENTS           0x00
#define FIP_CMD_DISP_MODE_09DIGITS_19SEGMENTS           0x08
#define FIP_CMD_DISP_MODE_10DIGITS_18SEGMENTS           0x09
#define FIP_CMD_DISP_MODE_11DIGITS_17SEGMENTS           0x0a
#define FIP_CMD_DISP_MODE_12DIGITS_16SEGMENTS           0x0b
#define FIP_CMD_DISP_MODE_13DIGITS_15SEGMENTS           0x0c
#define FIP_CMD_DISP_MODE_14DIGITS_14SEGMENTS           0x0d
#define FIP_CMD_DISP_MODE_15DIGITS_13SEGMENTS           0x0e
#define FIP_CMD_DISP_MODE_16DIGITS_12SEGMENTS           0x0f


#define FIP_CMD_DATA_SET_RW_MODE_WRITE_DISPLAY          0x40
#define FIP_CMD_DATA_SET_RW_MODE_WRITE_LED_PORT         0x41
#define FIP_CMD_DATA_SET_RW_MODE_READ_KEYS              0x42
#define FIP_CMD_DATA_SET_RW_MODE_READ_SWITCHES          0x43
#define FIP_CMD_DATA_SET_ADR_MODE_INCREMENT_ADR         0x40
#define FIP_CMD_DATA_SET_ADR_MODE_FIXED_ADR             0x44
#define FIP_CMD_DATA_SET_OP_MODE_NORMAL_OPERATION       0x40
#define FIP_CMD_DATA_SET_OP_MODE_TEST_MODE              0x48

#define FIP_CMD_ADR_SETTING                             0xC0

#define FIP_CMD_DISP_CTRL_PULSE_WIDTH_1_16              0x80
#define FIP_CMD_DISP_CTRL_PULSE_WIDTH_2_16              0x81
#define FIP_CMD_DISP_CTRL_PULSE_WIDTH_4_16              0x82
#define FIP_CMD_DISP_CTRL_PULSE_WIDTH_10_16             0x83
#define FIP_CMD_DISP_CTRL_PULSE_WIDTH_11_16             0x84
#define FIP_CMD_DISP_CTRL_PULSE_WIDTH_12_16             0x85
#define FIP_CMD_DISP_CTRL_PULSE_WIDTH_13_16             0x86
#define FIP_CMD_DISP_CTRL_PULSE_WIDTH_14_16             0x87
#define FIP_CMD_DISP_CTRL_TURN_DISPLAY_OFF_MASK         0x87
#define FIP_CMD_DISP_CTRL_TURN_DISPLAY_ON               0x88

#define DPRINTF(x...) diag_printf(x)
#define FIP_ASSERT(x) CYG_ASSERT(x, #x)
#define FIP_DELAY(us) HAL_DELAY_US(1000*us)

#define FIP_LOCK()      cyg_interrupt_mask(CYGNUM_HAL_INTERRUPT_WDTIMER);
#define FIP_UNLOCK()    cyg_interrupt_unmask(CYGNUM_HAL_INTERRUPT_WDTIMER);

#define FIP_FIFO_LOCK()                                              \
do {                                                                 \
	    cyg_interrupt_mask(CYGNUM_HAL_INTERRUPT_WDTIMER);            \
	    cyg_interrupt_mask(CYGNUM_HAL_INTERRUPT_PIO0);               \
} while(0)

#define FIP_FIFO_UNLOCK()                                            \
do {                                                                 \
	    cyg_interrupt_unmask(CYGNUM_HAL_INTERRUPT_WDTIMER);          \
	    cyg_interrupt_unmask(CYGNUM_HAL_INTERRUPT_PIO0);             \
} while(0)

extern cyg_flag_t fip_flag;
#define FIP_FIFO_WAIT(timeout) cyg_flag_timed_wait(&fip_flag, 0x1, CYG_FLAG_WAITMODE_OR | CYG_FLAG_WAITMODE_CLR, cyg_current_time() + timeout)

#endif /* _FIP_PRIVATE_H_ */