mstar.c

LCD OSD 程序用於8051 開發lcd

    { mStar_WriteByte(HS_LVL, 0x00); // setup ADC bandwidth
      mStar_WriteByte(BWCOEF, 0x01);   // setup ADC
      mStar_WriteByte(DCOEF,    0x03);
    }
  mStar_WriteByte(REGBK, REGBANKSCALER); // switch to scaler bank
}

//*******************************************************************
// Function Name: mStar_SetScalingFactor
//
// Decscription: setup scaler hor/ver scaling factor to expand image to full screen
//
// caller: mSar_WriteByte(), mStar_ReadByte() in ms_rwreg.c
///
// callee: mStar_SetupMode() in mstar.c
//*******************************************************************
#define HSC_offset	1
void mStar_SetScalingFactor(void)
{ DWORD factor;
  WORD width, height;

  width=mStar_ReadWord(SPRHDC_H);
  height=mStar_ReadWord(SPRVDC_H);
  if (SrcFlags&bInterlaceMode)
    height/=2; // if input timing is interlace, must use 1/2 height to get scaler factor
//  if (width==640)
//    mStar_WriteWord(SPRHDC_H, width+1);
  // Setup horizontal expansion
  if (width!=PanelWidth) // set expansion factor
    { factor=width-HSC_offset; // factor=((input width-1)*2^20)/(output width-1) + 1
      factor=((DWORD)(factor<<20))/(PanelWidth-HSC_offset)+1;
      mStar_WriteWord(SRH_M, factor&0xFFFF);
      mStar_WriteByte(SRH_H, ((factor>>16)&0xFF)|SENH_B);
    }
  else
    mStar_WriteByte(SRH_H, 0); // input width=output width, then disable expansion
  // Setup vertical expansion
  if (height!=PanelHeight)
    { factor=height-1; // factor=((input height-1)*2^20)/(output height-1) + 1
      factor=((DWORD)(factor<<20))/(PanelHeight-1)+1;
      mStar_WriteWord(SRV_M, factor&0xFFFF);
      mStar_WriteByte(SRV_H, ((factor>>16)&0xFF)|SENV_B);
    }
  else
    mStar_WriteByte(SRV_H, 0); // input height=output height, then disable expansion
//  mStar_WriteByte(FTAPEN, 1);		// enable 3-tap filter.
}

//*******************************************************************
// Function Name: mStar_ResetDClkPLL
//
// Decscription: Reset output PLL to prevent from PLL works abnormally by
//               toggle power down/on of PLL
//
// caller: mSar_WriteByte(), mStar_ReadByte() in ms_rwreg.c
///
// callee: mStar_SetupMode() in mstar.c
//*******************************************************************
void mStar_ResetDClkPLL(void)
{ BYTE regByte;

  regByte=mStar_ReadByte(PLLCTRL2);
  Delay1ms(10);
  mStar_WriteByte(PLLCTRL2, regByte|LP_PD_B); // force PLL power down
  Delay1ms(10);
  mStar_WriteByte(PLLCTRL2, regByte); // then re-enable PLL
}

//*******************************************************************
// Function Name: mStar_SetPanelTiming
//
// Decscription: Setup panel output dclk.
//
// callee: mStar_ResetDClkPLL() in mstar.c
//         mSar_ReadWord(), mStar_WriteWord(), mStar_WriteByte() in ms_rwreg.c
//
// caller: mStar_SetupMode() in mstar.c
//*******************************************************************
#define MST_HPeriod_UINT	MST_CLOCK_MHZ*16


#if UseNewPanelTiming

Bool mStar_SetPanelTiming(void)
{ DWORD factor;
  WORD hPeriod;
  BYTE regByte;
  WORD sclk;
  OutputFactorType	OutputFactor;

  //======================================================
  mStar_WriteByte(REGBK, REGBANKADC);
  mStar_WriteByte(TESTEN, TSTEN_B);
  if (SrcInputType!=Input_Digital)
    { sclk=((DWORD)UserPrefHTotal*MST_CLOCK_MHZ)/((DWORD)SrcHPeriod*1000);
      if (sclk<20)
        mStar_WriteByte(VCOCTRL, 0x05); // set VCO range
      else if (sclk>140)
        mStar_WriteByte(VCOCTRL, 0x35); // set VCO range
      else
        mStar_WriteByte(VCOCTRL, 0x15); // set VCO range

      if (sclk>173)
        mStar_WriteByte(TESTA3, 0xC0);
      else
      	mStar_WriteByte(TESTA3, 0x00);
    }
  else
    { sclk=0;
      mStar_WriteByte(TESTA3, 0x00);
    }

  mStar_WriteByte(TESTEN, 0x00);
  mStar_WriteByte(REGBK, REGBANKSCALER);
  //======================================================
  regByte=mStar_ReadByte(ISCTRL);
  if (sclk>165)
    mStar_WriteByte(ISCTRL, regByte|SCKI_B);
  else
    mStar_WriteByte(ISCTRL, regByte&~SCKI_B);
//===============================================================
  // for getting more accurate output htotal
  if (SrcHPeriod>511) // avoid overflow
    hPeriod=SrcHPeriod*16;
  else
    { regByte=GetVSyncTime()*3;
      mStar_WriteByte(HSPRD_H, IHDM_B); // enable 16 line line to calculate hsync period.
      Delay1ms(regByte);
      hPeriod=mStar_ReadWord(HSPRD_H)&0x1FFF;
      if (abs(hPeriod/16-SrcHPeriod)>5)
        hPeriod=SrcHPeriod*16;
      mStar_WriteByte(HSPRD_H, 0);
      Delay1ms(regByte);
    }
  // ***** IMPORTANT: must make sure the following is correct.
  OutputFactor.Flags=15;
  if (SrcFlags&bInterlaceMode) // set interlace mode
    OutputFactor.Flags|=BIT6;
  if (PanelLVDS) // set LVDS output
    OutputFactor.Flags|=BIT7;
  //******************************************************
  OutputFactor.MST_Clock_MHz=MST_CLOCK_MHZ;
  OutputFactor.expHTotal=PanelMinHTotal;
  OutputFactor.srcHPeriod=hPeriod;
  OutputFactor.PnlWidth=PanelWidth;
  OutputFactor.PnlHeight=PanelHeight;
  OutputFactor.PnlMaxDClk=PanelMaxDCLK;
  if (SetOutputDClk(&OutputFactor, &factor)==FALSE)
    return FALSE;

#if (!PanelRSDS && !PanelDualPort)
  factor/=2;
#endif
  // program LPLL parameters to generate expected output dclk
  mStar_WriteWord(LPLL_SET_M, factor&0xFFFF);
  mStar_WriteByte(LPLL_SET_H, factor>>16);
  mStar_WriteByte(ISELECT, mStar_ReadByte(ISELECT)&(~NIS_B));// enable lock input mode

  mStar_ResetDClkPLL(); // reset output PLL to prevent PLL works abnormally

  return TRUE;
 }

#else

Bool mStar_SetPanelTiming(void)
{ DWORD factor;
  WORD dclk;
  WORD sclk;
  WORD height;
  WORD dstHTotal;
  WORD hPeriod;

  // for getting more accurate output htotal
  sclk=GetVSyncTime()*3;
  mStar_WriteByte(HSPRD_H, IHDM_B); // enable 16 line line to calculate hsync period.
  Delay1ms(sclk);
  hPeriod=mStar_ReadWord(HSPRD_H)&0x1FFF;
  mStar_WriteByte(HSPRD_H, 0);
  Delay1ms(sclk);

  // calculate input timing dot clock for comparing with output dot clock
  sclk=0;
  if (mStar_ReadWord(SPRHDC_H)<PanelWidth || mStar_ReadWord(SPRVDC_H)<PanelHeight)
    sclk=((DWORD)UserPrefHTotal*MST_HPeriod_UINT)/((DWORD)hPeriod*1000);
  printData("input sclk %d", sclk);

  height=mStar_ReadWord(SPRVDC_H);
  if (SrcFlags&bInterlaceMode)
    height/=2;
  dstHTotal=PanelMinHTotal;

#if FixDClk // Fixed output dclk method: output clock will be fixed no matter what input timing is
  { // according to output clock to calculate output htotal
    dclk=OutDClk1;
    dstHTotal=((float)hPeriod*dclk*(height-1)*1000ul)/((float)(PanelHeight-1)*MST_HPeriod_UINT);

    //printData("dclk1 output htotal %d", dstHTotal);
    if (dstHTotal<PanelMinHTotal) // if input htotal is samll than panel htotal, then set to another dclk
      { dclk=OutDClk2;
        dstHTotal=((float)hPeriod*dclk*(height-1)*1000ul)/((float)(PanelHeight-1)*MST_HPeriod_UINT);
        //printData("dclk2 output htotal %d", dstHTotal);
      }
    dstHTotal&=0xFFFE; // make output htotal as even
    // if the htotal is out of panel htotal, then use the panel minimum htotal
    if (dstHTotal<PanelMinHTotal || dstHTotal>PanelMaxHTotal)
      dstHTotal=PanelMinHTotal;
  }
#endif
  if (sclk)
    { // in expansion mode, chip will assume output clock is faster than input clock,
      // if input clock is faster than output clock, must make output clock faster than input clock
      factor=((float)dstHTotal*(PanelHeight-1)*MST_HPeriod_UINT)/((DWORD)hPeriod*(height-1)); // output dclk
      dclk=(factor+500)/1000;
      printData("output dclk %d", dclk);
      if (dclk>PanelMaxDCLK) // if ouput clock is out of panel, then enable unsupported flag
      	{ SrcFlags|=bUnsupportMode;
      	  return FALSE;
      	}

    #if ChipID==ChipNone
      if (dclk<(sclk+3))
        { // output clock is slow than input clock, so fast output clock
          factor+=(sclk+3-dclk)*1000;
          dstHTotal=((float)hPeriod*factor*(height-1))/((float)MST_HPeriod_UINT*(PanelHeight-1));
          if (dstHTotal%4)
            dstHTotal=(dstHTotal/4+1)*4;
        //  printData("output 1 htotal %d", dstHTotal);
      	}
    #endif
    }

{ // used for support frequency over 173MHz, and native mode
#define	MPLL_Divider	15
  if (sclk==0)
    sclk=((DWORD)UserPrefHTotal*MST_HPeriod_UINT)/((DWORD)hPeriod*1000);

  mStar_WriteByte(REGBK, REGBANKADC);
  mStar_WriteByte(TESTEN, TSTEN_B);
  if (SrcInputType!=Input_Digital)
    { if (sclk<20)
        mStar_WriteByte(VCOCTRL, 0x05); // set VCO range
      else if (sclk>140)
        mStar_WriteByte(VCOCTRL, 0x35); // set VCO range
      else
        mStar_WriteByte(VCOCTRL, 0x15); // set VCO range

      if (sclk>173)
        mStar_WriteByte(TESTA3, 0xC0);
      else
      	mStar_WriteByte(TESTA3, 0x00);
    }
  else
    mStar_WriteByte(TESTA3, 0x00);

  mStar_WriteByte(TESTEN, 0x00);
  mStar_WriteByte(REGBK, REGBANKSCALER);

#define regByte		dclk
  regByte=mStar_ReadByte(ISCTRL);
  if (sclk>165)
    mStar_WriteByte(ISCTRL, regByte|SCKI_B);
  else
    mStar_WriteByte(ISCTRL, regByte&~SCKI_B);
#undef regByte

#if PanelLVDS
  factor=((float)hPeriod*524288ul*MPLL_Divider*(height-1))/((float)dstHTotal*7*(PanelHeight-1)); // 2^23
#else
  factor=((float)hPeriod*65536ul*MPLL_Divider*(height-1))/((float)dstHTotal*(PanelHeight-1)); // 2^20
#endif
#undef MPLL_Divider
}

#if (!PanelRSDS && !PanelDualPort)
  factor/=2;
#endif
  // program LPLL parameters to generate expected output dclk
  mStar_WriteWord(LPLL_SET_M, factor&0xFFFF);
  mStar_WriteByte(LPLL_SET_H, factor>>16);
  mStar_WriteByte(ISELECT, mStar_ReadByte(ISELECT)&(~NIS_B));// enable lock input mode

//jon add imformation with QDI panel
#if PanelQDI17L
  FixShortLine(); 
  #endif       
  

  mStar_ResetDClkPLL(); // reset output PLL to prevent PLL works abnormally

  return TRUE;
}

#endif


//*******************************************************************
// Function Name: mStar_PowerUp
//
// Decscription: Power on chip from power down mode
//
// callee: mStar_WriteByte() in ms_rwreg.c
//
// caller: Power_PowerOnSystem() in power.c
//*******************************************************************
void mStar_PowerUp(void)
{ //mStar_WriteByte(TRISTATE, 0x00);
  mStar_WriteByte(PLLCTRL2, 0); // power on master & output PLL
  mStar_WriteByte(PDMD, 0);// power on chip from power down mode
#if ADC2Sets
  mStar_WriteByte(REGBK, REGBANKADC);
  mStar_WriteByte(TESTEN, TSTEN_B);
  mStar_WriteByte(TESTA5, 0);
  mStar_WriteByte(TESTA6, 0);
  mStar_WriteByte(TESTMOD, 0x00);//0x08);//0x40);
  mStar_WriteByte(TESTEN, 0);
  mStar_WriteByte(REGBK, REGBANKSCALER);
#endif
  mStar_WriteByte(SWRST, GPR_B|ADCR_B); // reset graphic port RO register
  mStar_WriteByte(SWRST, 0);
}

//*******************************************************************
// Function Name: mStar_PowerDown
//
// Decscription: Power down chip
//
// callee: mStar_WriteByte() in ms_rwreg.c
//
// caller: Power_PowerOffSystem() in power.c
//*******************************************************************
void mStar_PowerDown(void)
{ mStar_WriteByte(TRISTATE, 0xFF);// tri-state all output panel signal

#if ADC2Sets
  { BYTE regByte=0x9E;//OVRD_B|DPLBG_B|DMIBEX_B|PHD_B|DMUX_B;

    mStar_WriteByte(PLLCTRL2, MP_PD_B|LP_PD_B);
    if (SrcInputType==Input_Digital)
      regByte=0x86;
    else if (SrcInputType==Input_Analog2)
      regByte|=AMUX_B;
    mStar_WriteByte(REGBK, REGBANKADC);
    mStar_WriteByte(TESTEN, TSTEN_B);
    mStar_WriteByte(TESTA5, regByte);
    mStar_WriteByte(TESTA6, 0xF8);//0xE8);
    mStar_WriteByte(TESTEN, 0);
    mStar_WriteByte(REGBK, REGBANKSCALER);
  }
  mStar_WriteByte(PDMD, PDDS_B|0x2);// power down chip except mode detection
#else
  mStar_WriteByte(PDMD, PDDS_B|0x3);// power down chip except mode detection
#endif
}

//*******************************************************************
// Function Name: mStar_InitADC
//
// Decscription: Initialize ADC bank registers
//
// callee: mStar_WriteByte() in ms_rwreg.c
//
// caller: mStar_Init() in mStar.c
//*******************************************************************
void mStar_InitADC(void)